第三代半导体GaN功率开关器件的发展现状及面临的挑战

氮化镓(GaN)材料具有优异的物理特性,非常适合于制作高温、高速和大功率电子器件,具有十分广阔的市场前景。Si衬底上GaN基功率开关器件是目前的主流技术路线,其中结型栅结构(p型栅)和共源共栅级联结构(Cascode)的常关型器件已经逐步实现产业化,并在通用电源及光伏逆变等领域得到应用。但是鉴于以上两种器件结构存在的缺点,业界更加期待能更充分发挥GaN性能的"真"常关MOSFET器件。而GaN MOSFET器件的全面实用化,仍然面临着在材料外延方面和器件稳定性方面的挑战。     

基于SiON/Al2O3叠层介质的薄势垒型HEMT栅极相关可靠性研究

氮化镓(gallium nitride,GaN)材料因其优秀的物理特性受到越来越多研究者的青睐,但常关型GaN基高电子迁移率晶体管(high electron mobility transistor,HEMT)技术发展尚处于初级阶段。文中的研究对象是薄势垒常关型HEMT,该类器件可以很大程度地降低栅极区域的刻蚀损伤,因此在未来的电力电子市场中极具潜力。文中工作中制备基于SiON/Al2O3叠层栅介质的薄势垒型HEMT器件,在叠层介质的帮助下,器件的阈值电压与肖特基栅极器件几乎一致,可以实现常关型操作。其最大关态击穿电压可以达到700V,栅极耐压超过23V,在超过1000s的正栅应力测试中阈值电压漂移量小于1V。通过对其关态击穿、栅极击穿、栅极应力测试等特性的分析,对其可靠性方面有更为深入的认识,同时进一步地展现出薄势垒HEMT器件的结构优势。     

具有高阈值电压和超低栅漏电的400V常关型槽栅AlGaN/GaN金属氧化物半导体高电子迁移率晶体管（英文）

介绍了一种采用ICP干法刻蚀技术制备的槽栅常关型AlGaN/GaN金属氧化物半导体高电子迁移率晶体管(MOS-HEMT)。采用原子层淀积(ALD)实现40 nm的栅介质的沉积。槽栅常关型AlGaN/GaN MOS-HEMT的阈值电压为+4.3 V。在栅压时,槽栅常关型AlGaN/GaN MOS-HEMT饱和电流为0.71 A,特征导通电阻为5.73 m?·cm~2。在栅压时,器件的击穿电压为400 V,关断漏电流为320μA。器件的开启与关断电流比超过了109。在栅压为-20 V时,槽栅常关型AlGaN/GaN MOS-HEMT的栅漏电流为1.8 n A。高的开启与关断电流比和低的栅漏电流反映了界面具有很好的质量。     

六英寸Si基GaN功率电子材料及器件的制备与研究

氮化镓(GaN)作为第三代半导体材料的代表,具有优异的材料物理特性,更加适合于下一代电力电子系统对功率开关器件更大功率、更高频率、更小体积和更恶劣工作温度的要求。为了兼容Si基CMOS工艺流程,以及考虑到大尺寸、低成本等优势,在Si衬底上进行GaN材料的异质外延及器件制备已经成为业界主要技术路线。详细介绍了在6英寸Si衬底上外延生长的AlGaN/GaN HEMT结构功率电子材料,以及基于6英寸CMOS产线制造Si基GaN功率MIS-HEMT和常关型Cascode GaN器件的相关成果。     

GaN功率开关器件的产业发展动态

氮化镓(GaN)功率电子器件具有优异的电学特性,在高速、高温和大功率领域具有十分广阔的应用前景,满足下一代功率管理系统对高效节能、小型化和智能化的需求。P型栅和Cascode结构的常关型GaN器件已逐步实现产业化,但鉴于这两种器件结构本身存在的缺点,常关型GaN MOSFET器件方案备受关注。目前,GaN功率开关器件主要朝高频化发展,封装形式从直插型(TO)封装向贴片式(QFN)封装演变,为进一步消除寄生效应对器件高速开关特性造成的不良影响,驱动和功率器件集成的GaN功率集成电路(IC)技术被采用,单片集成的全GaN功率IC是未来的发展方向。     

4H-SiC LDMOSFET沟道迁移率影响因素的研究

为了研究4H-SiC金属氧化物半导体场效应晶体管（MOSFET）沟道迁移率和界面态密度的影响因素,通过在N型4H-SiC（0001）外延片上制备不同沟道长度和宽度的横向扩散MOSFET（LDMOSFET）,其干氧氧化的栅极氧化层在不同温度和时间的NO和/或N₂气氛中退火,测试了其输出和转移曲线,提取了有效迁移率和场效应迁移率,利用亚阈值摆幅法提取了界面态密度,并探讨了漏源电压、晶圆位置、温度对迁移率和界面态密度的影响。结果显示,LDMOSFET的沟道尺寸对沟道迁移率和界面态密度有显著的影响,增加NO的退火温度和时间可以提高沟道迁移率,1 250℃40 min NO退火和1 200℃70 min NO退火的LDMOSFET的常温峰值迁移率均约为45 cm²·V^-1·s^-1,沟道迁移率随测试温度的增加而增加,且高栅压下栅压比测试温度对迁移率的影响更大。     

绝缘栅GaN基平面功率开关器件技术

绝缘栅氮化镓(GaN)基平面功率开关器件是下一代GaN功率电子技术的最佳选择。在此从Si基GaN金属绝缘体(氧化物)半导体(MIS/MOS)高电子迁移率晶体管(HEMT)器件面临的界面态和增强型栅产业化制备等方面入手,介绍了绝缘栅GaN基器件表界面态工程,高可靠栅介质及兼容互补MOS(CMOS)工艺的大尺寸Si基GaN器件制造等技术的研究进展,为绝缘栅GaN基平面功率开关器件的产业化应用奠定基础。     

碳化硅MOSFET栅氧化层可靠性研究

通过TCAD仿真的方法对器件可靠性与结构设计之间的关系进行分析;对栅极电压和栅氧化层最强电场进行仿真,以对碳化硅金属氧化物半导体场效应晶体管(metal-oxide-semiconductor field-effect transistor,MOSFET)单胞结构参数进行优化;在N型碳化硅外延层上制作金属氧化物半导体(metal-oxide-semiconductor,MOS)电容,并且通过对MOS电容进行C-V测试的方法评估Si O2/Si C界面质量。对导带附近界面陷阱密度进行比较。NO退火的样品与干氧氧化样品相比界面质量明显改善,界面态密度小于5×10~11 cm–2e V–1。     

SiC MOSFET重复雪崩能力提升的芯片结构优化方法

SiC MOSFET的高速开关工况易诱发巨大的di/dt,从而在电路的感性负载上引发过电压,导致器件进入雪崩状态。在多次雪崩冲击后,器件易发生重复雪崩失效。针对SiC MOSFET芯片元胞结构中栅氧化层薄弱导致器件耐重复雪崩冲击能力较差的问题,进行芯片元胞结构优化研究,以增强芯片耐重复雪崩能力,提升器件可靠性。首先,研究SiC MOSFET器件重复雪崩失效机理,开展SiC MOSFET器件重复雪崩失效测试,基于失效测试结果建立SiC MOSFET重复雪崩失效可靠性评估模型;其次,针对SiC MOSFET芯片元胞结构提出了栅极底部蚀刻、P-well区扩展、JFET顶部削弱三种优化结构,并研究三种优化结构对SiC MOSFET芯片SiO₂/SiC界面处碰撞电离率和垂直电场强度的影响;最后,基于SiC MOSFET雪崩失效可靠性评估模型,对比分析了三种不同优化结构SiC MOSFET的可靠性。研究结果表明SiC MOSFET器件栅极蚀刻元胞结构具有更高的重复雪崩失效可靠性,相关研究成果为SiC MOSFET器件耐重复雪崩失效能力提升的芯片元胞设计奠定理论基础。     

显示器中场效应管工作特点与检测方法

场效应管也是一种由PN结组成的半导体器件,它有P型和N型两种导电沟道,并且还有结型和绝缘栅(金属氧化物)型两种结构。结型是利用PN结在反向偏置下所产生的耗尽区,绝缘栅型则利用栅极电压产生的感应电荷来改变导电沟道的宽窄,从而控制多数载流子在沟道中的漂移运动所产生的漏极电流。所以它属于电压控制类型的器件。从工作性能的角度来看,场     

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO₂–HfO₂ (7.5?nm)–Ag/Au nc/C60 embedded HfO₂ (6?nm)–HfO₂ (30?nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.     

栅极下加氧化层的新型沟槽栅E-JFET仿真研究

新结构沟槽栅E-JFET的特点是在栅极下隐埋局域氧化层,以降低栅电容,从而改善器件的开关速度,尤其是适用于低压高频领域.通过理论及仿真分析,与无埋氧化层的沟槽栅MOSFET以及沟槽栅E-JFET进行了性能比较.结果证明,该结构具有最低的开关功耗,即QG最小,在相同条件下相对于沟槽栅MOSFET和沟槽栅E-JFET来说,QG的改善分别可达到86.3%和13.4%.     

Underlying design advantages for GaN MOSFETs compared with GaN HFETs for power applications

This study investigates the underlying reasons and quantifies the advantages the GaN MOSFET has over the GaN HFET for high voltage and power applications. Calibrated simulations with equivalent material model files show that equivalent dimensioned devices are capable of producing similar on-state modes of operation, and achieve similar effective mobility at equivalent larger electric fields. However, during sub-threshold operation, the GaN MOSFET is shown to contain a much lower carrier concentration than the GaN HFET. This prolongs the breakdown avalanche effect in the GaN MOSFET (3500 V) by roughly five times larger than the GaN HFET (600 V) for devices of similar dimensions. Implementing the MOS structure can potentially resolve fundamental constraints for high voltage power applications caused by current device architects.     

Potential‐based threshold voltage and subthreshold swing models for junctionless double‐gate metal‐oxide‐semiconductor field‐effect transistor with dual‐material gate

On the basis of quasi‐two‐dimensional solution of Poisson's equation, an analytical threshold voltage model for junctionless dual‐material double‐gate (JLDMDG) metal‐oxide‐semiconductor field‐effect transistor (MOSFET) is developed for the first time. The advantages of JLDMDG MOSFET are proved by comparing the central electrostatic potential and electric field distribution with those of junctionless single‐material double‐gate (JLSMDG) MOSFET. The proposed model explicitly shows how the device parameters (such as the silicon thickness, oxide thickness, and doping concentration) affect the threshold voltage. In addition, the variations of threshold voltage roll‐off, drain‐induced barrier lowering (DIBL), and subthreshold swing with the channel length are investigated. It is proved that the device performance for JLDMDG MOSFET can be changed flexibly by adjusting the length ratios of control gate and screen gate. The model is verified by comparing its calculated results with those obtained from three‐dimensional numerical device simulator ISE. Copyright © 2015 John Wiley & Sons, Ltd.     

半导体GaN功率开关器件灵敏度测试技术

测试半导体GaN功率开关器件灵敏度对掌握器件性能具有重要意义,提出一种新的半导体GaN功率开关器件灵敏度测试技术。通过分析半导体GaN功率开关器件的导通电阻与击穿电压关系、空穴电流与栅极电流关系掌握功率开关器件击穿机理,在此基础上,测试半导体GaN功率开关器件灵敏度;根据灵敏度测试原理与微频通道衰减值周期检查原理,测量功率开关器件微频信号功率和微频通道衰减值,汇总微频通道衰减值和最后一次开关灵敏时的衰减值,得到半导体GaN功率开关器件灵敏度。实验结果表明：所提测试技术测量半导体GaN功率开关器件灵敏度过程中,平均测试误差为0.03 dB,仅平均花费9.42ms,是一种高效、可靠的半导体GaN功率开关器件灵敏度测试技术。     

Impact of channel length,gate insulator thickness,gate insulator material,and temperature on the performance of nanoscale FETs

Aggressive technology scaling as per Moore’s law has led to elevated power dissipation levels owing to an exponential increase in subthreshold leakage power. Short channel effects (SCEs) due to channel length reduction, gate insulator thickness change, application of high-k gate insulator, and temperature change in a double-gate metal–oxide–semiconductor field-effect transistor (DG MOSFET) and carbon nanotube field-effect transistor (CNTFET) were investigated in this work. Computational simulations were performed to investigate SCEs, viz. the threshold voltage (V_th) roll-off, subthreshold swing (SS), and I_on/I_off ratio, in the DG MOSFET and CNTFET while reducing the channel length. The CNTFET showed better performance than the DG MOSFET, including near-zero SCEs due to its pure ballistic transport mechanism. We also examined the threshold voltage (V_th), subthreshold swing (SS), and I_on/I_off ratio of the DG MOSFET and CNTFET with varying gate insulator thickness, gate insulator material, and temperature. Finally, we handpicked almost similar parameters for both the CNTFET and DG MOSFET and carried out performance analysis based on the simulation results. Comparative analysis of the results showed that the CNTFET provides 47.8 times more I_on/I_off ratio than the DG MOSFET. Its better control over the threshold voltage, near-zero SCEs, high on-current, low leakage power consumption, and ability to operate at high temperature make the CNTFET a viable option for use in enhanced switching applications and low-voltage digital applications in nanoelectronics.     

Shielded channel double-gate MOSFET: a novel device for reliable nanoscale CMOS applications

In this paper, the unique features exhibited by a novel double-gate (DG) metal-oxide-semiconductor field-effect transistor (MOSFET) in which the front gate consists of two side gates to 1) electrically shield the channel region from any drain voltage variation and 2) act as an extremely shallow virtual extension to the source/drain are presented. This structure exhibits significantly reduced short-channel effects (SCEs) when compared with the conventional DG MOSFET. Using two-dimensional (2-D) and two-carrier device simulation, the improvement in device performance focusing on threshold voltage dependence on channel length, electric field in the channel, subthreshold swing, and hot carrier effects, all of which can affect the reliability of complementary metal oxide semiconductor (CMOS) devices, was investigated.     

Performance analysis of fully depleted triple material surrounding gate (TMSG) SOI MOSFET

In this paper, analytical model for threshold voltage is derived for fully depleted Triple material Surrounding gate (TMSG) SOI MOSFET. Three gate material of different work functions are introduced in the SOI MOSFET structure to reduce the short channel effects. The two dimensional Poisson equation is solved and based on parabolic approximation method, the model for threshold voltage is developed. The threshold voltage is analyzed for device parameters such as gate length ratios, oxide thickness, silicon thickness, doping concentration. The results of the analytical model values are validated using MEDICI simulation.     

A novel double-gate SOI MOSFET to improve the floating body effect by dual SiGe trench

In short-channel silicon-on-insulator metal-oxide-semiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOI MOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide.     

Performance estimation of sub-30 nm junctionless tunnel FET (JLTFET)

In this paper we examined the short channel behavior of junction less tunnel field effect transistor (JLTFET) and a comparison was made with the conventional MOSFET on the basis of variability of device parameter. The JLTFET is a heavily doped junctionless transistor which uses the concept of tunneling, by narrowing the barrier between source and channel of the device, to turn the device ON and OFF. The JLTFET exhibits an improved subthreshold slope (SS) of 24 mV/decade and drain-induced barrier lowering (DIBL) of 38 mV/V as compared to SS of 73 mV/decade and DIBL of 98 mV/V for the conventional MOSFET. The simulation result shows that the impact of length scaling on threshold voltage for JLTFET is very less as compared to MOSFET. Even a JLTFET with gate length of 10 nm has better SS than MOSFET with gate length of 25 nm, which enlightens the superior electrostatic integrity and better scalability of JLTFET over MOSFET.