A 90-nm variable frequency clock system for a power-managed itanium architecture processor

An Itanium Architecture microprocessor in 90-nm CMOS with 1.7B transistors implements a dynamically-variable-frequency clock system. Variable frequency clocks support a power management scheme which maximizes processor performance within a configured power envelope. Core supply voltage and clock frequency are modulated dynamically in order to remain within the power envelope. The Foxton controller and dynamically-variable clock system reside on die while the variable voltage regulator and power measurement resistors reside off chip. In addition, high-bandwidth frequency adjustment allows the clock period to adapt during on-die supply transients, allowing higher frequency processor operation during transients than possible with a single-frequency clock system.     

基于Java的多线程下载工具研究与实现

随着人们对计算机网络资源的依赖性越来越大,获取网络信息资源已经成为使用计算机的主要目的,而资源下载是获取资源的重要途径和手段。在此针对可靠性高,质量高的Java并行多任务特点,从程序设计的角度,根据用户选择的线程数来对下载的资源进行分块等方法展开论述,分析了基于Java技术进行多线程下载的原理。从状态、块对象、资源大小计算、上下文对象等方面分析了资源对象的创建方法,讨论了文件下载过程中下载、暂停、继续、保存等模块实现方法,给出了一个基于Java技术的多线程下载工具设计流程。经过测试,文件的下载速度得到了改善。     

Improved implementation of FFT algorithm on a high-performance processor

The letter demonstrates an FFT algorithm implemented on the 68000 microprocessor that can calculate a 256-point transform in less than 48 ms. The algorithm employs an interesting method of scaling data to overcome overflow.     

一种可重构处理器的编译器的设计与实现

在现有可重构处理器ESL模型的基础上,提出了为可重构处理器设计一个编译器-CoRP(Compiler of Reconfigurable Processor).CoRP以带有编译指示的串行C代码作为输入,并以并行计算的可重构处理器的机器码作为输出.可重构处理器有了CoRP的支持后,可以自动针对带有编译指示的不同应用程序完成对可重构阵列的重构工作.对数字信号处理应用的仿真结果显示,经过CoRP翻译的代码的性能十分接近于需要花费大量精力手动配置的最理想代码的性能.     

一种用于SDH支路净荷处理器的设计与实现

讨论了支路净荷处理器的实现方案.由于采用特殊的时分复用技术使得电路的规模小、功耗低,可靠性高;经硬件实验证实,电路的性能指标完全可以满足ITU-T的有关标准.采用这种设计方法对系统集成有明显的优势.     

Overview of the architecture, circuit design, and physical implementation of a first-generation cell processor

This paper reviews the design challenges that current and future processors must face, with stringent power limits, high-frequency targets, and the continuing system integration trends. This paper then describes the architecture, circuit design, and physical implementation of a first-generation Cell processor and the design techniques used to overcome the above challenges. A Cell processor consists of a 64-bit Power Architecture processor coupled with multiple synergistic processors, a flexible IO interface, and a memory interface controller that supports multiple operating systems including Linux. This multi-core SoC, implemented in 90-nm SOI technology, achieved a high clock rate by maximizing custom circuit design while maintaining reasonable complexity through design modularity and reuse.     

综合核心处理机的设计与实现

针对机载传感器系统的数字计算应用,分析了综合核心处理机（ICP）的架构特征及其设计时的考量因素,完成了软硬件架构及总线互连设计。在保证ICP硬件通用化、架构开放性及功能可重构的前提下,通过合理地设计模块内部电路、软件层次、网络拓扑及传输机制,有效降低了通信代价,从而提高系统的运算性能。这些方法和技术已被证明是可行的,并在实际的工程中成功应用。     

The microarchitecture of the synergistic processor for a cell processor

This paper describes an 11 FO4 streaming data processor in the IBM 90-nm SOI-low-k process. The dual-issue, four-way SIMD processor emphasizes achievable performance per area and power. Software controls most aspects of data movement and instruction flow to improve memory system performance and core performance density. The design minimizes instruction latency while providing for fine grain clock control to reduce power.     

Low-roundoff-noise limit-cycle-free implementation of recursivetransfer functions on a fixed-point digital signal processor

A method is presented for realizing recursive digital transfer functions on a fixed-point digital signal processor. The method is based on the parallel connection of L∞-norm scaled first- and second-order state-space structures. Magnitude truncation of the state update equations is employed to render the realization free of both overflow oscillations and constant-input limit cycles. The roundoff noise and coefficient sensitivity of the realization are also near minimum, giving a realization with outstanding performance in terms of all finite wordlength effects. An implementation on the DSP56000 family of digital signal processors demonstrates that the realization is efficient enough to achieve high sample rates     

用于MB-OFDM UWB系统的FFT/IFFT处理器的设计与实现

设计了一种应用于超宽带(UWB)无线通信系统中的FFT/IFFT处理器。该处理器采用基24算法进行FFT运算,利用8路并入并出的流水线结构实现该算法,提高了处理器的数据吞吐率,降低了芯片功耗。提出了一种新颖的数据处理方式,在保证信噪比的情况下节约了逻辑资源。在乘法器的设计环节,针对UWB系统的具体特点,在结构上对乘法器进行了改进和优化,提高了乘法器的性能。最后,设计的FFT/IFFT处理器采用TSMC 0.18μm CMOS标准工艺库综合,芯片的内核面积为0.762mm2(不含测试电路)。在1.8V,25℃条件下,最大工作时钟317.199MHz,在UWB典型的工作频率下,内核功耗为33.5304mW。     

Real-time implementation of a narrow-band Kalman filter with afloating-point processor DSP32

The author presents experimental results from two studies. First, a real-time narrowband Kalman filter is implemented with a floating-point digital processor DSP32. The real-time capability of this narrowband filter is investigated by varying parameters Q and R. The covariance matrices Q and R of the dynamic and measurement noise sequences are found to exhibit duality in the real-time tuning process and have a direct effect on system stability. If the value of Q used is smaller (with fixed R ), the tracking time and the narrower tracking bandwidth of the filter will be longer. In addition, if the value of R used (with fixed Q) is smaller, the tracking time will be smaller, and the tracking bandwidth of the filter will be larger. The results are tabulated. Second, two optimal codes (in the sense of the execution speed), straight-line code and general matrix-based code, have been developed for implementing the narrowband Kalman filter. These two codes are compared in terms of program memory size, data memory size, and speed of execution. With the matrix-based code, the DSP32 performance is evaluated in terms of speed and memory size by varying the number of states of a Kalman filter. The results are also tabulated     

Power and temperature control on a 90-nm Itanium family processor

This paper describes the embedded feedback and control system on a 90-nm Itanium family processor, code-named Montecito, that maximizes performance while staying within a target power and temperature (PT) envelope. This system, referred to as Foxton Technology (FT), utilizes on-chip sensors and an embedded microcontroller to measure PT and modulate both voltage and frequency (VF) to optimize performance while meeting PT constraints. Changing both VF takes advantage of the cubic relationship of P/spl prop/CV/sup 2/F. We present measured results that show a 31% reduction in power for only a 10% drop in frequency. Montecito is able to implement FT using only 0.5% of the die area and 0.5% of the die power.     

天文光电观测系统实时信息处理机的设计与实现

针对地基天文光电观测系统获取图像数据量大、实时处理难度高等特点,设计并实现了以高可靠CPCI工控机为平台、基于FPGA+双DSP TMS320C6455的实时信息处理机。详细介绍了实时信息处理机硬件结构,深入分析了实时信息处理机的设计特点。针对实时信息处理机实时图像获取和实时图像处理的主要任务,重点描述了工程实现过程中图像获取及处理流程、弱小目标检测算法实现、DSP任务分割和速度优化等。外场实验及大量实测数据处理结果验证了该处理机的实时性和处理能力,满足了天文光电观测系统的要求,为高分辨率图像的处理运算提供了可靠的硬件平台。     

多线程在分布式多层管理信息系统中的应用

在分布式多层管理信息系统中,信息查询往往是用得最多的操作,查询效率的高低通常能决定整个系统的优劣。利用Delphi多线程技术,探讨了一种在客户端有效的实现远程数据存取的方法。     

宽带自适应OFDM系统中可伸缩FFT处理器的设计和实现

基于Radix-22 SDF(single-path delay feedback)的蝶形运算结构设计了一个级数在64、256、1024、2048之间可选的可伸缩FFT(Scaleable FFT)处理器,以较少的硬件规模满足了宽带自适应正交频分复用(OFDM)传输系统子载波数目可变、数据流量高、低处理延迟、设置灵活的处理要求.文中还针对输入OFDM信号的波形分布特性,仿真分析了该FFT处理器在采用不同的中间处理字长和旋转因子量化字长时其输出信噪比和所占用逻辑单元数目的变化,并据此合理选择了实现参数,在性能提高的同时有效减少了其硬件规模.     

Analog implementation of radix-2, 16-FFT processor for OFDM receivers: non-linearity behaviours and system performance analysis

Analog implementations of decoders have been widely studied by considering circuit complexity, as well as power and speed, and their integration with other analog blocks is an extension of analog decoding research. In the front-end blocks of orthogonal frequency-division multiplexing (OFDM) systems, combination of an analog fast Fourier transform (FFT) with an analog decoder is suitable. In this article, the implementation of a 16-symbol FFT processor based on analog complementary metal-oxide-semiconductor current mirrors within circuit and system levels is presented, and the FFT is implemented using a butterfly diagram, where each node is implemented using analog circuits. Implementation details include consideration of effects of transistor mismatch and inherent noises and effects of circuit non-linearity in OFDM system performance. It is shown that not only can transistor inherent noises be measured but also transistor mismatch can be applied as an input-referred noise source that can be used in system- and circuit-level studies. Simulations of a radix-2, 16-symbol FFT show that proposed circuits consume very low power, and impacts of noise, mismatch and non-linearity for each node of this processor are very small.     

MXT0106处理器调试环境的设计与实现

针对国产SPARCv8处理器MXT0106,开展嵌入式系统专用调试环境研究,完成基于片上调试支持单元的软件调试环境的设计和实现,并和集成开发环境SPE-C进行了集成。     

基于DSP处理器的UMTS Turbo MAP解码器高效实现

Turbo码自1993年问世以来,以其出色的性能,在工业和科研领域都引起了广泛的关注.Turbo码性能逼近(信噪比差为0.7dB或更小)由Claude E.Shannon确定的信道容限.