Rapid thermal annealing of si implanted gaas

Rapid thermal annealing (RTA) technology offers potential advantages for GaAs MESFET device technology such as reducing dopant diffusion and minimizing the redistribution of background impurities. LEC semi-insulating GaAs substrates were implanted with Si at energies from 100 to 400 keV to doses from 1 × 10¹² to 1 × 10¹⁴/cm². The wafers were encapsulated with Si₃N₄ and then annealed at temperatures from 850-1000° C in a commercial RTA system. Wafers were also annealed using a conventional furnace cycle at 850° C to provide a comparison with the RTA wafers. These implanted layers were evaluated using capacitance-voltage and Hall effect measurements. In addition, FET’s were fabricated using selective implants that were annealed with either RTA or furnace cycles. The effects of anneal temperature and anneal time were determined. For a dose of 4 × 10¹²/cm² at 150 keV with anneal times of 5 seconds at 850, 900, 950 and 1000° C the activation steadily increased in the peak of the implant with overlapping profiles in the tail of the profiles, showing that no significant diffusion occurs. In addition, the same activation could be obtained by adjusting the anneal times. A plot of the equivalent anneal times versus 1/T gives an activation energy of 2.3 eV. At a higher dose of 3 × 10¹³ an activation energy of 1.7 eV was obtained. For a dose of 4 × 10¹² at 150 keV both the RTA and furnace annealing give similar activations with mobilities between 4700 and 5000 cm²/V-s. Mobilities decrease to 4000 at a dose of 1 × 10¹³ and to 2500 cm²/V-s at 1 × 10¹⁴/cm². At doses above 1 × 10¹³ the RTA cycles gave better activation than furnace annealed wafers. The MESFET parameters for both RTA and furnace annealed wafers were nearly identical. The average gain and noise figure at 8 GHz were 7.5 and 2.0, respectively, for packaged die from either RTA or furnace annealed materials.     

Capless rapid thermal annealing of GaAs using a graphite susceptor

The results of experiments performed to evaluate the use of a commercially available rapid thermal annealer (RTA) with a graphite susceptor for capless rapid thermal annealing to activate implants in GaAs are reported. The interior of the susceptor was easily charged with As by annealing a sacrificial GaAs wafer. Wafers annealed face up in the charged susceptor showed no evidence of surface degradation (due to preferential loss of As) and no decrease in implant activation (peak doping) when compared to dielectric (SiO₂) capped anneals. Over 50 wafers have been annealed without recharging the susceptor. In addition, slip on 3-in wafers was almost completely eliminated due to the reduction of radial temperature gradients. It is concluded that capless RTA in a commercially available graphite susceptor appears to be a viable annealing technique for activating implants in GaAs and related III-V materials and is suitable for a production environment     

Si^＋注入GaAs及其退火中SiO2包封的作用

对Ｓｉ＾＋注入ＧａＡｓ的前后及其退火的前后用和不用ＳｉＯ２包封进行了对比实验。包封退火大大提高了注入离子的激活率;在包封退火的情况下,光片注入的要比贯穿注入的载流子分布窄。所以,光片注入后包封退火较实用,它使载流子分布窄,激活率高。     

Rapid Thermal annealing of si implanted GaAs

Rapid thermal annealing (RTA) with incoherent light from tungsten lamps shows high potential relative to the conventional furnace annealing (FA) to activate the implanted dopant. Due to the short time annealing, it could completely eliminate the re-diffusion of dopant and host atom. For the Si implantation with dose of 2 × 10¹⁴ cm², the electrical activity of 78% for RTA was higher than that of the FA. But for this short time, some defects measured by deep level transient spectroscopy (DLTS) were hard to remove. A two-step annealing was suggested by the combination of high temperature RTA (1000° C) and FA (700° C). After the post-FA, the defects would be removed to a great extent, and the electrical activity of dopant also increased. With the dose of 2 x 1013 cm^-2, the activity attained after the two step annealing was 92.5%, which may be the highest value according to our knowledge for rapid thermal annealing on Si ion implanted GaAs.     

Rapid thermal annealing of neutron transmutation doped silicon

Rapid thermal annealing (RTA) of neutron transmutation doped Si wafers is shown to be an alternative to conventional furnace annealing. Measurements of resistivity and deep level transient spectroscopy (DLTS), demonstrated annealing on wafers with diameters up to 75 mm. A 4.5 kW incoherent-light RTA furnace was used. Evidence for crystalline slip was found but this did not appear to affect the results. The slip was more severe for the larger diameter wafers. Some results from a DLTS examination of a partially rapid-thermal-annealed wafer are presented.     

Co-Implantation and autocompensation in close contact rapid thermal annealing of Si-implanted GaAs:Cr

Close contact rapid thermal annealing of semi-insulating GaAs:Cr implanted with Si, Si + Al, and Si + P has been studied using variable temperature Hall effect measurements and low temperature (4.2K) photoluminescence (PL) spectroscopy. Isochronal (10 sec) and isothermal (1000° C) anneals indicate that As is lost from the surface during close contact annealing at high anneal temperatures and long anneal times. Samples which were implanted with Si alone show maximum activation at an annealing temperature of 900° C, above which activation efficiency decreases. Low temperature Hall and PL measurements indicate that this reduced activation is due to increasing auto-compensation of Si donors by Si acceptors at higher anneal temperatures. However, co-implantation of column V elements can increase the activation of Si implants by reducing Si occupancy of As sites and increasing Si occupancy of Ga sites, and therebyoffset the effects of As loss from the surface. For samples implanted with Si + P, activation increases continuously up to a maximum at an anneal temperature of 1050° C, and both low temperature Hall and PL measurements indicate that autocompensation does not increase in this case as the anneal temperature increases. In contrast, samples implanted with Si + Al show very low activation and very high compensation at all anneal temperatures, as expected. The use of column V co-implants in conjunction with close contact RTA can produce excellent donor activation of Si implanted GaAs.     

PMOS integrated circuit fabrication using BF3 plasma immersion ion implantation

The feasibility of plasma immersion ion implantation (PHI) for multi-implant integrated circuit fabrication is demonstrated. Patterned Si wafers were immersed in a BF₃ plasma forp-type doping steps. Boron implants of up to 3 × 10¹⁵ atoms/cm² were achieved by applying microsecond negative voltage (-2 to -30 kV) pulses to the wafers at a frequency of 100 Hz to 1 kHz. After implantation the wafers were annealed using rapid thermal annealing (RTA) at 1060° C for 20 sec to activate the dopants and to recrystallize the implant damaged Si. For the PMOS process sequence both the Si source-drain and polycrystalline Si (poly-Si) gate doping steps were performed using PIII. The functionality of several types of devices, including diodes, capacitors, and transistors, were electrically measured to evaluate the compatibility of PIII with MOS process integration.     

Ion implantation in gallium arsenide MESFET technology

The authors emphasize controlled shallow doping of GaAs by ion implantation and its limitations to state-of-the-art GaAs IC technology. The authors discuss the electrical activation behavior of implanted silicon in GaAs upon subsequent capless or silicon nitride capped rapid thermal annealing (RTA). It is demonstrated that atomic H diffuses into the implanted region of GaAs from a plasma-enhanced chemical vapor deposition Si₃N₄ cap during the deposition as well as during subsequent annealing, and the H retards the electrical activation kinetics of the implanted Si. Thru-Si cap dopant implants into GaAs have been studied to enhance dopant concentration in the surface region of the GaAs by recoil-implanted Si from the cap. Application of ion implantation to achieve buried-p layers in GaAs is also briefly discussed     

Correlation between chemical and electrical profiles in Si+, Se+ and S+ implanted bulk and epitaxial GaAs

We compare the chemical profiles of Cr, Mn, Si and Se with the electron concentration profiles in Si, Se and S implanted semi-insulating Cr-O doped bulk GaAs substrates and undoped VPE buffer layers annealed with and without a SiO₂ encapsulant in a H₂-As₄ atmosphere. A higher activation efficiency in the net electron concentration and the gateless saturated channel current is measured for SiO₂ encapsulated wafers annealed under arsine overpressure than for capless annealed ones using Cr-O doped bulk GaAs substrates. On the other hand, the net donor concentration peak is higher for implanted buffer epi layers capless annealed under arsine overpressure than for SiO₂ encapsulated ones. Secondary ion mass spectrometry (SIMS) studies of the Cr decoration of the implant damage indicate that the damage from the 100 keV Si implant anneals out at 840°C while a temperature of 900°C is required to anneal out the 260 keV Se implant damage. An explanation of these differences is provided using an impurity redistribution model and charge neutrality considerations. Excellent Hall electron mobilities at liquid nitrogen temperature of 5400–9200 cm²/V-sec are measured for Si-implanted buffer epi substrates.     

Halogen lamp annealing of GaAs for MESFET fabrication

Incoherent light from high-intensity halogen lamps was used for capless annealing of 2-inch GaAs wafers following silicon ion implantation. Fabrication of depletion mode MESFETs on the annealed wafers was used to study the DC characteristics and uniformity achieved with this annealing method. An average mutual transconductance of 110 mS/mm was obtained with MESFET fabricated wafers which were uniformly implanted at 5 × 1012 cm?2 with Si+ at 80 keV and subsequently annealed at 900°C for 2 s. The carrier concentration profiles obtained with this method are shown to be sharper than those obtained with furnace annealed wafers, which in turn results in a sharper device pinch-off voltage.     

Characteristics of Si3N4/GaAs metal-lnsulator-semiconductor interfaces with coherent Si/Al0.3Ga0.7As interlayers

Si₃N₄/GaAs metal-insulator-semiconductor (MIS) interfaces with Si(10Å)/ Al_0.3Ga_0.7As (20Å) interface control layers have been characterized using capacitance-voltage (C-V) and conductance methods. The structure was in situ grown by a combination of molecular beam epitaxy and chemical vapor deposition. A density of interface states in the 1.1 × 10¹¹ eV^-1 cm^-2 range near the GaAs midgap as determined by the conductance loss has been attained with an ex situ solid phase annealing of 600°C in N₂ ambient. A dip quasi-static C-V demonstrating the inversion of the minority-carrier verifies the decent interface quality of GaAs MIS interface. The hysteresis and frequency dispersion of the MIS capacitors were lower than 100 mV, some of them as low as 50 mV under a field swing of about ±2 MV/cm. The increase of the conductance loss at higher frequencies was observed when employing the surface potential toward conduction band edge, suggesting the dominance of faster traps. Self-aligned gate depletion mode GaAs metal-insulator-semiconductor field-effect transistors with Si/Al_0.3Ga_0.7As interlayers having 3 μm gate lengths exhibited a transconductance of about 114 mS/mm. The present article reports the first application of pseudomorphic Si/ Al_0.3Ga_0.7As interlayers to ideal GaAs MIS devices and demonstrates a favorable interface stability.     

Composite TaSi2/n+poly-Si formation by rapid thermal annealing

Composite TaSi2/n+ poly-Si structures have been formed by rapid thermal annealing (RTA). Polysilicon films 0.2 µm thick were deposited on oxidized Si wafers by LPCVD and heavily doped with phosphorus by diffusion. A layer of TaSix0.22 µm thick was then cosputtered on polysilicon from separate targets. The as-deposited samples were annealed by RTA using high-intensity tungsten lamps. Uniform stoichiometric low-resistivity tantalum disilicide was formed by RTA in 1 s at 1000°C. The sheet resistance and grain size of the silicide layers are comparable to those formed by conventional furnace anneals. The surface morphology of the RTA samples is superior to that obtained by furnace annealing. These results show that RTA technique has a great potential for low-resistivity tantalum silicide formation in VLSI circuits.     

Enhanced infrared transmission of GZO film by rapid thermal annealing for Si thin film solar cells

Ga doped ZnO (GZO) films prepared by sputtering at room temperature were rapid thermal annealed (RTA) at elevated temperatures. With increasing annealing temperature up to 570°C, film transmission enhanced significantly over wide spectral range especially in infrared region. Hall effect measurements revealed that carrier density decreased from ∼8 × 10²⁰ to ∼ 3 × 10²⁰ cm⁻³ while carrier mobility increased from ∼15 to ∼28 cm²/Vs after the annealing, and consequently low film resistivity was preserved. Hydrogenated microcrystalline Si (µc‐Si:H) and microcrystalline Si_1‐xGe_x (µc‐Si_1‐xGe_x:H, x = 0.1) thin film solar cells fabricated on textured RTA‐treated GZO substrates demonstrated strong enhancement in short‐circuit current density due to improved spectral response, exhibiting quite high conversion efficiencies of 9.5% and 8.2% for µc‐Si:H and µc‐Si_0.9Ge_0.1:H solar cells, respectively. Copyright © 2011 John Wiley & Sons, Ltd.     

The effects of point defects on the electrical activation ofSi-implanted GaAs during rapid thermal annealing

The effects of point defects on the electrical activation of Si-implanted GaAs during rapid thermal annealing were investigated using slow positron beam, cross-sectional transmission electron microscopy, and Hall measurements. The increase of the Ga vacancy concentration in the GaAs substrate induced by the SiO₂ cap layer on the substrate during annealing was observed to decrease the activation efficiency and the number of extrinsic stacking faults via the recombination of interstitials with vacancies. It was found that the efficiency of the carrier creation is not dependent upon the Ga vacancy concentration during the rapid thermal annealing of Si-implanted GaAs. Hence, it is proposed that the electrical activation of Si-implanted GaAs is not due to implantation-induced vacancies but to the self-exchange of interstitial Si atoms with the host Ga substitutional atoms     

Ion-implantation and activation behavior of Si in MBE-Grown GaAs on Si substrates for GaAs MESFET's

The suitability of MBE-grown GaAs layers on Si substrates has been studied for ion-implanted GaAs MESFET technology. The undoped as-grown GaAs layers had a carrier concentration below 10¹⁴cm^-3. Uniform Si ion implants into 4-µm-thick GaAs layers on Si were annealed at 900°C for 10 s, using a rapid-thermal-annealing (RTA) system. Both the activation and the doping profile were similar to those obtained in bulk semi-insulating GaAs under similar conditions. The SIMS profiles of Si and As atoms near the GaAs/Si heterointerface were identical before and after the RTA process, indicating negigible interdiffusion during the implant activation. Dual implants of a shallow n+ layer and an n-channel layer were used to fabricate GaAs MESFET's with a recess-gate technology. Selective oxygen ion implantation was used for device isolation. The maximum transconductance obtained was 135 mS/ mm compared to typical values of 150-180 mS/mm obtained in our laboratory on GaAs substrates in similar device structures.     

Sensitivity analysis of ion implanted silicon wafers after rapid thermal annealing

In this study, we have investigated sensitivities of the ion implanted silicon wafers processed by rapid thermal annealing (RTA), which can reveal the variation of sheet resistance as a function of annealing temperature as well as implantation parameters. All the wafers were sequentially implanted by the arsenic or phosphorous implantations at 40, 80, and 100 keV with the dose level of 10¹⁴ to 2 × 10¹⁶ ions/cm². Rapid thermal annealing was carried out for 10 s by the infrared irradiation at a temperature between 850 and 1150°C in the nitrogen ambient. The activated wafer was characterized by the measurements of the sheet resistance and its uniformity mapping. The values of sensitivities are determined from the curve fitting of the experimental data to the fitting equation of correlation between the sheet resistance and process variables. From the sensitivity values and the deviation of sheet resistance, the optimum process conditions minimizing the effects of straggle in process parameters are obtained. As a result, a strong dependence of the sensitivity on the process variables, especially annealing temperatures and dose levels is also found. From the sensitivity analysis of the 10 s RTA process, the optimum values for the implant dose and annealing temperature are found to be in the range of 10¹⁶ ions/cm² and 1050-1100°C, respectively. The sensitivity analysis of sheet resistance will provide valuable data for accurate activation process, offering a guideline for dose monitoring and calibration of ion implantation process.     

Si- and Mg-implanted InP,GaInAs and short-time proximity cap annealing

Si- and Mg-ions with energies of 180 keV have been implanted into semi-insulating InP substrates and low doped n- and p-type GalnAs epitaxial layers (3 · l0¹⁶cm⁻³). Sheet resistances and doping profiles are analyzed and compared with LSS theory. Post-implantation annealing is studied with respect to encapsulation, time and temperature. We have tested as new encapsulation techniques for InP the simple proximity cap annealing and for GalnAs the As-doped spun-on SiO₂. Proximity cap annealing yields decomposition-free surfaces when using a recessed capsubstrate. At annealing temperatures of around 800 °C less activation is obtained than with conventional PSG annealing and a surface accumulation of charge-carriers is established. A time limit of around 3 min is found for Si- and Mg-implanted InP, beyond which the sheet resistance no longer decreases and the doping saturates. For Si in InP, short-time annealing yields to a 68 % activation of carriers, not significantly higher than with conventional long-time annealing. In the case of Si in GalnAs, however, short-time annealing is much more effective. A 100 % activation is obtained for a dose of 2.10¹⁴ cm⁻², while only 7 % is found for long annealing. Even at such a high dose of 1. 10¹⁶cm⁻² we have achieved about an order of magnitude higher activation with short annealing than with long annealing. Most information contained in this paper was presented at the 1984 Electron Materials Conference as paper L-l.     

An electrical method to characterize thermal reactions of Pd/GaAs and Ni/GaAs contacts

Capacitance-voltage (C-V) and current-voltage (I-V) measurements were used to study the thermal reaction of Pd/GaAs contacts and Ni/GaAs contacts. The thickness of GaAs consumed by the metal/GaAs reaction during annealing was calculated from C-V analyses and I-V analyses. For annealing temperatures below 350°C, the Schottky characteristics of the diodes were good but the electrical junction moves into the GaAs after annealing. The amount of junction movement was calculated directly from our measurements. The diffusion coefficients of Pd and Ni in GaAs at 300°C were estimated both to be around 1.2 × 10¹⁴ cm₂/s.     

Self-assembly of metal nanocrystals on ultrathin oxide for nonvolatile memory applications

The self-assembly of metal nanocrystals including Au, Ag, and Pt on ultrathin oxide for nonvolatile memory applications are investigated. The self-assembly of nanocrystals consists of metal evaporation and selective rapid-thermal annealing (RTA). By controlling process parameters, such as the thickness of the deposited film, the post-deposition annealing temperatures, and the substrate doping concentration, metal nanocrystals with density of 2–4 × 10¹¹ cm⁻², diameter less than 8.1 nm, and diameter deviation less than 1.7 nm can be obtained. Observation by scanning-transmission electron microscopy (STEM) and convergent-beam electron diffraction (CBED) shows that nanocrystals embedded in the oxide are nearly spherical and crystalline. Metal contamination of the Si/SiO₂ interface is negligible, as monitored by STEM, energy dispersive x-ray spectroscopy (EDX), and capacitance-voltage (C-V) measurements. The electrical characteristics of metal, nanocrystal nonvolatile memories also show advantages over semiconductor counterparts. Large memory windows shown by metal nanocrystal devices in C-V measurements demonstrate that the work functions of metal nanocrystals are related to the charge-storage capacity and retention time because of the deeper potential well in comparison with Si nanocrystals.     

Effect of ionization on the behavior of silicon in gallium arsenide subjected to electron-beam annealing

The method of capacitance-voltage characteristics was used to study the behavior of Si implanted into GaAs after a postimplantation electron-beam annealing for 10 s under a beam-power density of 7.6 W cm^?2. The electron beam was incident on both the implanted and rear surfaces of the wafers. The reference samples were annealed thermally in a furnace for 30 min at 800°C. It is shown that the diffusion coefficient D is more than three orders of magnitude larger in the case of electron-beam annealing of the implanted surface than in the case of thermal annealing and by almost two orders of magnitude larger than in the case of electron-beam annealing of the rear surface. It is assumed that these distinctions are caused by a long existence time of the high steady-state concentration of nonequilibrium electrons and holes due to their spatial separation.