一种单片高稳振荡器芯片设计

针对传统Pierce振荡器改进了振荡器的起振电路结构,采用负阻起振理论基于0.35μm CMOS工艺设计了一种单片高稳振荡器芯片。芯片主要包含起振电路、缓冲器电路、驱动电路、使能电路及分频器电路,输出频率范围为4 MHz^30 MHz可调,应用cohesion及Hspice软件完成了电路设计与仿真,使用Cadence软件进行了芯片的版图设计,LVS验证后完成了芯片的后仿真工作,仿真结果表明在设定的6种晶体参数下,电路在800μs时完成了起振且在tt、ff、ss 3种模式下输出平稳,该芯片能适用于无线收发信机中。     

对称三相正弦波振荡器

一概述全通滤过器在相位校正电路、相位调制器、无感带通滤过器以及可变频振荡器等电子线路设计中有其广泛用途[参见参考文献1]。本文介绍基于全通滤过器原理,用集成运算放大器构成的对称三相正弦波振荡器。这种振荡器具有波形失真小、对称度好、幅频特性优良和变频时同步调节元件少等优点。以此为基础     

一种简单实用的基波检测方法

基波信号检测是有源滤波器的关键技术之一。提出一种采用并联谐振检测电网中基波信号的方法,该检测电路由一个LC电路构成的选频网络构成。理论分析表明：该选频网络对基波电流的阻抗远大于谐波阻抗,当被检测电流信号流经时,输出电压基本不含谐波。以一组电路参数为例研究了该选频网络的幅值响应、相位响应和动态响应,并分析了这种检测方式的优缺点。实验证明该检测方法具有优良的滤波效果和较快的动态响应。     

高通滤波反馈型正弦脉宽调制逆变器研究

通过分析SPWM逆变器的谐波成分和来源,建立了一种更接近实际的逆变器控制模型,提出了运用有源高通滤波器进行局部反馈控制,消除输出平均值反馈型正弦波逆变器谐波的逆变电源设计方法,并运用乃奎斯特稳定判据分析了系统的稳定性,得出设计参数,利用该方法可以有效地解决输出平均值反馈型正弦波逆变器在非线性负载条件下输出电压波形的失真问题,从而在发挥输出平均值反馈型正弦波逆变器的优势的同时,扩大了其应用范围。之后,利用MATLAB进行了仿真,制作了实验电路,仿真和实验结果进一步证明了该理论的正确性以及该方法的合理性。     

全差分低电压、高驱动能力运算放大器的实现

该文提出了一种全差分低电压、高驱动能力运算放大器电路,通过分析具有不同有源负载结构的差分放大器,得到具有反折电流镜有源负载的差分输入级电路具有较宽的共模输入范围.高效率的甲乙类输出级能提供轨对轨输出摆幅和高输出电流,由于电路具有特定拓扑结构的输出级,因而运算放大器能够工作在低电源电压状态下.采用台积电(TSMC)2层多晶硅、4层金属(2P4M)3.3V,0.35μmCMOS工艺流片得到所设计的全差分低电压、高驱动能力运算放大器在3.3V电源电压工作条件下的功耗仅为625μW,电流输出幅度达到1.2mA.     

电感三点式振荡电路设计探讨

正在广播、通信和电视系统中,都需要高频信号振荡器,广泛应用于无线电发射、超声波焊接和核磁共振等设备中。振荡器是一种波形产生电路,能将直流能量转换为具有一定频率的交流电信号输出。根据所产生的波形不同,可将振荡器分成正弦波振荡器和非正弦波振荡器。振荡器的分类方法有很多,按振荡激励的方式可分为自激型振荡器、他激型振荡器;按电路结构可分为阻容式振荡器、电感电容式振荡器等;按照选频网络所采用元件的不     

集成运放有源电阻波形发生器

本文根据运放单极点模型,利用开环运放所具有的积分特性,提出了有源电阻积分式正弦波发生器,以及有源电阻三角波发生器,并对有源电阻方波发生器进行了介绍。这些电路都分别由两个运算放大器和几个电阻所组成,不需外接电容,其输出波形良好。文中给出实验结果。     

运算放大器应用(續二)

19.滤波器利用运算放大器可以做成滤波器。一般来讲,采用LC滤波器能获得较好的特性和稳定性,然而为了获得更好的特性,就需要用很多元件,这样调整就困难些,同时其体积、重量均也加大。因此不适合用于晶体管电路。而当采用RC滤波器时,其特性就很差,特别在超低频中根本无法采用。在这种情况下,可以采用放大器和反馈电路组成的所谓有源滤波器。有源滤波器的特点为,以RC和放大器来组成低通滤波器、通带滤波器和阻带滤波器等。图22为运算放大器与二组RC电路组成的通带滤波器之一例。若放大器的增益(—A)     

一种低功耗CMOS晶体振荡器电路设计

晶体振荡器作为时钟电路的重要组成部分，是时钟电路中功耗最大的模块，针对传统晶体振荡器功耗过大的问题，根据晶体振荡器起振和停振情况下输出电压信号平均值的特性，提出了一种能够获得振荡器维持振荡状态所需的最小电流的方法，大大降低了晶体振荡器电路的功耗。基于28 nm CMOS工艺设计了一种皮尔斯振荡电路。仿真实验结果表明，在1.8 V电源电压下，电路能够在200 ms内快速起振，振荡频率为32.768 kHz,输出时钟信号稳定后振荡器的工作电流仅为270 nA。     

新型的正弦波振荡器

本文介绍一种新型的可变频率正弦波振荡器,它把最理想的线性调谐规律(即f_0正比于R_0及f_0正比于C_0)应用到正弦波振荡器领域。文中给出了两个典型电路和与理论相符合的实验结果。实验证明,所推荐的由二种不同的工作原理构成的正弦波振荡器,无论用在测量仪表中,还是用在现场测试方面,都将具有以往任何有源RC振荡器所不具备的许多显著的优点。     

New sinusoidal oscillator configurations using operational transresistance amplifier

The objective of this brief is to introduce four new structures of electronically tunable sinusoidal oscillators (SOs) designed using operational transresistance amplifier (OTRA). Each of the proposed SO consists of forward path derived from a generic structure along with one/two OTRA-based resistive gain stages or differentiator in its feedback path. All the proposed SOs enjoy independent tuning of the frequency of oscillation (FO) through resistors without affecting the condition of oscillation (CO). Further, all topologies are found to exhibit low f_o sensitivities at all frequencies with respect to circuit parameters, and the second topology is capable of achieving very low frequencies (VLFs) using less RC component spread and provides linear tuning too. The fourth circuit provides quadrature output. The proposed SOs have been successfully implemented and verified in 180-nm CMOS technology node using ADE (analog design environment) tool Cadence Virtuoso. Both prelayout and postlayout simulation results have been included. To assess the oscillator prefabrication performances, Monte Carlo and process-voltage-temperature (PVT) analyses have been performed. The total harmonic distortion (THD) is observed to be less than 3.5%.     

A linearized and low noise CMOS mixer with B‐type amplifier‐based sub‐harmonic balun

A low noise and high linearity down‐conversion CMOS mixer for 2.4‐GHz wireless receiver is presented in this paper. Using a sub‐harmonic balun with a simple but effective B‐type amplifier, the local oscillator frequency required for this mixer has been reduced by half, and the input local oscillator signal could be single‐ended rather than differential, which simultaneously simplifies the design of local oscillator. A distortion and noise cancelation transconductor in association with current bleeding technique is employed to improve the noise and linearity of the entire mixer under a reduced bias current without compromising the voltage gain. Fabricated in a 0.18‐µm RF CMOS technology of Global Foundries, the mixer demonstrates a voltage gain of 15.8 dB and input‐referred third‐order intercept point of 6.6 dBm with a noise figure of 2.6 dB. It consumes 7.65 mA from a 1.0‐V supply and occupies a compact area of 0.75 × 0.71 mm² including all test pads. Copyright © 2016 John Wiley & Sons, Ltd.     

An approach to model high‐frequency distortion in negative‐feedback amplifiers

In this paper, we present an analytical approach to study the harmonic distortion in the frequency domain of operational amplifiers (opamps) embedded in a nonlinear feedback network. The analysis is based on a frequency‐domain block scheme that models the opamp with one block and the feedback network with two blocks, but it is demonstrated that only one feedback block needs to be characterized for the two basic inverting and non‐inverting configurations. The obtained closed‐form expressions extend our understanding of nonlinear frequency behaviour in feedback opamp circuits. Indeed, they give the contribution of each network component to the output distortion. As an instructive example, we analysed second‐ and third‐order harmonic distortion of an active‐RC inverting lossy integrator having all the components nonlinear. The accuracy of the proposed method is confirmed by comparison with computer simulations at transistor level. Copyright © 2006 John Wiley & Sons, Ltd.     

A CMOS DCO design using delay programmable differential latches and a novel digital control scheme

A novel 16-bit CMOS digitally controlled oscillator (DCO) is described. This CMOS DCO design is based on a delay programmable differential latch and a novel digital control scheme which yields improved phase noise characteristics. Simulations of a 4-stage CMOS DCO using the 0.5 μm Agilent CMOS process parameters achieved a controllable frequency range of 750 MHz–1.6 GHz with a monotone tuning range of around 1 GHz. Monte Carlo simulations indicate that the time-period jitter due to random supply voltage fluctuations is under 250 ps for worst-case considerations. Also, phase noise was found to be in the range of −175 dBc at a frequency of 600 KHz from the carrier at 1.5 GHz (for digital control word of 1512 H) after numerous iterations of Monte Carlo simulations. FFT analysis indicate a total harmonic distortion (THD) of around − 57 dB for the DCO output signal. This CMOS design would thus provide considerable performance enhancement in digital PLL applications.     

Multiple output differential OTA with linearizing bulk‐driven active‐error feedback loop for continuous‐time filter applications

A CMOS circuit realization of a highly linear multiple‐output differential operational transconductance amplifier (OTA) has been proposed. The presented approach exploits a differential pair as an input stage with both the gate and the bulk terminals as signal ports. For the proposed OTA, improved linearity is obtained by means of the active‐error feedback loop operating at the bulk terminals of the input stage. SPICE simulations of the OTA show that, for 0.35 µm AMS process, total harmonic distortion at 1.36Vpp is less than 1% with dynamic range equal to 60.1 dB at power consumption of 276 μW from 3.3 V supply. As an example, both single output and dual differential OTAs are used to design third‐order elliptic low‐pass filters. The cut‐off frequency of the filters is 1 MHz. The power consumption of the OTA‐C filter utilizing the dual output differential OTA is reduced to 1.24 mW in comparison to 2.2 mW consumed by the single output differential OTA‐C filter counterpart. Copyright © 2014 John Wiley & Sons, Ltd.     

碱金属热电转换器功率调节系统研究

针对碱金属热电转换器(AMTEC)的伏安特性,设计了DC/DC和DC/AC两级变换的功率调节系统.功率调节系统采用高频变压器隔离,避免了工频变压器产生的一系列问题.DC/DC变换器采用移相ZVS(零电压开关)PWM全桥变换和电压闭环控制,把AMTEC在较宽范围变动的输出电压变成稳定的直流电压.逆变器控制采用优化的特定消谐PWM技术,以滤波后总谐波含量(THD)为目标函数,计算预定开关角度.整个系统具有电压输入范围宽、转换效率高、输出波形THD低等优点.     

An asynchronous pulse width modulator for DC-DC buck converter

This paper presents an asynchronous pulse width modulation (APWM) approach for the analysis of a new class of the switched mode power supply (SMPS). The proposed APWM significantly simplified the mathematical analysis by utilizing a binary comparator (BAPWM) and a distinctive delay cell instead of hysteretic comparator. By this way, the mathematical analysis can be extended to study the behavior of high-order self-oscillating modulators in terms of key parameters such as the harmonic distortion and the stability. The performance of the proposed BAPWM is deeply analyzed for different orders of loop filters (here up to third order) in both time and frequency domain. To verify the effectiveness of the proposed analytical derivations, the BAPWMs are employed in a classic synchronous DC-DC buck converter and its closed loop performance, in terms of stability, has been investigated. Then the converter is designed and simulated in 130-nm CMOS technology to convert input voltage of 5 to 3.3 V with maximum load current of 1 A, using Spectre simulator. From the post-layout simulation results, the peak efficiency conversion efficiency for 3.3 V output voltage is higher than 89%.     

逆变器并联系统中谐波环流抑制的研究

逆变器中,电压瞬时值反馈调节对死区等因素造成的输出电压波形畸变有着很好的校正作用,但在实验中发现,对于大功率逆变器,由于滤波电感及并机电抗都很小,使得死区等因素可引起很大的谐波环流,而电压瞬时值反馈控制对这种谐波环流的抑制能力是非常有限的。该文为研究谐波环流的产生机理及瞬时值反馈控制对谐波环流的抑制作用,建立了基于谐波扰动的逆变器模型。研究表明,瞬时值反馈控制对谐波环流的抑制能力与其波形校正能力存在相互关系。通过对电压单环,电压电流双环控制的谐波环流抑制能力的比较,发现波形控制效果较好的瞬时值反馈控制,对谐波环流也有较好的抑制作用。仿真与实验验证了上述结论。     

Advanced phase-locked-loop oscillators

This article presents a very sophisticated subclass of communication subsystems, namely oscillators, that use the phase-locked loop (PLL) technique. Some basic features and several application examples are presented that enable locking in the oscillator signal for each frequency offset. If the oscillator is used on its fundamental frequency, a high spectral purity is achieved without additional distortion. Furthermore, it can be increased by the filter function of the loop. An integrated 70 GHz synthesizer is introduced and discussed, and a microwave synthesizer module and its technical behavior is described. Several measured results supported by analytical considerations show the applicability and the high performance of the PLLs introduced     

静止变频器系统分数次谐波分析

通过搭建静止变频器(SFC)系统矩阵实验室(MATLAB)双闭环仿真模型,研究了SFC系统运行参数对分数次谐波的影响.分析发现,总的谐波畸变率(THD)随着回路电流的增大而减小,随着电源电压的升高而增加,分数次谐波含量也有类似的变化规律,其原因在于换相重叠角的改变;分数次谐波次数与机桥输出频率密切相关.通过类比的方法,推导分数次谐波与机桥输出频率的简化关系式,并通过仿真验证其可用性.