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基于小波分析和神经网络的模拟电路故障诊断方法 总被引:1,自引:1,他引:1
提出了一种基于神经网络和小波分析的模拟电路故障诊断的系统方法。该方法通过对电路的可测性测度计算,选择电路的最佳测试节点,然后利用小波分析作为特征提取手段提取电路的故障特征向量,经归一化和主元分析(PCA)处理后。得到最优特征向量,最后输入到神经网络实现电路故障诊断。计算机仿真结果表明该方法具有更好的故障分辨率。 相似文献
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随着集成电路系统复杂性的提高及基于 IP核的 SOC系统的出现 ,电路测试的难度不断增大 ,对电路可测性设计提出了更高的要求。文中在研究了现有各种可测性设计方法优劣后提出了扩展化的 JTAG可测性设计电路 ,它在稍增加电路复杂度的情况下融合各测试方法 ,并提出了利用这种测试电路的 IC系统测试方案。它克服了测试基于 IP核的 SOC系统的一些难点。 相似文献
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本文介绍了正向设计的局用万门程控交换机专用集成电路CSC71018的可测性设计。通过可测性设计,使该电路的测试难度及测试时间减少了将近一半。 相似文献
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可测性设计已应用在大规模集成电路设计中。本文介绍了可测性设计原理和实现技术。同时介绍了一款无线局域网(WLAN)芯片,根据该芯片的结构特点,介绍了本款芯片应用的可测性技术以及实现过程,对使用的EDA工具及设计方法进行了深入描述。最后对可测性设计实现的效果进行了说明,并给出部分测试结果。 相似文献
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本文对SCOAP可测性度量方法作了改进,提出了动态SCOAP算法。此算法反映测试生成过程中系统和电路各节点可测性的变化,比静态SCOAP更准确地描述了每个故障的可测性难度,为测试生成过程提供更有效的启发性信息。 相似文献
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为了提高大规模集成电路可测性设计(Design For Test,DFT)的故障覆盖率,减少测试时间,通过分析自我测试(Self-Testing Using MISR and Parallel SRSG,STUMPS)方法中的测试机制,找出了其测试效果不理想的原因,提出了改进型的大规模集成电路的测试方法,用C语言编写了故障模拟程序,并且在ISCAS’85标准测试电路上进行了验证。 相似文献
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介绍了基于模拟电路极零点灵敏度的分析方法,给出了极零点灵敏度的计算公式。介绍了模拟电路可测性度量的概念,以及基于极零点灵敏度的模拟电路可测性分析方法,给出了求可测性度量的方法。该方法可以用于确定模拟电路的测试点和测试方法。作为例子,对一个3阶电路进行了简要分析。 相似文献
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模拟集成电路的测试与故障检测技术 总被引:2,自引:0,他引:2
本文综述了模拟集成电路的测试及故障检测等有关问题,首先介绍面向性能的测试方法,然后讨论故障模型和面向故障的测试方法,在介绍了模拟集成电路的可测性设计技术之后,讨论了利用电源监测进行故障检测的方法。 相似文献
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Ravi S. Lakshminarayana G. Jha N.K. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2001,9(6):824-832
In this paper, we present testability analysis and optimization (TAO), a novel methodology for register-transfer level (RTL) testability analysis and optimization of RTL controller/data path circuits. Unlike existing high-level testing techniques that cater restrictively to certain classes of circuits or design styles, TAO exploits the algebra of regular expressions to provide a unified framework for handling a wide variety of circuits including application-specific integrated circuits (ASICs), application-specific programmable processors (ASPPs), application-specific instruction processors (ASIPs), digital signal processors (DSPs), and microprocessors. We also augment TAO with a design-for-test (DFT) framework that can provide a low-cost testability solution by examining the tradeoffs in choosing from a diverse array of testability modifications like partial scan or test multiplexer insertion in different parts of the circuit. Test generation is symbolic and, hence, independent of bit width. Experimental results on benchmark circuits show that TAO is very efficient, in addition to being comprehensive. The fault coverage obtained is above 99% in all cases. The average area and delay overheads for incorporating testability into the benchmarks are only 3.2% and 1.0%, respectively. The test generation time is two-to-four orders of magnitude smaller than that associated with gate-level sequential test generators, while the test application times are comparable 相似文献
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FMECA在雷达装备综合保障中的开展与应用 总被引:1,自引:0,他引:1
综合保障是提高装备战斗力的重要手段,综合保障工作的开展,可以全面解决装备可靠性、维修性、测试性、安全性和保障性的问题。而在装备综合保障工作中,可以通过开展FMECA来获得可靠性、维修性、测试性、安全性和保障性的重要信息,从而指导装备综合保障各项工作的开展,发现综合保障中的薄弱环节,从而提出改进措施。该文重点讨论FMECA在综合保障各项工作中的重要意义,并为FMECA适应综合保障工作提出了相应的要求及实现方法,使FMECA成为综合保障的核心工作内容。在某型雷达综合保障工作中,通过重点开展FMECA工作达到综合保障设计的要求。 相似文献
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针对综合模块化航电系统对测试性提出的更高要求及其工程实践中存在的典型问题,定义了一种分布-集中式的系统测试诊断架构,以适应其体系架构的特点和生产配套关系的变化;提出了一种基于模型的系统测试性设计方法和流程,以测试性模型为驱动指导航电系统的测试性方案设计、评估与优化过程,取代传统的基于指标的测试性设计方法。在某机载综合射频系统上开展了方法应用,成功解决了该系统综合化以后测试诊断架构设计与测试性分配的非线性问题。 相似文献
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This article presents a discussion of several methods that can be used to improve the testability of complex mixed-signal telecommunication integrated circuits. We begin by outlining the role of test and its impact on product cost and quality. A brief look at the pending test crises for mixed-signal circuits is also considered. Subsequently, we outline the evolution of test strategies with time, and their corresponding test setups for verifying the function of the analog portion of a mixed-signal circuit. The article also describes several circuit techniques for improving test access and providing built-in self-test solutions for telecommunication circuits 相似文献
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The testability of majority voting based fault-tolerant circuits is investigated and sufficient conditions for constructing circuits that are testable for all single and multiple stuck-at faults are established. The testability conditions apply to both combinational and sequential logic circuits and result in testable majority voting based fault-tolerant circuits without additional testability circuitry. Alternatively, the testability conditions facilitate the application of structured design for testability and Built-In Self-Test techniques to fault-tolerant circuits in a systematic manner. The complexity of the fault-tolerant circuit, when compared to the original circuit can significantly increase test pattern generation time when using traditional automatic test pattern generation software. Therefore, two test pattern generation algorithms are developed for detecting all single and multiple stuck-at faults in majority voting based circuits designed to satisfy the testability conditions. The algorithms are based on hierarchical test pattern generation using test patterns for the original, non-fault-tolerant circuit and structural knowledge of the majority voting based design. Efficiency is demonstrated in terms of test pattern generation time and cardinality of the resulting set of test patterns when compared to traditional automatic test pattern generation software. 相似文献