Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ hbox{HfSiO}_{x}/hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si_0.77Ge_0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm^-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.     

Fully strained Si0.75Ge0.25 epitaxial films with HfSiO gate dielectrics for high mobility channel metal-oxide semiconductor devices

The authors report on fully strained Si_0.75Ge_0.25 metal-oxide-semiconductor capacitors with HfSiO₂ high-k gate dielectric and TaN metal gate fabricated on Si substrates. Fully strained Si_0.75Ge_0.25 films are directly grown on Si substrates below the critical thickness. HfSiO₂ high-k gate dielectrics exhibit an equivalent oxide thickness of 13-18 Å with a permittivity of 17.7 and gate leakage current density lower than SiO₂ gate oxides by >100×. Interfacial oxide of the HfSiO₂/Si_0.75Ge_0.25 stack consists primarily of SiO₂ with a small amount of Ge and Hf. High performance SiGe field effect transistors are highly manufacturable with excellent electrical characteristics afforded by the fully strained HfSiO₂/SiGe gate stack.     

High mobility strained Si0.5Ge0.5/SSOI short channel field effect transistors with TiN/GdScO3 gate stack

Short channel p-type metal-oxide-semiconductor field effect transistors (MOSFETs) with GdScO₃ gate dielectric were fabricated on a quantum well strained Si/strained Si_0.5Ge_0.5/strained Si heterostructure on insulator. Amorphous GdScO₃ layers with a dielectric constant of 24 show small hysteresis and low density of interface states. All devices show good performance with a threshold voltage of 0.585 V, commonly used for the present technology nodes, and high I_on/I_off current ratios. We confirm experimentally the theoretical predictions that the drive current and the transconductance of the biaxially strained (1 0 0) devices are weakly dependent on the channel orientation. The transistor’s hole mobility, extracted using split C-V method on long channel devices, indicates an enhancement of 90% (compared to SiO₂/SOI transistors) at low effective field, with a peak value of 265 cm²/V s. The enhancement is however, only 40% at high electrical fields. We demonstrate that the combination of GdScO₃ dielectric and strained SiGe layer is a promising solution for gate-first high mobility short channel p-MOSFETs.     

New opportunities for SiGe and Ge channel p-FETs

A thin body (fully depleted) strained SGOI device structure (FDSGOI), and a strained SiGe channel layer on SOI, were fabricated using scaled high-κ gate dielectrics and metal gate technology. The uniaxial strain effect and corresponding drive current enhancement reported by Irisawa et al. [1] for narrow-width devices was investigated on these structures. Although the strained FDSGOI device structure exhibited reduced off-state leakage compared to thicker body devices, and long-channel drive current enhancement under uniaxial strain, the loss of drive current enhancement at short channel length led to uncompetitive I_ON-I_OFF characteristics. The SiGe on SOI structure showed the highest long-channel drive current enhancement (nearly 3×) in the narrowest devices, and also showed a significant reduction in off-state current. This trend was maintained down to the shortest channel lengths studied here and resulted in I_ON-I_OFF characteristics that were competitive with contemporary uniaxial strained Si channel devices.     

Strained‐SiGe Complementary MOSFETs Adopting Different Thicknesses of Silicon Cap Layers for Low Power and High Performance Applications

We introduce a strained‐SiGe technology adopting different thicknesses of Si cap layers towards low power and high performance CMOS applications. By simply adopting 3 and 7 nm thick Si‐cap layers in n‐channel and p‐channel MOSFETs, respectively, the transconductances and driving currents of both devices were enhanced by 7 to 37% and 6 to 72%. These improvements seemed responsible for the formation of a lightly doped retrograde high‐electron‐mobility Si surface channel in nMOSFETs and a compressively strained high‐hole‐mobility Si_0.8Ge_0.2 buried channel in pMOSFETs. In addition, the nMOSFET exhibited greatly reduced subthreshold swing values (that is, reduced standby power consumption), and the pMOSFET revealed greatly suppressed 1/f noise and gate‐leakage levels. Unlike the conventional strained‐Si CMOS employing a relatively thick (typically > 2 µm) Si_xGe_1‐x relaxed buffer layer, the strained‐SiGe CMOS with a very thin (20 nm) Si_0.8Ge_0.2 layer in this study showed a negligible self‐heating problem. Consequently, the proposed strained‐SiGe CMOS design structure should be a good candidate for low power and high performance digital/analog applications.     

HfAlOx high-k gate dielectric on SiGe: Interfacial reaction, energy-band alignment, and charge trapping properties

Ultra thin HfAlO_x high-k gate dielectric has been deposited directly on Si_1−xGe_x by RF sputter deposition. The interfacial chemical structure and energy-band discontinuities were studied by using X-ray photoelectron spectroscopy (XPS), time of flight secondary ion mass spectroscopy (TOF-SIMS) and electrical measurements. It is found that the sputtered deposited HfAlO_x gate dielectric on SiGe exhibits excellent electrical properties with low interface state density, hysteresis voltage, and frequency dispersion. The effective valence and conduction band offsets between HfAlO_x (E_g = 6.2 eV) and Si_1−xGe_x (E_g = 1.04 eV) were found to be 3.11 eV and 2.05 eV, respectively. In addition, the charge trapping properties of HfAlO_x/SiGe gate stacks were characterized by constant voltage stressing (CVS).     

Performance enhancement in Ge pMOSFETs with <1 0 0> orientation fabricated with a Si-compatible process flow

The electrical characterization of Ge pMOSFETs having <1 1 0> and <1 0 0> orientations with gate lengths of 3 μm have been demonstrated with a Si-compatible process flow. Employment of <1 0 0> orientation in Ge pMOSFETs without incorporation of strain provided ∼10% enhancement in effective hole mobility and drive current when compared to <1 1 0> oriented regular transistors. In this fabrication technology, the effective hole mobility improves from 190 cm²/V s for <1 1 0> devices to 210 cm²/V s for the <1 0 0> oriented Ge devices at room temperature, which is ∼2 times the hole mobility of Si pFET devices. This study also presents first time investigation of post metallization anneal (PMA) at 350 °C in H₂ ambient for <1 0 0> Ge pMOSFETs. The overall performance of the devices has been enhanced by 15% after performing PMA. It is likely attributed to a strong decrease of D_it, improving the transistor performance. These results indicate that the <1 0 0> Ge pMOSFETs could be a viable candidate for future low voltage high speed CMOS applications.     

0.6nm-EOT high-k gate stacks with HfSiOx interfacial layer grown by solid-phase reaction between HfO2 and Si substrate

We have developed a process for forming an ultra-thin HfSiO_x interfacial layer (HfSiO_x-IL) for high-k gate stacks. The HfSiO_x-IL was grown by the solid-phase reaction between HfO₂ and Si-substrate performed by repeating the sequence of ALD HfO₂ deposition and RTA. The HfSiO_x-IL grown by this method enables the formation of very uniform films consisting of a few mono-layers, and the dielectric constant of the HfSiO_x-IL is about 7. The FUSI-NiSi/HfO₂ gate stacks with HfSiO_x-IL have achieved 0.6 nm EOT, a very low gate leakage currents between 1 A/cm² and 5 × 10⁻² A/cm², an excellent subthreshold swing of 66mV/dec, and a high peak mobility of 160 cm²/Vs compared to the reference samples without HfSiO_x-IL. These results indicate that the HfSiO_x-IL has a good quality compared to the SiO₂ interfacial layer grown by oxygen diffusion through HfO₂ films.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

A comparative 1/f noise study of GeOI wafers obtained by the Ge enrichment technique and the Smart Cut technology

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying GeOI pMOSFETs, and the enrichment process by studying Si_1−xGe_x (x = 25% and 35%) pMOSFETs. The buried oxide is used as a back gate for experimental purposes. The extracted values are of the same order of magnitude for both processes and are close to those of state of art buried oxide SiO₂/Si interfaces, demonstrating that both the Smart Cut™ and enrichment techniques produce equally good quality interfaces.     

Interfacial microstructure and electrical properties of HfAlOx thin films on compressively strained Si83Ge17 grown by RF magnetron sputtering

Interfacial microstructure and electrical properties of HfAlO_x films deposited by RF magnetron sputtering on compressively strained Si₈₃Ge₁₇/Si substrates were investigated. HfSiO_x-dominated amorphous interfacial layer (IL) embedded with crystalline HfSi_x nano-particles were revealed by high resolution transmission electron microscopy (HRTEM) and X-ray photoelectron spectroscopy depth profile study. About 280 mV-wide clockwise capacitance-voltage(C-V) hysteresis for the HfAlO_x film deposited in Ar + N₂ mixed ambient was observed. Oxygen vacancies and interfacial defects in the HfSiO_x IL, as well as trapped charges in the boundaries between the HfSi_x nano-particles and surrounded amorphous HfSiO_x may be responsible for the large C-V hysteresis.     

Enhanced electrical properties of nominally undoped Si/SiGe heterostructure nanowires grown by molecular beam epitaxy

Electrical properties of epitaxial single-crystalline Si/SiGe axial heterostructure nanowires (NWs) on Si〈1 1 1〉 substrate were measured by contacting individual NWs with a micro-manipulator inside an scanning electron microscope. The NWs were grown by incorporating compositionally graded Si_1−xGe_x segments of a few nm thicknesses in the Si NWs by molecular beam epitaxy. The I-V characteristics of the Si/SiGe heterostructure NWs showed Ohmic behavior. However, the resistivity of a typical heterostructure NW was found to be significantly low for the carrier concentration extracted from the simulated band diagram. Similarly grown pure Si and Ge NWs showed the same behavior as well, although the I-V curve of a typical Si NW was rectifying in nature instead of Ohmic. It was argued that this enhanced electrical conductivities of the NWs come from the current conduction through their surface states and the Ge or Si/SiGe NWs are more strongly influenced by the surface than the Si ones.     

Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels

The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is /spl sim/ 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.     

Parameters extraction of hafnium based gate oxide capacitors

From quantum simulations of both capacitance and current measurements, the main physical parameters (dielectric thickness and permittivity, doping levels) of hafnium based (HfSiO_x and HfO₂) gate oxide capacitors have been extracted. Three kinds of gates (n⁺-polysilicon, totally silicided (TOSI) NiSi and metal TiN gates) have been studied. In the case of thick (EOT between 11.1 and 12.3 nm) HfSiO_x gate oxides or thin (EOT inferior to 2 nm) HfO₂ stacks with n⁺-polysilicon or TiN gates, a good agreement between simulations and experimental data is obtained. Electron tunneling currents are prevalent in these stacks except for the specific case of TiN/HfO₂ stacks in p-substrate accumulation mode. In this case, electron and hole tunneling transparencies become of the same order of magnitude. Hole transport contribution can no more be neglected and should be taken into account in simulations.     

High Mobility Strained Ge pMOSFETs With High-κ/Metal Gate

Compressively strained Ge long channel ring-type pMOSFETs with high-kappa Si/SiO₂/HfO₂/TiN gate stacks are fabricated on Si_0.2Ge_0.8 virtual substrates. Effective oxide thickness is approximately 1.4 nm with low gate leakage current. A peak hole mobility of 640 cm²/ Vldrs and up to a four times enhancement over the Si/SiO₂ universal curve are observed. Parasitic conduction within the Si-cap layers degrades the mobility at large vertical fields, although up to a 2.5 times enhancement over universal remains at a field of 0.9 MV/cm.     

Dopant effects on the thermal stability of FUSI NiSi

The thermal stability of fully silicided (FUSI) NiSi with arsenic or boron doping on silicon on insulator (SOI) was investigated. After the stacks were subjected to a typical back-end of line (BEOL) thermal annealing in a N₂ ambient, abnormal oxidation of As doped FUSI NiSi stacks is observed by X-ray photoelectron spectroscopy (XPS), and confirmed by high-resolution transmission electron microscopy (HRTEM). X-ray diffraction (XRD) results show Ni-rich phases like Ni₃Si are formed due to abnormal oxidation of FUSI NiSi. In contrast to As doped stacks, no phase transformation nor abnormal oxidation are observed for B doped stacks under similar annealing. However, backside secondary ion mass spectrometry (SIMS) results indicate B penetration through a 3 nm SiON layer into the Si channel after N₂ annealing for 4 h at 400 °C. There is no evidence for Ni diffusion into the Si channel for B doped stacks. However, Ni penetration into the Si channel is observed for As doped stacks due to the enhancement of abnormal oxidation of FUSI NiSi.     

NBTI reliability on high-k metal-gate SiGe transistor and circuit performances

Negative-bias temperature instability (NBTI) on high-k metal-gate SiGe p-channel MOSFETs has been examined. SiGe p-MOSFETs shows reduced interface states and enhanced NBTI reliability compared to their Si p-channel control devices as evidenced by experimental data. Impact of NBTI reliability on digital and RF circuits has been also examined using extracted fresh and stressed BSIM4 model parameters in circuit simulation. High-k metal-gate SiGe pMOSFETs demonstrate less inverter pull-up delay, smaller noise figure of a cascode low-noise amplifier, and larger output power and power-added efficiency than their Si counterparts when subject to NBTI stress.     

Precise determination of metal effective work function and fixed oxide charge in MOS capacitors with high-κ dielectric

Effective metal work function, Φ_m,eff, and oxide charge, Q_ox, were determined on MOS capacitors with slanted high-κ dielectric. Φ_m,eff and Q_ox were extracted using flat-band voltage shift versus equivalent oxide thickness data, both deduced from the capacitance–voltage measurements. Slanted HfSiO_x dielectric (initial thickness was 9 nm) was prepared by gradual etching in HF-based solution. As a metal electrode, thin Ru-films were deposited by MOCVD-derived technique—Atomic Vapor Deposition^® on the slanted HfSiO_x as well as SiO₂ dielectrics. The Φ_m,eff of Ru was found to be 4.74 and 4.81 eV for Ru/HfSiO_x and Ru/SiO₂ gate stacks, respectively. Ultraviolet photoelectron spectroscopy yields the work function of 4.62 eV in agreement with the capacitance–voltage data. We also studied the I–V characteristics of the Ru/HfSiO_x/Si MOS capacitors. The barrier height was found to be constant within the HfSiO_x bulk.     

应用400℃低温Si技术制备应变Si沟道pMOSFET

在利用分子束外延方法制备SiGe pMOSFET中引入了低温Si技术.通过在Si缓冲层和SiGe层之间加入低温Si层,提高了SiGe层的弛豫度.当Ge主分为20%时,利用低温Si技术生长的弛豫Si1-xGex层的厚度由UHVCVD制备所需的数微米降至400nm以内,AFM测试表明其表面均方粗糙度(RMS)小于1.02nm.器件测试表明,与相同制备过程的体硅pMOSFET相比,空穴迁移率最大提高了25%.     

Electrical characteristics and TDDB breakdown mechanism of N2-RTA-treated Hf-based high-κ gate dielectrics

This study investigates the effects of rapid thermal annealing (RTA) in nitrogen ambient on HfO₂ and HfSiO_x gate dielectrics, including their electrical characteristics, film properties, TDDB reliability and breakdown mechanism. The optimal temperature for N₂ RTA treatment is also investigated. The positive oxide trap charges (oxygen vacancies) in HfO₂ and HfSiO_x dielectric films can be reduced by the thermal annealing, but as the annealing temperature increased, many positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy level will be formed in the grain boundaries, degrading the electrical characteristics, and changing the breakdown mechanism. We believe that variation in the number of positive oxide trap charges (oxygen vacancies) with shallow or deep trap energy levels is the main cause of the CV shift and difference in the breakdown behaviors between HfO₂ and HfSiO_x dielectrics. With respect to CV characteristics and TDDB reliability, the optimal temperature for N₂ RTA treatment is in the range 500-600 °C and 800-900 °C, respectively.