Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs

The threshold voltage, V_th of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss's law and solving Poisson's equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for V_th is developed, and an analytic expression for V_th is obtained, including quantum mechanical effects and SB lowering effect. We find that V_th is very sensitive to the silicon body thickness, t_si. For a device with a small t_si (<3 nm), V_th increases dramatically with the reduction of t_si. V_th decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers.     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

2D analytical calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunneling/thermionic current

In this paper we present a new approach to calculate the channel electric field within a Schottky barrier Double-Gate MOSFET (SB-DG-MOSFET) in subthreshold region by solving Poissons equation. The Poisson equation is solved two dimensionally in an analytical closed-form with the conformal mapping technique. A comparison with data simulated by TCAD Sentaurus simulator for channel lengths down to 22 nm was made and shows an accurate agreement. Futhermore, a new way for the estimation of the tunneling current in SB-DG-MOSFET by applying the above 2D solution for the electric field and a 2D solution of the electrostatic potential is presented. Calculating the tunneling current, we use Wentzel-Kramers-Brillouin (WKB) approximation for the estimation of the tunneling probability. For the calculation of the tunneling and thermionic current a comparison with TCAD Sentaurus for channel lengths down to 65 nm was made.     

Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nm and the 20 nm n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher Ion/Ioff ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs.     

AlGaN/GaN HEMT低温直流特性研究

研究了20℃～-70℃栅宽为100μm、栅长为1μm的AlGaN/GaN HEMT的直流特性.随温度降低，电子迁移率增大，而二维电子气密度基本不变，HEMT饱和漏电流IDsat增大;阈值电压低温时有所下降，在一定温度范围内变化不明显，其原因除栅肖特基势垒高度、AlGaN/GaN导带差发生变化外，还可能与器件制备工艺和源极串联电阻有关。     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.     

Influence of temperature and drain current on source and drain resistances in AlGaN/GaN HEMTs

The behavior of source and drain resistances (R_S and R_D) has been studied for a wide range of drain currents at ambient temperatures from 150 to 500 K. Both parasitic resistances show an important increase as temperature rises, directly related to the reduction in the electron mobility. High drain currents also produce a non-linear increment of R_S and R_D, once the space-charge limited current is exceeded. Both temperature and drain current mechanisms have been modeled together by means of a simple equation, and a good agreement between simulations and measurements is found. Non-linear R_S and R_D allow a more accurate extraction of the intrinsic parameters, especially in the high drain current range. The use of variable parasitic resistances instead of their usually assumed constant values reveals higher intrinsic transconductance (g_m,int) and C_gs.     

Stress analysis of Si1−xGex embedded source/drain junctions

The purpose of this paper is to evaluate the impact of the geometry of embedded Si_1−xGe_x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si_1−xGe_x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.     

TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件的模拟研究

对0．25μm TiN栅及抬高源漏的薄膜全耗尽SOI CMOS器件进行了模拟研究。由于TiN栅具有中间禁带功函数，在低的工作电压下，NMOS和PMOS的阈值电压都得到了优化。随硅膜厚度的减小，釆用源漏抬高结构，减小了源漏串联电阻。采用抬高源漏结构的NMOS和PMOS，其饱和电流分别提高了36％和41％。由于采用源漏抬高能进一步降低硅膜厚度，短沟道效应也得到了抑制．     

纳米CMOS器件中源/漏串联电阻栅长相关性研究

本文利用恒定迁移率、直接I_d-V_gs和Y函数三种方法对纳米CMOS器件中提取的源/漏串联电阻(R_sd)与器件栅长(L)相关性进行了研究。结果表明,采用恒迁移率方法得到的R_sd具有与栅长无关的特性,纳米小尺寸CMOS器件的R_sd值在14.3Ω～10.9Ω之间。直接I_d-V_gs和Y函数方法都得到了与L相关的R_sd值,误差分析发现从直接I_d-V_gs和Y函数两种方法中提取的R_sd对L依赖性与提取过程中的栅极电压导致有效沟道迁移率(μ_eff)降低有关,推导过程中忽略了这种影响,R_sd值叠加了一个与栅长相关的量。本文计算了这个叠加的误差值,并得到消除此误差值之后各个栅长器件的R_sd值。     

Degradation of 1/f noise in short channel MOSFETs due to halo angle induced VT non-uniformity and extra trap states at interface

The impact of halo implantation angle on the low-frequency noise of short channel n-MOSFET is reported. The low-frequency noise is degraded with larger tilt angle for the same implant dose and energy. The higher dose/energy of the halo implant with larger tilt angle further enhances the degradation of low-frequency noise. The larger halo angle introduces non-uniform doping distribution and creates the non-uniform threshold voltage along the channel. Additional traps can be created near the oxide/semiconductor interface due to boron pileup due to larger tilt angle. A quantitative analysis supported by experimental results confirm that the degradation of 1/f noise is due to the combined effect of non-uniformity in threshold voltage along the channel and the creation of extra trap charges near the oxide-semiconductor interface (near-interfacial charges).     

基于自适应遗传算法的摆镜动态优化设计

为了满足正弦摆动过程中较高面型精度,实现相关跟踪系统摆镜的高度轻量化设计,在直径110 mm圆平面反射镜的设计过程中引入了基于自适应遗传算法的摆镜结构优化。对背部粘结支撑点的大小进行了计算,同时对摆镜的有限元模型进行了轴对称的简化,提高了优化过程中的效率。介绍了自适应遗传算法结构优化的原理及优越性,并提出了两种正弦振动过程中的面型求解方案。最后将自适应遗传算法的结果与传统算法进行了比较。结果证明,基于自适应遗传算法的摆镜动态参数优化方案正确可靠,具有较高的寻优能力,对类似工程结构参数优化具有一定的指导性与借鉴性。     

Analytical 2D modeling for potential distribution and threshold voltage of the short channel fully depleted cylindrical/surrounding gate MOSFET

A two-dimensional analytical model for fully depleted cylindrical/surrounding gate MOSFET is presented. We used the evanescent mode analysis to solve the 2D Poisson's equation and to deduce analytically the surface potential and threshold voltage expressions of this device. Comparison with the other models reveals a good agreement.     

Fast multi-objective optimization of multi-parameter antenna structures based on improved MOEA/D with surrogate-assisted model

For multi-objective design of multi-parameter antenna structures, optimization efficiency and computational cost are two major concerns. In this paper, an improved multi-objective evolutionary algorithm based on decomposition (MOEA/D) is proposed to improve global optimization capability by diversity detection operation and mixed population update operation. Further, in order to reduce the computational cost, a hybrid optimization strategy integrating a dynamically updatable surrogate-assisted model into the improved MOEA/D is proposed. The numerical results of test functions show that our algorithm outperforms original MOEA/D, modified MOEA/D (M-MOEA/D), and nondominated sorting genetic algorithm II (NGSA-II) in terms of diversity. Experimental validation of Pareto-optimal planar miniaturized multiband antenna designs is also provided, showing excellent convergence and considerable computational savings compared to those previously published approaches.     

SSIM-based error-resilient rate-distortion optimization of H.264/AVC video coding for wireless streaming

The SSIM-based rate-distortion optimization (RDO) has been verified to be an effective tool for H.264/AVC to promote the perceptual video coding performance. However, the current SSIM-based RDO is not efficient for improving the perceptual quality of the video streaming application over the error-prone network, because it does not consider the transmission induced distortion in the encoding process. In this paper, a SSIM-based error-resilient RDO scheme for H.264/AVC is proposed to improve the wireless video streaming performance. Firstly, with the help of the SSE-based RDO, we present a low-complexity Lagrange multiplier decision method for the SSIM-based RDO video coding in the error-free environment. Then, the SSIM-based decoding distortion of the user end is estimated at the encoder and is correspondingly introduced into the RDO to involve the transmission induced distortion into the encoding process. Further, the Lagrange multiplier is theoretically derived to optimize the encoding mode selection in the error-resilient RDO process. Experimental results show that the proposed SSIM-based error-resilient RDO can obtain superior perceptual video quality (more structural information) to the traditional SSE-based error-resilient RDO for wireless video streaming at the same bit rate condition.     

遗传算法在和差波束印刷天线中的应用

讨论比较了四种现代化方法的基本原理和内容，据此选择遗传算法建立了一种耦合渐变槽线天线的多目标优化模型，用于设计单脉冲系统的和差波束印刷天线，详细讨论了应用遗传算法的具体步骤，经计算得出的天线性能达到了预期的优化目标，并得到实测数据的验证。