Electric potential and threshold voltage models for double-gate Schottky-barrier source/drain MOSFETs

The threshold voltage, V_th of a double-gate (DG) Schottky-barrier (SB) source/drain (S/D) metal-oxide-semiconductor field-effect transistor (MOSFET) has been investigated. An analytic expression for surface potential is obtained by using Gauss's law and solving Poisson's equation, the results of which are compared with simulations, and good agreement is observed. Based on the potential model, a new definition for V_th is developed, and an analytic expression for V_th is obtained, including quantum mechanical effects and SB lowering effect. We find that V_th is very sensitive to the silicon body thickness, t_si. For a device with a small t_si (<3 nm), V_th increases dramatically with the reduction of t_si. V_th decreases with the increase of the back-gate oxide thickness, and with the increasing of the drain bias. All the results can be of great help to the ultra-large scale integrated-circuit (ULSI) designers.     

Modeling the drain current and its equation parameters for lightly doped symmetrical double-gate MOSFETs

A 2D model for the potential distribution in silicon film is derived for a symmetrical double gate MOSFET in weak inversion. This 2D potential distribution model is used to analytically derive an expression for the subthreshold slope and threshold voltage. A drain current model for lightly doped symmetrical DG MOSFETs is then presented by considering weak and strong inversion regions including short channel effects, series source to drain resistance and channel length modulation parameters. These derived models are compared with the simulation results of the SILVACO (Atlas) tool for different channel lengths and silicon film thicknesses. Lastly, the effect of the fixed oxide charge on the drain current model has been studied through simulation. It is observed that the obtained analytical models of symmetrical double gate MOSFETs are in good agreement with the simulated results for a channel length to silicon film thickness ratio greater than or equal to 2.     

Modeling of subthreshold characteristics for undoped and doped deep nanoscale short channel double-gate MOSFETs

A model of subthreshold characteristics for both undoped and doped double-gate (DG) MOSFETs has been proposed. The models were developed based on solution of 2-D Poisson's equation using variable separation technique. Without any fitting parameters, our proposed models can exactly reflect the degraded subthreshold characteristics due to nanoscale channel length. Also, design parameters such as body thickness, gate oxide thickness and body doping concentrations can be directly reflected from our models. The models have been verified by comparing with device simulations' results and found very good agreement.     

Source/drain extension region engineering in nanoscale double gate SOI MOSFETs: Novel design methodology for low-voltage analog applications

The present paper proposes for the first time, a novel design methodology based on the optimization of source/drain extension (SDE) regions to significantly improve the trade-off between intrinsic voltage gain (A_VO) and cut-off frequency (f_T) in nanoscale double gate (DG) devices. Our results show that an optimally designed 25 nm gate length SDE region engineered DG MOSFET operating at drain current of 10 μA/μm, exhibits up to 65% improvement in intrinsic voltage gain and 85% in cut-off frequency over devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient and symmetric as well as asymmetrically designed SDE regions on key analog figures of merit (FOM) such as transconductance (g_m), transconductance-to-current ratio (g_m/I_ds), Early voltage (V_EA), output conductance (g_ds) and gate capacitances are examined in detail. The present work provides new opportunities for realizing future low-voltage/low-power analog circuits with nanoscale SDE engineered DG MOSFETs.     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

A new symmetrical double gate nanoscale MOSFET with asymmetrical side gates for electrically induced source/drain

In this paper, we present the unique features exhibited by a novel double gate MOSFET in which the front gate consists of two side gates as an extension of the source/drain. The asymmetrical side gates are used to induce extremely shallow source/drain regions on either side of the main gate. Using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing and the hot carrier effect. Based on our simulation results, we demonstrate that the proposed symmetrical double gate SOI MOSFET with asymmetrical side gates for the induced source/drain is far superior in terms of controlling the short-channel effects when compared to the conventional symmetrical double gate SOI MOSFET. We show that when the side gate length is equal to the main gate length, the device can be operated in an optimal condition in terms of threshold voltage roll-off and hot carrier effect. We further show that in the proposed structure the threshold voltage of the device is nearly independent of the side gate bias variation.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

An accurate two-dimensional CAD-oriented model of retrograde doped MOSFETs for improved short channel performance

An analytical CAD-oriented model for short channel threshold voltage of retrograde doped MOSFETs is developed. The model is extended to evaluate the drain induced barrier lowering parameter (R) and gradient of threshold voltage. The dependence of short channel threshold voltage and R on thickness of lightly doped layer (d) has also been analyzed in detail. It is shown that a retrograde doping profile reduces short channel effects to a considerable extent. A technique is developed to optimize the device parameters for minimizing short channel effects. The results so obtained are in close proximity with published data.     

An analytical drain current model of short-channel MOSFETs including source/drain resistance effect

In this paper, the DC characteristics of MOSFETs are investigated by means of an analytical approach with considerations of the source/drain parasitic resistance (R _S/R _D). Experimental data of MOS devices for DRAM design and results of TCAD simulation are used to verify the accuracy of theoretical calculation. It is found that both the R _S and R _D can induce a large reduction in the drain current in the linear region, but only the source resistance can cause a large reduction in the drain current in the saturation region. Moreover, the drain current deduction due to the R _S/R _D increases with decreasing channel length and oxide thickness.     

Analytical modeling of drain current and RF performance for double-gate fully depleted nanoscale SOI MOSFETs

A new 2D analytical drain current model is presented for symmetric double-gate fully depleted nanoscale SOI MOSFETs. Investigation of device parameters like transconductance for double-gate fully depleted nanoscale SOI MOSFETs is also carried out. Finally this work is concluded by modeling the cut-off frequency, which is one of the main figures of merit for analog/RF performance for double-gate fully depleted nanoscale SOI MOSFETs. The results of the modeling are compared with those obtained by a 2D ATLAS device simulator to verify the accuracy of the proposed model.     

Temperature dependent model for threshold voltage and subthreshold slope of strained-Si channel MOSFETs with a polysilicon gate

We present a temperature dependent model for the threshold voltage V_t and subthreshold slope S of strained-Si channel MOSFETs and validate it with reported experimental data for a wide range of temperature, channel doping concentration, oxide thickness and strain value. Such model includes the effect of lattice strain on material, temperature dependent effective mass of carriers, interface-trapped charge density and bandgap narrowing due to heavy channel doping. Also considered are polydepletion effects, carrier localization effect in the ultra-thin channel and quantum-mechanical effects. Our investigation reveals that the threshold voltage reduces linearly with increasing temperature whereas the subthreshold slope increases. In addition V_t is found to be sensitive to strain while S is weakly dependent on strain. Moreover, the channel doping concentration influences both V_t and S, and also the rate of change of V_t with temperature. Furthermore, S decreases for a lightly doped channel particularly at lower temperatures.     

2D analytical calculation of the electric field in lightly doped Schottky barrier double-gate MOSFETs and estimation of the tunneling/thermionic current

In this paper we present a new approach to calculate the channel electric field within a Schottky barrier Double-Gate MOSFET (SB-DG-MOSFET) in subthreshold region by solving Poissons equation. The Poisson equation is solved two dimensionally in an analytical closed-form with the conformal mapping technique. A comparison with data simulated by TCAD Sentaurus simulator for channel lengths down to 22 nm was made and shows an accurate agreement. Futhermore, a new way for the estimation of the tunneling current in SB-DG-MOSFET by applying the above 2D solution for the electric field and a 2D solution of the electrostatic potential is presented. Calculating the tunneling current, we use Wentzel-Kramers-Brillouin (WKB) approximation for the estimation of the tunneling probability. For the calculation of the tunneling and thermionic current a comparison with TCAD Sentaurus for channel lengths down to 65 nm was made.     

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate(CSG) MOSFETs has been developed.Based on this a subthreshold drain current model has also been derived.This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model.The fringing gate capacitances taken into account are outer fringe capacitance,inner fringe capacitance,overlap capacitance,and sidewall capacitance.The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.     

Feasible approach to the fabrication of asymmetric Schottky barrier MOSFETs by using the spacer technique

The spacer technique is proposed for the fabrication of the Asymmetric Schottky Barrier MOSFETs (ASB-MOSFET). The characteristics of the 45 nm and the 20 nm n-channel ASB-MOSFETs, which adopt a Schottky barrier height of 0.9 eV at source and that of 0.2 eV at drain, have been simulated and discussed by the comparisons with the conventional Schottky Barrier MOSFETs (SB-MOSFET). With a higher Ion/Ioff ratio, the ASB-MOSFET structure has shown a better performance than the conventional SB-MOSFETs.     

AlGaN/GaN HEMT低温直流特性研究

研究了20℃～-70℃栅宽为100μm、栅长为1μm的AlGaN/GaN HEMT的直流特性.随温度降低，电子迁移率增大，而二维电子气密度基本不变，HEMT饱和漏电流IDsat增大;阈值电压低温时有所下降，在一定温度范围内变化不明显，其原因除栅肖特基势垒高度、AlGaN/GaN导带差发生变化外，还可能与器件制备工艺和源极串联电阻有关。     

Characterization of GeSn materials for future Ge pMOSFETs source/drain stressors

In order to outperform current uniaxial compressively strained Silicon channel pMOSFET technology (with embedded SiGe source/drain), switching to strained Ge channel is mandatory. GeSn materials, having larger lattice parameter than Ge, are proposed in this article as embedded source/drain stressors for Ge channels. Our simulation results indicate that a minimum of 5% Sn is required in the GeSn source/drain to build a competitive strained Ge pMOSFETs with respect to strained Si channels. Therefore the compatibility of GeSn (with 2-8% Sn) materials with source/drain engineering processes (B implantation and activation and NiGeSn formation) has been studied. A low thermal budget has been determined for those processes on GeSn alloys: temperatures must be lower than 600 °C for B activation and lower than 450 °C for NiGeSn formation.     

Influence of temperature and drain current on source and drain resistances in AlGaN/GaN HEMTs

The behavior of source and drain resistances (R_S and R_D) has been studied for a wide range of drain currents at ambient temperatures from 150 to 500 K. Both parasitic resistances show an important increase as temperature rises, directly related to the reduction in the electron mobility. High drain currents also produce a non-linear increment of R_S and R_D, once the space-charge limited current is exceeded. Both temperature and drain current mechanisms have been modeled together by means of a simple equation, and a good agreement between simulations and measurements is found. Non-linear R_S and R_D allow a more accurate extraction of the intrinsic parameters, especially in the high drain current range. The use of variable parasitic resistances instead of their usually assumed constant values reveals higher intrinsic transconductance (g_m,int) and C_gs.     

自热和陷阱对AlGaN/GaN高电子迁移率晶体管漏极瞬态响应的影响

本文利用二维数值仿真研究了自热和陷阱对AlGaN/GaN高电子迁移率晶体管漏极瞬态响应的影响。分析了脉冲作用下漏极电流的变化;结果表明温度是漏极电流滞后的主要原因。漏极电流达到稳态的时间决定于热时间常数,这里为80微秒。详细讨论了脉冲作用下沟道电子密度和陷阱捕获电子数目的变化情况。结果表明当电场发生突变时,缓冲层受主陷阱是漏极电流崩塌的主要原因。并且沟道电子密度随沟道温度上升而增大。     

Stress analysis of Si1−xGex embedded source/drain junctions

The purpose of this paper is to evaluate the impact of the geometry of embedded Si_1−xGe_x source/drain junctions on the stress field. Stress simulations were performed using TSUPREM4 2D software to further investigate the elastic strain relaxation as a function of Si_1−xGe_x alloy active size, in the regime where no plastic relaxation is present. Moreover, the role of the epilayer thickness and the Ge content on the stress levels is also discussed. The work is complemented with experimental Raman spectroscopy.     

基于沟道及电极修饰的酞菁铜场效应晶体管的性能提高研究

利用对四联苯p -4P 以及五氧化二钒V2O5同时修饰导电沟道及源/漏电极,大幅 提高了基于酞菁铜CuPc场效应晶体管的性能。本文通过在绝缘层SiO2和有源层CuPc 之间插入p-4p缓冲薄层,同时在源/漏电极Al与有机半导体之间引入电极修饰层V2O5, 使得CuPc场效应晶体管的饱和迁移率和电流开/关比分别提高到5×10-2cm2 / V s和 104。p -4P能够诱导p型CuPc形成高度取向的连续薄膜,使得载流子能够在有源层中 更好地传输;而V2O5能够调节载流子的注入势垒,并可有效地降低沟道接触电阻(Rc)。 此方法能够在降低器件制备成本的前提下,大幅提高器件的性能。