Role of titanium in Ti/Ni ohmic contact on n-type 6H-SiC

A set of Ti/Ni metallizations with different thickness of the underlying titanium layer was prepared on 6H-SiC together with structures that contained only pure Ti and Ni. Samples were gradually annealed at 750-1150 °C. Structures Ti(2)/Ni(50) and Ti(100)/Ni(50) showed the lowest contact resistivity, 2 × 10⁻⁴ Ω cm² in both cases. For the Ti(2)/Ni(50) structure, low contact resistivity was reached most likely due to reduction of surface oxides on SiC by the thin titanium layer. In the Ti(100)/Ni(50) structure, the titanium layer prevents diffusion of nickel towards SiC and there is a layer containing mainly TiC at the interface with silicon carbide.     

SiC-DACFET

The nm-range abrupt doping profiles in SiC epitaxial layers are stable even after the high temperature process because SiC crystal exhibits little diffusion of impurities. Growth of the SiC delta-doped layers have been reported by our group and the others. We believe that the well-designed delta-doped epitaxial layers for the FET channels extend possibility of the power SiC FET. We proposed the SiC Delta-doped Accumulation Channel MOSFET (DACFET) consisting of the delta-doped layers for MOS channel and reported its high MOS-channel mobility.The vertical hot-wall-type CVD system was used to grow SiC epitaxial layers. The pulse valve, which supplied short (<ms) gas pulse flow, was directly connected to the CVD reactor to introduce the doping gases N₂. The pulse-doping technique enabled formation of the delta-doped-layer structure during SiC epitaxial growth. The n-type delta-doped layer as thin as 2 nm was fabricated with a peak N concentration of 1 × 10¹⁹ cm⁻³.The electrical characteristics of the DACFET, for example threshold voltage and R_on, can be tuned by controlling the delta-doped-layer structures in MOS channel. MOS-channel mobility of the normally-off lateral DACFET was measured to be >100 cm²/V s. The vertical DACFET, whose blocking voltage was >600 V, was fabricated with the double-implantation MOS process. R_on of the normally-off 2 μm-gate DACFET was measured to be 13 mΩ cm². Current density was observed to be >140 A cm⁻² larger than Si-IGBT. Shortening of gate length and unit cell size of the SiC-DACFET using high-resolution lithography will result in R_on <7 mΩ cm².     

Simultaneous Formation of Ni/Al Ohmic Contacts to Both n- and p-Type 4H-SiC

The fabrication procedure for silicon carbide power metal oxide semiconductor field-effect transistors can be improved through simultaneous formation (i.e., using the same contact materials and a one-step annealing process) of ohmic contacts on both the n-source and p-well regions. We have succeeded in the simultaneous formation of Ni/Al ohmic contacts to n- and p-type SiC after annealing at 1000°C for 5 min in an ultrahigh vacuum. Ohmic contacts to n-type SiC were found when the Al-layer thickness was less than about 6 nm, while ohmic contacts to p-type SiC were observed for an Al-layer thickness greater than about 5 nm. Only the contacts with an Al-layer thickness in the range of 5 nm to 6 nm exhibited ohmic behavior to both n- and p-type SiC, with a specific contact resistance of 1.8 × 10⁻⁴ Ω cm² and 1.2 × 10⁻² Ω cm² for n- and p-type SiC, respectively. An about 100-nm-thick contact layer was uniformly formed on the SiC substrate, and polycrystalline δ-Ni₂Si(Al) grains were formed at the contact/SiC interface. In the samples that exhibited ohmic behavior to both n- and p-type SiC, the distribution of the Al/Ni ratios in the δ-Ni₂Si(Al) grains was larger than that observed for any of the samples that showed ohmic behavior to either n- or p-type SiC. Furthermore, the grain size of the δ-Ni₂Si(Al) grains in the samples showing ohmic behavior to both n- and p-type SiC was smaller than the grains in any of the samples that showed ohmic behavior to either n- or p-type SiC. Thus, the large distribution in the Al/Ni ratios and a fine microstructure were found to be characteristic of the ohmic contacts to both n- and p-type SiC. Grains with a low Al concentration correspond to ohmic contacts to n-type SiC, while grains with a high Al concentration correspond to ohmic contacts to p-type SiC.     

Al contacts to nanoroughened p-GaN

Nanoroughening of a p-GaN surface using nanoscale Ni islands as an etch mask was utilized to investigate the feasibility for the flip-chip configuration light-emitting diodes (LEDs) using an Al-based reflector. Improved ohmic characteristics were found for the nanoroughened sample. A specific contact resistivity of 8.9×10⁻² Ω cm² and a reflectance of 82% at 460 nm were measured for the nanoroughened Al contact. The Schottky barrier heights were decreased from 0.81 eV (I-V) and 0.84 eV (Norde) for the Al contact to 0.70 eV (I-V) and 0.69 eV (Norde) for the nanoroughened Al contact. The barrier height reduction may be attributed to enhanced tunneling and the increased contact area due to the nanoroughening. This work suggests that the ohmic contact characteristics and the light extraction efficiency may be improved further with a well-defined nanopatterned p-GaN layer.     

Characteristics of Ni/SiC Schottky diodes grown by ICP-CVD

A Ni/SiC Schottky diode was fabricated with an α-SiC thin film grown by the inductively coupled plasma chemical vapor deposition, ICP-CVD method on a (1 1 1) Si wafer. The α-SiC film was grown on a carbonized Si layer that the Si surface had been chemically converted to a very thin SiC layer by the ICP-CVD method at 700 °C. To reduce defects between the Si and α-SiC, the surface of the Si wafer is slightly carbonized. The film characteristics of α-SiC were investigated by employing TEM and FT-IR. A sputtered Ni thin film was used for the anode metal. The boundary status of the Ni/SiC contact was investigated by AES as a function of annealing temperature. It is shown that the ohmic contact could be acquired below 1000 °C annealing temperature. The forward voltage drop of the Ni/α-SiC Schottky diode is 1.0 V at 100 A/cm². The breakdown voltage is 545 V which is five times larger than the ideal breakdown voltage of a silicon device. Also, the dependence of barrier height on temperature was observed.     

Improved Thermal Stability Observed in Ni-Based Ohmic Contacts to <Emphasis Type="Italic">n</Emphasis>-Type SiC for High-Temperature Applications

The high-temperature stability of a Pt/TaSi₂/Ni/SiC ohmic contact metallization scheme was characterized using a combination of current–voltage measurements, Auger electron spectroscopy, and transmission electron microscopy imaging and associated analytical techniques. Increasing the thicknesses of the Pt and TaSi₂ layers promoted electrical stability of the contacts, which remained ohmic at 600°C in air for the extent of heat treatment; the specific contact resistance showed only a gradual increase from an initial value of 5.2 × 10⁻⁵ Ω cm². We observed a continuous silicon oxide layer in the thinner contact structures, which failed after 36 h of heating. Meanwhile, thicker contacts with enhanced stability contained a much lower oxygen concentration that was distributed across the contact layers, precluding the formation of an electrically insulating contact structure.     

Ohmic contacts to single-crystalline 3C-SiC films for extreme-environment MEMS applications

This paper describes the ohmic contacts to single-crystalline 3C-SiC thin films heteroepitaxially grown on Si (0 0 1) wafers. In this work, a TiW (titanium-tungsten) film was deposited as a contact material by RF magnetron sputter and annealed through the vacuum and rapid thermal anneal (RTA) process. Contact resistivity between the TiW film and the n-type 3C-SiC substrate was measured by the circular transmission line model (C-TLM) method. The contact phases and interface of the TiW/3C-SiC were evaluated with X-ray diffraction (XRD), scanning electron microscope (SEM) and Auger electron spectroscopy (AES) depth-profiles. The TiW film annealed at 1000 °C for 45 s with the RTA plays an important role in the formation of ohmic contact with the 3C-SiC film and the contact resistance is less than 4.62×10⁻⁴ Ω cm². Moreover, the inter-diffusion at the TiW/3C-SiC interface was not generated during, before and after annealing, and was kept in a stable state. Therefore, the ohmic contact formation technology of single-crystalline 3C-SiC films by using the TiW film is very suitable for high-temperature micro-electro-mechanical system (MEMS) applications.     

Simultaneous formation of p- and n-type ohmic contacts to 4H-SiC using the ternary Ni/Ti/Al system

Fabrication procedures for silicon carbide power metal oxide semiconductor field effect transistors (MOSFETs) can be improved through simultaneous formation (i.e., same contact materials and one step annealing) of ohmic contacts on both the p-well and n-source regions. We have succeeded with the simultaneous formation of the ohmic contacts for p- and n-type SiC semiconductors by examining ternary Ni/Ti/Al materials with various compositions, where a slash symbol “/” indicates the deposition sequence starting with Ni. The Ni(20 nm)/Ti(50 nm)/Al(50 nm) combination provided specific contact resistances of 2 × 10⁻³ Ω-cm² and 2 × 10⁻⁴ Ω-cm² for p- and n-type SiC, respectively, after annealing at 800°C for 30 min, where the doping level of Al in the SiC substrate was 4.5 × 10¹⁸ cm⁻³ and the level of N was 1.0 × 10¹⁹ cm⁻³.     

High quality relaxed Ge layers grown directly on a Si(0 0 1) substrate

After a long period of developing integrated circuit technology through simple scaling of silicon devices, the semiconductor industry is now embracing technology boosters such as strain for higher mobility channel material. Germanium is the logical supplement to enhance existing technologies, as its material behaviour is very close to silicon, and to create new functional devices that cannot be fabricated from silicon alone (Hartmann et al. (2004) [1]). Germanium wafers are, however, both expensive and less durable than their silicon counterparts. Hence it is highly desirable to create a relaxed high quality Ge layer on a Si substrate, with the provision that this does not unduly compromise the planarity of the system. The two temperature method, proposed by Colace et al. (1997) [2], can give smooth (RMS surface roughness below 1 nm) and low threading dislocation density (TDD <10⁸ cm⁻²) Ge layers directly on a Si(0 0 1) wafer (Halbwax et al. (2005) [3]), but these are currently of the order of 1-2 μm thick (Hartmann et al. (2009) [4]).We present an in depth study of two temperature Ge layers, grown by reduced pressure chemical vapour deposition (RP-CVD), in an effort to reduce the thickness. We report the effect of changing the thickness, of both the low temperature (LT) and the high temperature (HT) layers, emphasising the variation of TDD, surface morphology and relaxation.Within this study, the LT Ge layer is deposited directly on a Si(0 0 1) substrate at a low temperature of 400 °C. This low temperature is known to generate monolayer islands (Park et al. (2006) [5]), but is sufficiently high to maintain crystallinity whilst keeping the epitaxial surface as smooth as possible by suppressing further island growth and proceeding in a Frank-van der Merwe growth mode. This LT growth also generates a vast number of dislocations, of the order of 10⁸-10⁹ cm⁻², that enable the next HT step to relax the maximum amount of strain possible. The effect of varying the HT layer thickness is studied by depositing on a LT layer of fixed thickness (100 nm) at a higher growth temperature of 670 °C. We find that the HT layer allows Ge-on-Ge adatom transport to minimise the surface energy and smooth the layer. The final step to the technique is annealing at a high temperature that allows the dislocations generated to glide, increasing the degree of relaxation, and annihilate. We find that annealing can reduce the TDD to the order of 10⁷ cm⁻², but at a cost of a significantly roughened surface.     

Heavily Aluminum-Doped Epitaxial Layers for Ohmic Contact Formation to <Emphasis Type="Italic">p</Emphasis>-Type 4H-SiC Produced by Low-Temperature Homoepitaxial Growth

In this work, heavily aluminum (Al)-doped layers for ohmic contact formation to p-type SiC were produced by utilizing the high efficiency of Al incorporation during the epitaxial growth at low temperature, previously demonstrated by the authors’ group. The low-temperature halo-carbon epitaxial growth technique with in situ trimethylaluminum (TMA) doping was used. Nearly featureless epilayer morphology with an Al atomic concentration exceeding 3 × 10²⁰ cm⁻³ was obtained after growth at 1300°C with a growth rate of 1.5 μm/h. Nickel transfer length method (TLM) contacts with a thin adhesion layer of titanium (Ti) were formed. Even prior to contact annealing, the as-deposited metal contacts were almost completely ohmic, with a specific contact resistance of 2 × 10⁻² Ω cm². The specific contact resistance was reduced to 6 × 10⁻⁵ Ω cm² by employing a conventional rapid thermal anneal (RTA) at 750°C. Resistivity of the epitaxial layers better than 0.01 Ω cm was measured for an Al atomic concentration of 2.7 × 10²⁰ cm⁻³.     

Normally-off trench JFET technology in 4H silicon carbide

A double gate normally-off silicon carbide (SiC) trench junction field effect transistors (JFET) design is considered. Innovative migration enhanced embedded epitaxial (ME³) growth process was developed to replace the implantation process and realize high device performance. Strong anisotropic behavior in electrical characteristics of the pn junction fabricated on (1 1 −2 0) and (1 −1 0 0) trench a-planes was observed, although quality of the pn diodes was found to be independent of trench plane orientations. Fabricated normally-off trench 4H-SiC JFET demonstrates the potential for lower specific on-resistance (R_onS) in the range of 5-10 mΩ cm² (1200 V class). A relative high T^−2.6 dependence of R_onS is observed. A breakdown voltage of 400 V in the avalanche mode was confirmed at zero gate bias conditions for cell design without edge termination. It was demonstrated that the normally-off JFETs are suitable for high temperature applications. Average temperature coefficient of threshold voltage (V_th) was calculated as −1.8 mV/°C, which is close to the MOS based Si power devices.     

Microstructural properties of thermally stable Ti/W/Au ohmic contacts on n-type GaN

We have investigated the microstructural and electrical characteristics of Ti/W/Au ohmic contacts on n-type GaN (4.0 × 10¹⁸ cm⁻³) using Auger electron spectroscopy (AES) and transmission electron microscopy (TEM) after annealing at 900 °C. It is shown that the electrical properties are improved upon annealing at 900 °C for 1 min in nitrogen ambient. The 900 °C annealed contact produced a specific contact resistance of 8.4 × 10⁻⁶ Ω cm². It is further shown that the contact exhibits thermal stability during annealing at 900 °C. Based on the Auger electron microscopy and transmission electron microscopy studies, the formation of TiN layer results in an excess of N vacancies near the surface of the GaN layer, which could be the reason for the low-resistance of the Ti/W/Au contact.     

Four-point probe characterization of 4H silicon carbide

We report on four-point probe measurements on SiC wafers as such measurements give erratic data. Current-voltage measurements on n-type SiC wafers doped to 3 × 10¹⁸ cm⁻³ are non-linear and single probe I-V measurements are symmetrical for positive and negative voltages. For comparison, similar measurements of p-type Si doped to 5 × 10¹⁴ cm⁻³ gave linear I-V, well-defined sheet resistance and the single probe I-V curves were asymmetrical indicating typical Schottky diode behavior. We believe that the reason for the non-linearity in four-point probe measurements on SiC is the high contact resistance. Calculations predict the contact resistance of SiC to be approximately 10¹² Ω which is of the order of the input resistance of the voltmeter in our four-point probe measurements. There was almost no change in two-probe I-V curves when the spacing between the probes was changed from 1 mm to 2 cm, further supporting the idea that the I-V characteristics are dominated by the contact resistance.     

Correlation between the electrical properties and the interfacial microstructures of TiAl-based ohmic contacts to p-type 4H-SiC

In order to understand a mechanism of TiAl-based ohmic contact formation for p-type 4H-SiC, the electrical properties and microstructures of Ti/Al and Ni/Ti/Al contacts, which provided the specific contact resistances of approximately 2×10⁻⁵ Ω-cm² and 7×10⁻⁵ Ω-cm² after annealing at 1000°C and 800°C, respectively, were investigated using x-ray diffraction (XRD) and high-resolution transmission electron microscopy (HRTEM). Ternary Ti₃SiC₂ carbide layers were observed to grow on the SiC surfaces in both the Ti/Al and the Ni/Ti/Al contacts when the contacts yielded low resistance. The Ti₃SiC₂ carbide layers with hexagonal structures had an epitaxial orientation relationship with the 4H-SiC substrates. The (0001)-oriented terraces were observed periodically at the interfaces between the carbide layers and the SiC, and the terraces were atomically flat. We believed the Ti₃SiC₂ carbide layers primarily reduced the high Schottky barrier height at the contact metal/p-SiC interface down to about 0.3 eV, and, thus, low contact resistances were obtained for p-type TiAl-based ohmic contacts.     

Simultaneous Formation of Ohmic Contacts on p +- and n +-4H-SiC Using a Ti/Ni Bilayer

In this work, Ti/Ni bilayer contacts were fabricated on both p ⁺- and n ⁺-4H-SiC formed by ion implantation, and the effects of the Ti interlayer on the contact resistance and interfacial microstructure were studied. Adoption of a thin (10 nm) Ti interlayer resulted in specific contact resistance of 4.8 μΩ cm² and 1.3 mΩ cm² on n ⁺- and p ⁺-4H-SiC, respectively, comparable to the values for contacts using only Ni. Moreover, contacts using Ti/Ni provide a flat and uniform interface between Ni₂Si and SiC, whereas discontinuous, agglomerated Ni₂Si islands are formed without the use of a Ti interlayer. In addition, the Ti interlayer was demonstrated to effectively dissociate the thin oxide film on SiC, which is advantageous for low-resistance, reliable ohmic contact formation. In summary, use of a Ti/Ni bilayer is a promising solution for one-step formation of ohmic contacts on both p ⁺- and n ⁺-4H-SiC, being especially suitable for SiC n-channel metal-oxide-semiconductor field-effect transistor (nMOSFET) fabrication.     

Analytic computation of the photocurrent density in a n-6H-SiC/p-Si/n-Si/p-Si0.8Ge0.2 multilayer solar cell

In this work we conceived a model of a multilayer solar cell composed by four layers of opposite conductivities: an n-type 6H-SiC used as a frontal layer to absorb high energy photons (energy gap equals 2.9 eV), a p-type Si layer, an n-type Si layer and a p-type SiGe back layer to absorb low energy photons (Si_0.8Ge_0.2 with an energy gap equal to 0.8 eV). The impurity concentration in every layer of the model is taken equal to 10¹⁷ cm⁻³ to ensure abrupt junctions inside the cell. The optical properties of the separate layers have been fitted and tabulated to be used for thin films devices numerical simulation. We developed the equations giving the minority carrier concentration and the photocurrent density in each abscissa of the model. We used Matlab software to simulate and optimize the layers thicknesses to achieve the maximum photocurrent generated under AM0 solar spectrum. The results of simulation showed that the optimized structure could deliver, assuming 10⁵ cm/s surface recombination velocity, a photocurrent density of more than 53 mA/cm², which represents 88.3% of the ideal photocurrent (59.99 mA/cm²) that can be generated under AM0 solar spectrum.     

Investigation on the effect of annealing process parameters on AuGeNi ohmic contact to n-GaAs using microstructural characteristics

The electrical and structural properties of AuGeNi ohmic contact to n-GaAs have been studied. A combination of EDX and X-ray diffraction analysis was used to examine the reactions between AuGeNi-based metallization and GaAs. Scanning Tunneling Microscope (STM) was used to study surface morphology and surface roughness. By the use of Rapid Thermal Annealing (RTA), contact resistivity as low as 5.5 × 10⁻⁸ Ω cm² have been obtained. The minimum in the contact resistivity coincides with the formation of AuGa and NiAs phases. On the other hand, poor thermal stability after contact formation was concluded to be due to the formation of low melting point AuGa phases. Formation of dark particles, recognized as GeNi particles, in different distributions and shapes after annealing, was found to be essential for low contact resistivity. Correlation between GeNi particles distribution and contact resistivity was found and introduced as d/λ parameter. It was found that the lower the size of these particles (d) as well as the larger the contact area over which they are distributed (λ) leading to the better contact resistivity.     

Temperature behavior and modeling of ohmic contacts to Si implanted n-type GaN

The behavior of an ohmic contact to an implanted Si GaN n-well in the temperature range of 25-300 °C has been investigated. This is the sort of contact one would expect in many GaN based devices such as (source/drain) in a metal-oxide-semiconductor transistor. A low resistivity ohmic contact was achieved using the metal combination of Ti (350 Å)/Al (1150 Å) on a protected (SiO₂ cap) and unprotected samples during the post implantation annealing. Sheet resistance of the implanted layer and metal-semiconductor contact resistance to N⁺ GaN have been extracted at different temperatures. Both, the experimental sheet resistance and the contact resistance decrease with the temperature and their characteristics are fitted by means of physical based models.     

Schottky barrier height modification in Au/n-type 6H-SiC structures by PbS interfacial layer

We have prepared the Au/PbS/n-6H-SiC Schottky diodes with interface layer and the reference Au/n-6H-SiC/Ni Schottky diodes without interface layer to realize Schottky barrier height (SBH) modification in the Au/SiC Schottky diodes. The BH reduction has been succeeded by the PbS interlayer to modify the effective BH by influencing the space charge region of the SiC. The PbS thin layer on the SiC was formed by the vacuum evaporation. The SBH values of 0.97 and 0.89 eV for the samples with and without the interfacial PbS layer were obtained from the forward bias current-voltage (I-V) characteristics. X-ray diffraction (XRD) study was carried out to determine the structural formation of the PbS on SiC. The reduction of the BH in the Au/PbS/n-6H-SiC Schottky diodes has been attributed to the fact that the interface states have a net positive interface charge in metal/n-type semiconductor contact, and thus the positive space charge Q_sc in the Au/PbS/n-6H-SiC Schottky diodes becomes smaller than if the interface state charges Q_ss were absent. The experimental carrier concentration value of 4.73 × 10¹⁷ cm⁻³ obtained from the forward and reverse bias capacitance-voltage characteristics for the Au/PbS/n-6H-SiC contacts is lower than the value of 5.52 × 10¹⁷ cm⁻³ obtained for the reference diode, and this is an evidence of the reduction of the BH by the modification of the space charge density of the SiC.     

Structural and electrical characteristics of RF-sputtered HfO2 high-k based MOS capacitors

The HfO₂ high-k thin films have been deposited on p-type (1 0 0) silicon wafer using RF magnetron sputtering technique. The XRD, AFM and Ellipsometric characterizations have been performed for crystal structure, surface morphology and thickness measurements respectively. The monoclinic structured, smooth surface HfO₂ thin films with 9.45 nm thickness have been used for Al/HfO₂/p-Si metal-oxide-semiconductor (MOS) structures fabrication. The fabricated Al/HfO2/Si structure have been used for extracting electrical properties viz dielectric constant, EOT, barrier height, doping concentration and interface trap density through capacitance voltage and current-voltage measurements. The dielectric constant, EOT, barrier height, effective charge carriers, interface trap density and leakage current density are determined are 22.47, 1.64 nm, 1.28 eV, 0.93 × 10¹⁰, 9.25 × 10¹¹ cm⁻² eV⁻¹ and 9.12 × 10⁻⁶ A/cm² respectively for annealed HfO₂ thin films.