服务于IC产业的MEMS探卡

圆片级芯片测试在IC制造工艺中已经成为不可或缺的一部分,发挥着重要的作用,而测试探卡在圆片级芯片测试过程中起着关键的信号通路的作用。分析指出由于芯片管脚密度的不断增加以及在高频电路中应用的需要,传统的组装式探卡将不能适应未来的测试要求;和传统探卡的组装方法相比,MEMS技术显然更适应当今的IC技术。综述了针对MEMS探卡不同的应用前景所提出的多种技术方案,特别介绍了传感技术国家重点实验室为满足IC圆片级测试的要求,针对管脚线排布型待测器件的新型过孔互连式悬臂梁芯片和针对管脚面排布型待测器件的Ni探针阵列结构的设计和制造。     

Novel analysis model for investigation of contact force and scrub length for design of probe card

Fabrication defects in IC chips are generally identified using a multi-layer needle probe card. To prolong the life of the card, the needles in each layer should experience a similar contact force and should produce a scrub mark of minimal length. To facilitate the probe card design process, this paper proposes an analytical model for evaluating the contact force and scrub mark length of a single-needle probe as a function of the overdrive distance. The model is based on Castigliano’s displacement theorem and takes account of both the material and the geometric properties of the needle. The validity of the analytical model is confirmed by performing a series of finite-element simulations at overdrive distances ranging from 30 to 70 μm. In addition, experimental probe card tests are performed using a tungsten needle probe and an aluminum pad. A good agreement is found between the experimental and analytical results for overdrive distances in the range 50 ± 10 μm. Overall, the results presented in this study confirm that the proposed analytical model provides an accurate and convenient means of determining the optimal needle probe design given maximum permissible values of the contact force and scrub mark length, respectively.     

Application of a Genetic Algorithm to the Design Optimization of a Multilayer Probe Card for Wafer-Level Testing

The number of input and output pads on high-performance IC devices has increased in recent years, and hence wafer-level testing is conventionally performed using a probe card with a multilayer needle layout. This paper employs ANSYS commercial software and a Genetic Algorithm (GA) to optimize the design parameters of a multilayer needle probe card such that the scrub marks produced by the different needle layers are of approximately equal length. A dummy probe card containing both a conventional multilayer needle layout and the optimized needle layout is then fabricated and used in a series of single-contact probing tests. The results reveal that the scrub marks produced by the optimized needle layout are both shorter and of a more uniform length that those produced by the conventional needle design. For both needle layouts, a lower and more stable contact resistance is obtained as the overdrive distance is increased. Finally, a multicontact probing test is performed to evaluate the effect on the contact resistance of probe tip contamination following repeated surface contacts. The results show that the needles in the optimized layout are less heavily contaminated than those in the conventional layout, and hence the contact resistance is both lower and more stable. As a consequence, the probe card requires cleaning less frequently and hence its service life is improved.     

Silicon cantilever arrays with by-pass metal through-silicon-via (TSV) tips for micromachined IC testing probe cards

In this paper, an integrated probe card is proposed and developed for wafer-level IC testing. Based on micromachining technology, totally about 26,000 cantilever-tip probes can be formed simultaneously in one 4-in. silicon wafer, with the minimum pitch of 35 μm for adjacent probing tips. The probe card is designed with a novel composite structure that combines both single-crystalline silicon and electroplated metals. In the composite structure, a novel bypass through-silicon-via with a low aspect ratio can be high-yield fabricated for transferring the testing signals from the probing sided (at the wafer bottom side) to the I/O interface (at the front side). The probe card makes full use of the advantages of the single-crystal silicon and the electroplated nickel and copper. Bulk micromachined silicon cantilevers behave uniform probing height and a good elastic deformation property, while the electroplated nickel probing tips promise high hardness and satisfactory electric contact performance with the dies-under-test (DUT). Measurements show that the fabricated cantilever is able to withstand a contact force of 80mN by a tip displacement of 20 μm. The measured contact resistances on metal pads (Al, Cu, and Au) are all below 1 Ω, whereas the maximum current leakage is 64 pA for 3.3 V voltage across two adjacent tips. After a probing reliability test of 100,000 cycles, the cantilever-tip shows no sign of any performance degradation.     

Geometric design for ultra-long needle probe card for digital light processing wafer testing

The probe card with ultra-long probing needles is specifically designed for probe testing of wafers that feature protruding housing for digital micromirror devices (DMD) for digital light processing (DLP) applications. Compared with a conventional short probing needle, an ultra-long probing needle leaves a smaller scrub mark on the pad during probe testing but it suffers the risk from buckling. In this work, three-dimensional finite element models were developed and validated by experiments for single conventional and ultra-long probing needles to analyze their mechanical responses during wafer-level probe testing. Following the Taguchi method, we conducted separate optimal geometric designs for an ultra-long probing needle with respect to the minimized scrub length and minimized buckling potential. It was found that a long beam length of the ultra-long probing needle is preferred in reducing both scrub length and buckling potential. A compromised design that considers minimizing scrub length and buckling potential conjointly but with different weightings was presented.     

Measurement and analysis of contact resistance in wafer probe testing

When testing IC chips using a wafer probe card, maintaining a low and stable contact resistance is essential. However, the electrical contact between the probe and the bonding pad of the IC chip becomes unstable following repeated probing operations since particles from the chip surface gradually accumulate on the probe tip. The contamination caused by these particles causes the contact resistance to increase. Accordingly, this study develops an experimental procedure for investigating the effect of the particle contamination on the magnitude and stability of the contact resistance. Initially, an experiment is performed to establish the contact resistance between a clean tungsten probe and various specimen surfaces, i.e. aluminum, gold and copper, at various levels of overdrive. Subsequently, an experiment is conducted to investigate the accumulation of surface particles on the probe tip following multiple contacts of the probe with the wafer surface. The extent of particle contamination following 10,000, 30,000 and 50,000 contacts, respectively, is examined using a scanning electron microscope (SEM). The contact resistance of the contaminated probes is then measured at various levels of overdrive. The experimental results are then integrated to establish a suitable tradeoff between the contact resistance, the overdrive displacement, and the number of contacts.The results from the contact resistance experiment conducted using a clean tungsten probe indicate that the surface specimens with a lower resistively generate a lower contact resistance. For example, the contact resistance between the tungsten probe and the copper foil is approximately 100 mΩ, and becomes stable at an overdrive of 45 μm. However, the contact resistance increases with an increasing number of contacts. In general, the probe should be removed for cleaning following 30,000 contacts to ensure that a contact resistance of less than 1 Ω is maintained.     

Design Optimization of Needle Geometry for Wafer-Level Probing Test

The probing test is a typical quality control method for individual chips on a wafer. With a proper design, the service life of probing needles in the probe card can be sufficiently elongated and hence reduces the testing cost. In this paper, we followed the Taguchi method with the $L_{18}(2^{1}times 3^{7})$ orthogonal array to obtain an optimal geometrical design of the probing needle based on the minimization of the scrub length the probe tip travels during a wafer-level probing test procedure. Geometrical factors of the needle included tip shape, needle diameter, beam length, taper length, knee diameter, shooting angle, tip length, and tip diameter. Importance of theses factors on the scrub length was also ranked.      

Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink

Power dissipation in microprocessors will reach a level that necessitates chip-level liquid cooling in the near future. An on-chip microfluidic heat sink can reduce the thermal interfaces between an IC chip and the convective cooling medium. Through wafer-level processing, integrated thermal-fluidic I/O interconnects enable on-chip microfluidic heat sinks with ultrasmall form factor at low-cost. This letter describes wafer-level integration of microchannels at the wafer back-side with through-wafer fluidic paths and thermal-fluidic input/output interconnection for future generation gigascale integrated chips.     

Sea of Leads (SoL) ultrahigh density wafer-level chip input/output interconnections for gigascale integration (GSI)

Sea of Leads (SoL) is an ultrahigh density (>10/sup 4//cm/sup 2/) compliant chip input/output (I/O) interconnection technology. SoL is fabricated at the wafer level to extend the economic benefits of semiconductor front-end and back-end wafer-level batch fabrication to include chip I/O interconnections, packaging, and wafer-level testing and burn-in. This paper discusses the fabrication, the mechanical and electrical performance, and the benefits of SoL. SoL can lead to enhancements in reliability, electrical performance, manufacturing throughput, and cost. A chip with 12 /spl times/ 10/sup 3//cm/sup 2/ compliant I/O leads is demonstrated. The mechanically compliant I/O leads are designed to enable wafer-level testing and eliminate the need for underfill between chips and printed wiring boards by mitigating thermo-mechanical expansion mismatches between the two. The fabrication of partially nonadherent, or slippery, leads is desirable as it allows the leads to freely undergo strain during thermal cycling. Compared to adherent metal leads, preliminary results show that slippery leads enhance the overall in-plane compliance. Microindentation experiments show that a polymer film with embedded air gaps provides substantially higher compliance than a polymer film without embedded air gaps.     

晶圆级封装非制冷大面阵红外探测器应用分析

红外成像系统已经应用到军事和民用领域多年,但一直没得到广泛应用,主要原因是其分辨率低、成本高、工艺不稳定和技术门槛高等。解决这些问题需要从传感器工艺、探测器封装、红外图像处理芯片等方面加以改进。红外技术未来会朝低成本、专用处理芯片、高分辨率等方向发展。目前,国内厂商陆续推出了晶圆级封装(Wafer-Level Package,WLP)、高分辨率探测器和专用图像处理芯片等方面的新产品。但采用这些新器件的红外成像系统却没有得到相应的研究。本文主要基于烟台艾睿光电科技有限公司新推出的晶圆级封装的1280×1024元红外探测器以及专用图像处理芯片的实际应用,在系统架构、结构散热、成像算法等方面对由新器件构建的红外成像系统进行了验证分析。     

Reliability challenges in 3D IC packaging technology

At the moment, a major paradigm change, from 2D IC to 3D IC, is occurring in microelectronic industry. Joule heating is serious in 3D IC, and vertical interconnect is the critical element to be developed. Also reliability concerns will be extremely important. For example, in order to remove heat, a temperature gradient must exist in the packaging. If we assume just a difference of 1 °C across a micro-bump of 10 μm in diameter, the temperature gradient is 1000 °C/cm which cannot be ignored due to thermomigration. Equally challenging reliability issues are electromigration and stress-migration. Since the 3D IC structure is new, the details of reliability problems are mostly unknown. This paper presents a projection of the reliability challenges in 3D IC packaging technology on the basis of what we have known from flip chip technology.     

Anodic bonding of glass and silicon wafers with an intermediate silicon nitride film and its application to batch fabrication of SPM tip arrays

This paper reports a detailed study of wafer-level anodic bonding with a dielectric intermediate layer and its application to the fabrication of scanning probe microscope (SPM) probe arrays. First, the bonding performance between sodium-ion rich glass and silicon nitride coated silicon substrate is characterized. The effects of voltage, tool pressure, bonding time, surface properties, and cleanliness are thoroughly studied. Then, the silicon nitride based SPM probe arrays consisted of pyramidal tip and 1.5 μm-thickness cantilever are successful bonded and transferred to Pyrex 7740 glass substrate by use of our optimized wafer-scale electrostatic force bonding condition. The nano-imaging capability of the scanning probe array is also demonstrated.     

/spl beta/-Helix: a lithography-based compliant off-chip interconnect

Microsystems packages continue to demand lower cost, higher reliability, better performance and smaller size. Compliant wafer-level interconnects show great potential for next-generation packaging. The proposed /spl beta/-Helix interconnect, an electroplated compliant wafer-level off-chip interconnect, can facilitate wafer-level probing as well as wafer-level packaging without the need for an underfill. The fabrication of the /spl beta/-Helix interconnect is similar to conventional integrated circuit (IC) fabrication processes and is based on electroplating and photolithography. /spl beta/-Helix interconnect has good mechanical compliance in the three orthogonal directions and can accommodate the differential displacement induced by the coefficient of thermal expansion (CTE) mismatch between the silicon die and the organic substrate. In this paper, we report the wafer-level fabrication of area-arrayed /spl beta/-Helix interconnects. The geometry effect on the mechanical compliance and the electrical parasitics of /spl beta/-Helix interconnect has been studied. Thinner and narrower arcuate beams with larger radius and taller post are found to have better mechanical compliance. However, it is also found that structures with excellent mechanical compliance cannot have good electrical performance. Therefore, a trade off is needed. Using response surface methodology (RSM), an optimization has been done, and the optimal compliant /spl beta/-Helix interconnect will have a total standoff height of 110 /spl mu/m, radius of 37 /spl mu/m and cross section area of 525 /spl mu/m/sup 2/. It is also found that the structure self-weight effect during the fabrication and the die and heat sink weights during the assembly have negligible effect on the /spl beta/-Helix interconnect, especially when the interconnect density is high.     

Low cost bulk-silicon CDMOS technology and enhanced dv/dt high voltage driver circuit for PDP data driver IC

In this paper, a 256-channel data driver IC for plasma display panels (PDPs) is proposed. A new low cost 0.5 μm bulk-silicon CDMOS (CMOS and DMOS) technology is developed, resulting in the improvement of input data frequency up to 120 MHz and reduction of die cost about 20% compared with the conventional one. A novel high voltage driver circuit is also presented to optimize dv/dt of the output signal from 1.2 to 0.2 V/ns. The proposed circuit can avoid unwanted turning on of the pLEDMOS transistors in output stage and cut down the power dissipation by 12% compared with the conventional one. The application results show rising and falling times of the output stage are 45 and 84 ns, respectively.     

圆片级真空封装技术在MEMS陀螺中的应用

为维持MEMS硅微陀螺的真空度,利用两次硅-玻璃阳极键合和真空长期维持技术,实现了MEMS硅微陀螺的圆片级真空气密性封装。制作过程包括:先将硅和玻璃键合,在硅-玻璃衬底上采用DRIE工艺刻蚀出硅振动结构;再利用MEMS圆片级阳极键合工艺在10-5 mbar(1 mbar=100 Pa)真空环境中进行封装;最后利用吸气剂实现圆片的长期真空气密性。经测试,采用这种方式制作出的硅微陀螺键合界面均匀平整无气泡,漏率低于5.0×10-8 atm.cm3/s。对芯片进行陶瓷封装,静态下测试得出品质因数超过12 000,并对样品进行连续一年监测,性能稳定无变化。     

Experimental method and FE simulation model for evaluation of wafer probing parameters

Wafer probing technology is a critical testing technology that is used in the semiconductor manufacturing and packaging process. A well-designed probing system must enable low and stable contact resistance when each needle-like probe makes contact with the IC chip-bonding pad. Mechanical contact using excessive probe force causes over-sized scrub marks that may damage the die pad and sizably deform the probe tip. In this paper, an experimental setup of a single tungsten needle probe making contact with an Al pad was employed to investigate the relationships between the overdrive, contact force, and scrub mark length. A three-dimensional computational probing simulation model was developed for analyzing dynamic deformations of the contact phenomena during wafer testing. The mechanical tensile strength of the tungsten needle was tested with a micro-tester to examine the tensile stress-strain relationship. The elastoplastic behaviors of the probe and die were taken into account in the simulation model. The resultant scrub lengths from the simulation were verified against the experimental data. Additional critical data, such as data of the scrub mark sinking on the die surface and the maximum Von-Mises stress level location at the probe tips, can be predicted. The experimental and numerical methods presented here can be used as useful performance evaluation tools to support the choice of suitable probe geometry and wafer probe testing parameters.     

Electrical test strategies for a wafer-level packaging technology

A wafer-level packaging (WLP) technology is under development that provides compliant electrical leads with a density as high as 12,000 per cm/sup 2/. The leads are batch processed while the integrated circuits are still in wafer form through a series of relatively simple photolithographic steps. After electrical testing, the wafers are diced and the integrated circuits (ICs) are ready for direct assembly to an interconnect substrate. Sufficient lateral and vertical compliance is provided by the leads to accommodate the nonplanarity encountered during assembly and the thermal mismatch between the IC and substrate during normal operation. The high density of compliant leads presents both challenges and opportunities for electrical testing. This paper first summarizes the process technology used to fabricate these high-density electrical contacts. Several potential test strategies are then introduced that may take advantage of these contacts.     

On the status of wafer-level metal integrity testing

Wafer-level metal integrity testing is very complex. Trade-offs with test time, stress temperature, test structure, stress technique, and true understanding of the stress, are all involved and are discussed in this work. A discussion of conventional electromigration stress execution issues is provided as a prelude to highly accelerated metal integrity testing in the last section. Much of the published work in wafer-level EM and metal integrity testing is used to help describe the issues and trade-offs involved.     

Effect of the spatial distribution of SiO2 thickness on the switching behavior of bistable MOS tunnel structures

Simulations of the reverse current-voltage characteristics of an Al/l-3 nm SiO₂/n-Si tunnel structure are carried out, considering the spatial non-uniformity of oxide thickness. In a certain range of average thickness, these characteristics are S-shaped, exhibiting thereby a bistability. The shift of the turn-on and holding voltages related to the thickness deviation is predicted. The electric overload leads to the displacement of switching voltages as if the deviation of oxide thickness had became larger. Supporting experimental data are also provided.     

A 1.0 V power supply, 9.3 GB/s write speed, Single-Cell Self-Boost program scheme for high performance ferroelectric NAND flash SSD

A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage V_PGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at V_CC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at V_CC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application.