Improving bulk FinFET DC performance in comparison to SOI FinFET

The implementation of FinFET structure in bulk silicon wafers is very attractive due to low-cost technology and compatibility with standard bulk CMOS in comparison with silicon-on-insulator (SOI) FinFET. SOI and bulk FinFET were analyzed by a three-dimensional numerical device simulator. We have shown that bulk FinFET with source/drain-to-body (S/D) junctions shallower than gate-bottom has equal or better subthreshold performance than SOI FinFET. By reducing S/D junction depth, fin width scaling for suppression of short-channel-effects (SCEs) can be relaxed. On-state performance has also been examined and drain current difference between the SOI and bulk FinFET at higher body doping levels has been explained by investigating enhanced conduction in silicon-oxide interface corners. By keeping the body doping low and junctions shallower than the gate-bottom, bulk FinFET characteristics can be improved with no increase in process complexity and cost.     

Physics-based compact model for ultra-scaled FinFETs

A physical and explicit compact model for lightly doped FinFETs is presented. This design-oriented model is valid for a large range of silicon Fin widths and lengths, using only a very few number of model parameters. The quantum mechanical effects (QMEs), which are very significant for thin Fins below 15 nm, are included in the model as a correction to the surface potential. A physics-based approach is also followed to model short-channel effects (roll-off), drain-induced barrier lowering (DIBL), subthreshold slope degradation, drain saturation voltage, velocity saturation, channel length modulation and carrier mobility degradation. The quasi-static model is then developed and accurately accounts for small-geometry effects as well. This compact model is accurate in all regions of operation, from weak to strong inversion and from linear to saturation regions. It has been implemented in the high-level language Verilog-A and exhibits an excellent numerical efficiency. Finally, comparisons of the model with 3D numerical simulations show a very good agreement making this model well-suited for advanced circuit simulations.     

DC self-heating effects modelling in SOI and bulk FinFETs

DC thermal effects modelling for nanometric silicon-on-insulator (SOI) and bulk fin-shaped field-effect transistors (FinFETs) is presented. Among other features, the model incorporates self-heating effects (SHEs), velocity saturation and short-channel effects. SHEs are analysed in depth by means of thermal resistances, which are determined through an equivalent thermal circuit, accounting for the degraded thermal conductivity of the ultrathin films within the device. Once the thermal resistance for single-fin devices has been validated for different gate lengths and biases, comparing the modelled output characteristics and device temperatures with numerical simulations obtained using Sentaurus Device, the thermal model is extended by circuital analysis to multi-fin devices with multiple fingers.     

Suppression of corner effects in triple-gate MOSFETs

The abnormal corner effects on channel current in nanoscale triple-gate MOSFETs are examined via two-dimensional (2-D) numerical simulations and quasi-2-D analysis. Heavy body doping [for threshold voltage (V/sub t/) control with a polysilicon gate] is found to underlie the effects, which can hence be suppressed, irrespective of the shape of the corners, by leaving the body undoped, and relying on a metal gate with proper work function for V/sub t/ control. Short-channel effects tend to ameliorate the corner effects, but the need for ad hoc suppression remains.     

Quantum-mechanical effects and gate leakage current of nanoscale n-type FinFETs: A 2d simulation study

This paper simulates a kind of new sub-50 nm n-type double gate MOS nanotransistors by solving coupled Poisson-Schrödinger equations in a self-consistent manner with a finite element method, and presents a systematic simulation-based study on quantum-mechanical effects, gate leakage current of FinFETs. The simulation results indicate that the deviation from the classical model becomes more important as the gate oxide, gate length and Fin channel width becomes thinner and the Fin channel doping increases. Gate tunneling current density reduces with the body thickness decreasing. Excessive scaling increases the gate current below Fin thickness of 5 nm. The gate current can be dramatically reduced beyond 10¹⁷ cm⁻³ with the Fin body doping increasing. In order to understand the influence of electron confinement, quantum mechanical simulation results are also compared with the results from the classical approach. Our simulation results indicate that quantum mechanical simulation is essential for the realistic optimization of the FinFET structure.     

FinFET器件总剂量效应研究进展

全面综述鳍式场效应晶体管(FinFET)的总剂量效应,包括辐照期间外加偏置、器件的工艺参数、提高器件驱动能力的特殊工艺、源/漏掺杂类型以及不同栅介质材料和新沟道材料与FinFET总剂量效应的关系。对于小尺寸器件,绝缘体上硅(SOI)FinFET比体硅FinFET具有更强的抗总剂量能力,更适合于高性能抗辐照的集成电路设计。此外,一些新的栅介质材料和一些新的沟道材料的引入,如HfO₂和Ge,可以进一步提高FinFET器件的抗总剂量能力。     

Experimental study and analysis of corner compensation structures for CMOS compatible bulk micromachining using 25 wt% TMAH

In the present work, most common compensation structures (〈1 1 0〉 squares and 〈1 0 0〉 bars) have been used for convex corner compensation with 25 wt% TMAH-water solution at 90±1 °C temperature. Etch flow morphology and self-align properties of the compensating structures have been investigated. For 25 wt% TMAH water solution {3 1 1} plane is found to be responsible for corner undercutting, which is the fast etch plane. Etch-front-attack angle is measured to be 24°. Generalized empirical formulas are also discussed for these compensation structures for TMAH-water solution. 〈1 1 0〉 square structure protects mesa and convex corner and is the most space efficient compared to other compensation structures, but unable to produce perfect convex corner as 〈1 0 0〉 bar type structures. Both the 〈1 0 0〉 bar structures provide perfect convex corners, but 〈1 0 0〉 wide bar structure is more space efficient than the 〈1 0 0〉 thin bar structure. Implications of these compensation structures with realization of accelerometer structure have also been discussed. A modified quad beam accelerometer structure has been realized with these compensation structures using 25 wt% TMAH.     

Evaluation of process parameter space of bulk FinFETs using 3D TCAD

Using full 3D TCAD, an evaluation of process parameter space of bulk FinFET is presented from the point of view of DRAM, SRAM and I/O applications. Process and device simulations are performed with varying uniform fin doping, anti-punch implant dose and energy, fin width, fin height and gate oxide thickness. Bulk FinFET architecture with anti-punch implant is introduced beneath the channel region to reduce the punch-through and junction leakage. For 30 nm bulk FinFET, anti-punch implant with low energy of 15 to 25 keV and dose of 5.0 × 10¹³ to 1.0 × 10¹⁴ cm⁻² is beneficial to effectively suppress the punch-through leakage with reduced GIDL and short channel effects. Our simulations show that bulk FinFETs are approximately independent of back bias effect. With identical fin geometry, bulk FinFETs with anti-punch implant show same I_ON-I_OFF behavior and approximately equal short channel effects like SOI FinFETs.     

Analysis and prevention of convex corner undercutting in bulk micromachined silicon microstructures

Convex corner undercutting in <100> silicon is an undesired phenomena during bulk micromachining of crystalline silicon substrate using anisotropic wet chemical etching process. The present investigation concentrates on the studies of convex corner undercutting at the free end of silicon cantilever beams released by anisotropic etching process. It also reports a simple, space efficient compensation design for complete prevention of corner deformation. Various compensation patterns such as square, rectangle and superposition of square and rectangular blocks of various dimensions have been employed at the free end corners of cantilever beam to protect corner deformation due to undercutting. The experiment was carried out in 44 wt.% KOH at 70 °C using <100> oriented silicon wafer. Both n-type and p-type silicon wafers were used to study the variations in the nature of corner deformation. A simple empirical relation has been obtained from the experimental data to calculate the lateral dimensions of the compensation layout from the total etch depth required to release the structure.     

新型纳米尺寸MOSFET器件的模拟和设计

在半导体器件的研制过程中,用计算机数值模拟取代测量方法来优化设计器件的性能参数,则器件的调试周期将显著缩短,费用将大幅度降低。本文简述了新型纳米尺寸MOSFET器件模拟的主要物理模型和数值方法,阐述MOSFET相关器件模拟的国内外研究动态,判断其发展趋势和研究方向。     

用三维蒙特卡罗模拟栅-源/漏不对准对体硅FinFET器件性能的影响

We investigate the influence of gate-source/drain(G-S/D) misalignment on the performance of bulk fin field effect transistors(FinFETs) through the three-dimensional(3D) full band Monte Carlo simulator.Several scattering mechanisms,such as acoustic and optical phonon scattering,ionized impurity scattering,impact ionization scattering and surface roughness scattering are considered in our simulator.The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work.Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length.The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.     

非平面三栅场效应晶体管总剂量辐射研究

This paper investigates the total ionizing dose response of different non-planar triple-gate transistor structures with different fin widths. By exposing the pseudo-MOS transistor to different amounts of radiation, different interface trap densities and trapped-oxide charges can be obtained. Using these parameters together with Altal 3D simulation software, the total dose radiation response of various non-planar triple-gate devices can be simulated. The behaviors of three kinds of non-planar devices are compared.     

槽栅MOS器件的研究与进展

随产丰ＶＬＳＩＫ器件尺寸越来越小,槽栅ＭＯＳ器件被作为在深亚微９米及亚０．１范围极具应用前景的理想同出来。文中介绍了槽顺件提出的背景,论述了槽栅ＭＯＳ器件的结构与特点,并就其发展现状和趋势以及存在的问题进行了概括和总结。     

利用LKMC仿真和NBD测试对FinFET中的应变的仿真和表征

一种新的仿真方法和测试手段被采用来验证了FinFET中传统的应力仿真方法。首先,名为lattice kinetic Monte Carlo的算法第一次被用来仿真了FinFET上SiGe的外延生长过程以及由之产生的应力。外延过程的仿真充分可信,同时与传统的由多面体法生成结果的系统对比证实了两种算法具有相近的结果和相似的分布。接下来,P型FinFET器件结构片在实验室制备出来并在RPCVD机台中对源漏区进行了成功的SiGe外延的实验。对做完SiGe外延结构片进行TEM和纳米束衍射测试来表征Fin中的应变,测试的结果与相同条件下的多面体法仿真结果进行比较,二者相互验证。     

Characterization and 3D TCAD simulation of NOR-type flash non-volatile memories with emphasis on corner effects

The impact of 3D device architecture in aggressively scaled embedded non-volatile memories has been investigated by means of experiments and 3D TCAD simulations. A complete 3D calibration methodology covering DC and transient operating regimes has been introduced and validated against measurements for different technological options. This approach has been employed to determine the key features for device optimization. In particular, shallow trench isolation corners around the active area have been identified as critical regions of the memory cell for program and erase operations, as well as for gate coupling ratio optimization.     

抑制 SOIp- MOSFET中短沟道效应的 GeSi源 /漏结构

提出在 SOI p- MOSFET中采用 Ge Si源 /漏结构 ,以抑制短沟道效应 .研究了在源、漏或源与漏同时采用 Ge Si材料对阈值电压漂移、漏致势垒降低 (DIBL)效应的影响 ,并讨论了 Ge含量及硅膜厚度变化对短沟道效应及相关器件性能的影响 .研究表明 Ge含量应在提高器件驱动电流及改善短沟道效应之间进行折中选择 .对得到的结果文中给出了相应的物理解释 .随着器件尺寸的不断缩小 ,Ge Si源 /漏结构不失为 p沟 MOS器件的一种良好选择     

Compact modeling of quantum effects in symmetric double-gate MOSFETs

Quantum effects have been incorporated in the analytic potential model for double-gate MOSFETs. From extensive solutions to the coupled Schrodinger and Poisson equations, threshold voltage shift and inversion layer capacitance are extracted as closed form functions of silicon thickness and inversion charge density. With these modifications, the compact model is shown to reproduce C-V and I-V curves of double-gate MOSFETs consistent with those obtained from those measured from experimental FinFET hardware.     

Reduction of gate-to-channel tunneling current in FinFET structures

In this work, the gate-to-channel leakage current in FinFET structures is experimentally studied in comparison with quasi-planar very wide-fin structures, and as a function of the fin width. Devices with both doped and undoped channels and different gate stacks are studied. Experimental evidence for the reduction of gate tunneling current density in narrow FinFET structures compared to their counterpart quasi-planar structures is reported for the first time. This gate current reduction is observed for both n-channel and p-channel devices and is found to be stronger for HfO₂ than for SiON. For a given gate dielectric, the above gate current improvement in FinFETs enhances with decreasing the fin width. For SiON with an equivalent oxide thickness of 1.6 nm in undoped n-channel devices, it varies from factor of 2.3–4.3, when the fin width decreases from 75 to 25 nm. The possible reasons for the observed effect are discussed.     

Non-peripheral octahexylphthalocyanine doping effects in bulk heterojunction polymer solar cells

The improvement of long-wavelength sensitivity in bulk heterojunction organic thin-film solar cells based on poly(3-hexylthiophene) (P3HT) by the addition of the soluble phthalocyanine derivative, 1,4,8,11,15,18,22,25-octahexylphthalocyanine (C6PcH₂) is reported. C6PcH₂ possesses near-infrared absorption and can be mixed with a P3HT:1-(3-methoxy-carbonyl)-propyl-1-1-phenyl-(6,6)C61 (PCBM) bulk heterojunction active layer. By doping C6PcH₂, the photosensitivity in the long-wavelength region was improved, and the energy conversion efficiency reached 3.0% at a composition ratio of P3HT:C6PcH₂:PCBM = 10:3:10. We discuss the principle of photoconversion in the bulk heterojunction solar cell based on the P3HT:C6PcH₂:PCBM active layer by taking into consideration the existence of both highly ordered P3HT domains and hexagonal columnar structures of C6PcH₂, and the microphase separation of P3HT and C6PcH₂ in the active layer.     

Gate metallurgy effects in InAs/AlSb HFETs: Preliminary results and demonstration of surface fermi level shifts

The effect of gate metallurgy on depletion-mode InAs/AlSb heterostructure field-effect transistors (HFETs) is studied for the first time by carefully comparing the characteristics of Al- and Ti/Au-gate transistors. HFETs fabricated simultaneously from the same molecular beam epitaxial layers and processed identically, but differing only in the metal used for the gate electrode, feature very different gate and drain I-V characteristics. The metal dependence indicates that the Fermi level is not completely pinned at the surface of InAs/AlSb quantum wells. We also show that the gate metal modifies the charge control properties of InAs/AlSb HFETs: Al-gate HFETs exhibit an enhanced kink effect accompanied by a marked transconductance compression at zero gate bias, whereas the Ti/Au-gate devices exhibit nearly kink-free drain characteristics. The gate metal dependence is shown to be a consequence of the increased channel equilibrium electron concentration accompanying the Al-metallization.