Investigation of voltage-swing effect and trap generation in high-k gate dielectric of MOS devices by charge-pumping measurement

Charge-pumping (CP) techniques with various rise and fall times and with various voltage swings are used to investigate the energy distribution of interface-trap density and the bulk traps. The charge pumped per cycle (Q_cp) as a function of frequency was applied to detect the spatial profile of border traps near the high-k gate dielectric/Si interface and to observe the phenomena of trap migration in the high-k dielectric bulk during constant voltage stress (CVS) sequence. Combining these two techniques, a novel CP technique, which takes into consideration the carrier tunneling, is developed to measure the energy and depth profiles of the border trap in the high-k bulk of MOS devices.     

Improved electrical characteristics of high-k gated MOS devices by nitrogen incorporation with plasma immersion ion implantation (PIII)

High-k gate dielectric process is the key technology for nano-scale MOS device. A nitridation treatment on silicon surface is promising for characteristic improvement on high-k dielectric. It is found in this work that the electrical characteristics of high-k gated MOS devices can be improved by a nitridation treatment at silicon surface using plasma immersion ion implantation (PIII) at low ion energy and with a short implantation time. A shallow nitrogen profile at Si surface is known to be favorable for further enhancement of device properties.     

Effect of interfacial fluorination on the electrical properties of the inter-poly high-k dielectrics

In this paper, the reliabilities and insulating characteristics of the fluorinated aluminum oxide (Al₂O₃) and hafnium oxide (HfO₂) inter-poly dielectric (IPD) are studied. Interface fluorine passivation has been demonstrated in terminating dangling bonds and oxygen vacancies, reducing interfacial re-oxidation and smoothing interface roughness, and diminishing trap densities. Compared with the IPDs without fluorine incorporation, the results clearly indicate that fluorine incorporation process is effective to improve the insulating characteristics of both the Al₂O₃ and HfO₂ IPDs. Moreover, fluorine incorporation will also improve the dielectric quality of the interfacial layer. Although HfO₂ possesses higher dielectric constant to increase the gate coupling ratio, the results also demonstrate that fluorination of the Al₂O₃ dielectric is more effective to promote the IPD characteristics than fluorination of the HfO₂ dielectric. For future stack-gate flash memory application, the fluorinated Al₂O₃ IPD undoubtedly possesses higher potential to replace current ONO IPD than the fluorinated HfO₂ IPD due to superior insulating properties.     

Effect of thin Si insertion at metal gate/high-k interface on electrical characteristics of MOS device with La2O3

The effect of a thin Si layer insertion at W/La₂O₃ interface on the electrical characteristics of MOS capacitors and transistors is investigated. A suppression in the EOT increase can be obtained with Si insertion, indicating the inhibition of diffusion of oxygen atoms into La₂O₃ layer by forming an amorphous La-silicate layer at the W/La₂O₃ interface. In addition, positive shifts in V_fb and V_th caused by Si insertion implies the formation of amorphous La-silicate layer at the top of La₂O₃ dielectrics reduces the positive fixed charges induced by the metal electrode. Consequently, a large improvement in mobility has been confirmed for both at peak value and at high E_eff of 1 MV/cm with Si inserted nFETs. Although a degradation trend on EOT scaling has been observed, the insertion of thin Si layer is effective in pushing the scaling limit.     

An evaluation of contamination from plasma immersion ion implantation on silicon device characteristics

Silicon devices including diodes, metal oxide semiconductor capacitors, and p-channel metal oxide semiconductor transistors were fabricated by plasma immersion ion implantation (PHI) doping technique using a microwave multipolar bucket plasma system. B₂H₆ diluted in helium (1%) was used as the gas source. The contamination by helium, hydrogen, iron, sodium, and aluminum impurities was evaluated by secondary ion mass spectrometry measurements. During PHI processing in an aluminum chamber with a stainless steel wafer holder, no aluminum and a dose of 4.1 x 10¹²/cm² of Fe were detected. Most of Fe ions were shielded by a thin layer of SiO₂ during the device fabrications. Good quality devices have been demonstrated including low reverse current of 15 nA/cm² (V_R = -5 V) in diodes and reasonable lifetimes of the minority carriers such as t_g = 55.0 μsec and = τ_r 54.2 μsec.     

CHC degradation of strained devices based on SiON and high-k gate dielectric materials

A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied.     

Gentle FUSI NiSi metal gate process for high-k dielectric screening

In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).     

Performance of current mirror with high-k gate dielectrics

This work compares the performance of the basic current mirror topology by using two different materials for gate dielectrics, the conventional SiON and an Hf-based high-k dielectrics. The impact of gate leakage and of channel length modulation on the basic current mirror operation is described. It is shown that in the case of SiON gate dielectrics with an equivalent oxide thickness (EOT) of 1.4 nm, it is not possible to find a value for the channel length which allows a good trade-off to be obtained while minimizing the gate leakage and reducing the channel length modulation. On the other hand, the study demonstrates that in the case of HfSiON gate dielectrics with similar EOT, appropriate L values can be found obtaining very high output impedance current sources with reduced power consumption owing to low leakage and most of all with better parameter predictability.     

High-quality high-k HfON formed with plasma jet assisted PVD process and application as tunnel dielectric for flash memories

We demonstrate low-trap-density HfON film made by the molecular-atomic deposition (MAD) technique, which is an Ar/N₂ plasma jet assisted physical vapor deposition process. This high-k HfON can be deposited on top of the nearly trap-free MAD-Si₃N₄ to form a single-side crested tunnel barrier. The Al/(HfON-Si₃N₄)/Si capacitor structure with HfON/Si₃N₄ stack as the tunnel barrier demonstrates steeper I-V slope than that of a single layer SiO₂ with the same EOT, and is readily applicable to improve the programming speed and data retention of flash memories.     

Rare earth-based high-k materials for non-volatile memory applications

A study of a La-based high-k oxide to be employed as active dielectric in future scaled memory devices is presented. The focus will be held on La_xZr_1−xO_2−δ (x = 0.25) compound. In order to allow the integration of this material, its chemical interaction with an Al₂O₃ cap layer has been studied. Moreover, the electrical characteristics of these materials have been evaluated integrating them in capacitor structures. The rare earth-based ternary oxide is demonstrated to be a promising candidate for future non-volatile memory devices based on charge trapping structure.     

A nanoanalytical investigation of elemental distributions in high-k dielectric gate stacks on silicon

Two high-k gate stacks with the structure Si/SiO₂/HfO₂/TiN/poly-Si are characterised using nanoanalytical electron microscopy. The effect of two key changes to the processing steps during the fabrication of the stacks is investigated. Electron energy-loss spectroscopy is used to show that the TiN layer has a very similar composition whether it is deposited by PVD or ALD. Spectrum imaging in the electron microscope was used to profile the distribution of elements across the layers in the stack. It was found that when the anneal after HfO₂ deposition is carried out in a NH₃ atmosphere instead of an O₂ atmosphere, there is diffusion of N into the SiO₂ and HfO₂ layers. There is also significant intermixing of the layers at the interfaces for both wafers.     

Titanium-aluminum oxynitride (TAON) as high-k gate dielectric for sub-32 nm CMOS technology

High-k insulators for the next generation (sub-32 nm CMOS (complementary metal-oxide-semiconductor) technology), such as titanium-aluminum oxynitride (TAON) and titanium-aluminum oxide (TAO), have been obtained by Ti/Al e-beam evaporation, with additional electron cyclotron resonance (ECR) plasma oxynitridation and oxidation on Si substrates, respectively. Physical thickness values between 5.7 and 6.3 nm were determined by ellipsometry. These films were used as gate insulators in MOS capacitors fabricated with Al electrodes, and they were used to obtain capacitance-voltage (C-V) measurements. A relative dielectric constant of 3.9 was adopted to extract the equivalent oxide thickness (EOT) of films from C-V curves under strong accumulation condition, resulting in values between 1.5 and 1.1 nm, and effective charge densities of about 10¹¹ cm⁻². Because of these results, nMOSFETs with Al gate electrode and TAON gate dielectric were fabricated and characterized by current-voltage (I-V) curves. From these nMOSFETs electrical characteristics, a sub-threshold slope of 80 mV/dec and an EOT of 0.87 nm were obtained. These results indicate that the obtained TAON film is a suitable gate insulator for the next generation (MOS) devices.     

Pore sealing of mesoporous silica low-k dielectrics by oxygen and argon plasma treatments

In this study, we have prepared surfactant templated mesoporous silica thin films as the ultralow-k dielectrics and a TaN_X thin film deposited by plasma enhanced atomic layer chemical vapor deposition (PE-ALCVD) using TaCl₅ as the gas precursor was used as the diffusion barrier. Without any surface modification for the dielectric layer, Ta atoms could easily diffuse into the mesoporous layer seriously degrading dielectric properties. O₂ and Ar plasmas have been used to modify the surface of the mesoporous dielectric in a high density plasma chemical vapor deposition (HDP-CVD) system, and both of the treatments produced a densified oxide layer a few nanometer thick. According to transmission electron microscopy and Auger electron spectroscopy, the pore sealing treatment could effectively prevent Ta atoms from diffusing into the mesoporous dielectric during the PE-ALCVD process.     

Resistive switching effects of HfO2 high-k dielectric

Resistive switching behavior of HfO₂ high-k dielectric has been studied as a promising candidate for emerging non-volatile memory technology. The low resistance ON state and high resistance OFF state can be reversibly altered under a low SET/RESET voltage of ±3 V. The memory device shows stable retention behavior with the resistance ratio between both states maintained greater than 103. The bipolar nature of the voltage-induced hysteretic switching properties suggests changes in film conductivity related to the formation and removal of electronically conducting paths due to the presence of oxygen vacancies induced by the applied electric field. The effect of annealing on the switching behavior was related to changes in compositional and structural properties of the film. A transition from bipolar to unipolar switching behavior was observed upon O₂ annealing which could be related to different natures of defect introduced in the film which changes the film switching parameters. The HfO₂ resistive switching device offers a promising potential for high density and low power memory application with the ease of processing integration.     

Reliability and gate conduction variability of HfO2-based MOS devices: A combined nanoscale and device level study

The electrical properties and reliability of MOS devices based on high-k dielectrics can be affected when the gate stack is subjected to an annealing process, which can lead to the polycrystallization of the high-k layer. In this work, a Conductive Atomic Force Microscope (C-AFM) has been used to study the nanoscale electrical conduction and reliability of amorphous and polycrystalline HfO₂ based gate stacks. The link between the nanoscale properties and the reliability and gate conduction variability of fully processed MOS devices has also been investigated.     

Process damage-free damascene metal gate technology for gentle integration of epitaxially grown high-k

This paper presents the first successful attempt to integrate crystalline high-k gate dielectrics into a virtually damage-free damascene metal gate process. Process details as well as initial electrical characterization results on fully functional gate Gd₂O₃ dielectric MOSFETs with equivalent oxide thickness (EOT) down to 1.9 nm are discussed and compared with devices with rare-earth gate dielectrics fabricated previously in a conventional CMOS process.     

MOCVD fluorine free WSix metal gate electrode on high-k dielectric for NMOS technology

We report material and electrical properties of tungsten silicide metal gate deposited on 12 in. wafers by chemical vapor deposition (CVD) using a fluorine free organo-metallic (MO) precursor. We show that this MOCVD WSi_x thin film deposited on a high-k dielectric (HfSiO:N) shows a N+ like behavior (i.e. metal workfunction progressing toward silicon conduction band). We obtained a high-k/WSi_x/polysilicon “gate first” stack (i.e. high thermal budget) providing stable equivalent oxide thickness (EOT) of ∼1.2 nm, and a reduction of two decades in leakage current as compared to SiO₂/polysilicon standard stack. Additionally, we obtained a metal gate with an equivalent workfunction (EWF) value of ∼4.4 eV which matches with the +0.2 eV above Si midgap criterion for NMOS in ultra-thin body devices.     

Thermal stability of tantalum nitride diffusion barriers for Cu metallization formed using plasma immersion ion implantation

Plasma immersion ion implantation (PIII) technique was employed to form Tantalum nitride diffusion barrier films for copper metallization on silicon. Tantalum coated silicon wafers were implanted with nitrogen at two different doses. A copper layer was deposited on the samples to produce Cu/Ta(N)/Si structure. Samples were heated at various temperatures in nitrogen ambient. Effect of nitrogen dose on the properties of the barrier metal was investigated by sheet resistance, X-ray diffraction and scanning electron microscopy measurements. High dose nitrogen implanted tantalum layer was found to inhibit the diffusion of copper up to 700 °C.     

The correlation of the electrical properties with electron irradiation and constant voltage stress for MIS devices based on high-k double layer (HfTiSiO:N and HfTiO:N) dielectrics

This paper describes the influence of e-beam irradiation and constant voltage stress on the electrical characteristics of metal-insulator-semiconductor structures, with double layer high-k dielectric stacks containing HfTiSiO:N and HfTiO:N ultra-thin (1 and 2 nm) films. The changes in the electrical properties were caused by charge trapping phenomena which is similar for e-beam irradiation and voltage stress cases. The current flow mechanism was analyzed on the basis of pre-breakdown, soft-breakdown and post-breakdown current-voltage (J-V) experiments. Based on α-V analysis (α=d[ln(J)]/d[ln(V)]) of the J-V characteristics, a non-ideal Schottky diode-like current mechanism with different parameters in various ranges of J-V characteristics is established, which limits the current flow in these structures independent of irradiation dose or magnitude of applied voltage during stress.     

Effects of oxygen partial pressure on structural and electrical characteristics of HfAlO high-k gate dielectric grown on strained SiGe by pulsed-laser deposition

Dependence of oxygen partial pressures on structural and electrical characteristics of HfAlO (Hf:Al=1:1) high-k gate dielectric ultra-thin films grown on the compressively strained Si₈₃Ge₁₇ by pulsed-laser deposition were investigated. The microstructure and the interfacial structure of the HfAlO thin films grown under different oxygen partial pressures were studied by transmission electron microscopy, and the their electrical properties were characterized by capacitance–voltage (C−V) and conductance–voltage measurements. Dependence of interfacial layer thickness and C–V characteristics of the HfAlO films on the growth of oxygen pressure was revealed. With an optimized oxygen partial pressure, an HfAlO film with an effective dielectric constant of 16 and a low interface state density of 2.1×10¹⁰ cm⁻² eV⁻¹ was obtained.