Intra-level voltage ramping-up to dielectric breakdown failure on Cu/porous low-k interconnections in 45 nm ULSI generation

The degradation of reliability for intra-level voltage-breakdown in the 45 nm generation node has become an increasingly important issue with the introduction of porous low-k dielectrics. The dominant failure mechanism for lower voltage ramping-up to dielectric breakdown and higher leakage current was that more electrons easily transported through the percolation path in intra-level porous low-k interconnections damaged from HF corrosion. An optimal ultraviolet curing process and a less NH₃ plasma pre-treatment on porous low-k dielectrics before the SiCN capping layer are developed to improve performance in both of these cases. The stiff configuration of the reconstruction of Si-O network structures and less HF corrosion is expected to have high tolerance to electrical failure. As a result, the proposed model of this failure facilitates the understanding of the reliability issue for Cu/porous low-k interconnections in back-end of line (BEOL) beyond 45 nm nodes.     

Study of metal barrier deposition-induced damage to porous low-k materials

A unique test structure based on a metal-insulator-semiconductor planar capacitor (Pcap) design was used to investigate several aspects of metal barrier-induced low-k damage. A special term called Effective Damage Thickness was introduced to describe the degree of damage. Ta(N) barrier was deposited on various dielectric films with porosity up to 32%. It has been found that the Effective Damage Thickness increases as the porosity increases. The damage is influenced more by the porosity of low-k films than the film density. Furthermore, the damage was modulated by Ta(N) deposition conditions. More damage was observed when higher target and/or substrate bias power was used, suggesting that the ion energy of the barrier material plays an important role in the low-k damage mechanism. A same degree of damage was observed for Ta barrier as for Ta(N), suggesting that Ta(N) deposition-induced low-k damage was primarily caused by Ta ions not nitrogen. Impact of Ru(Ta) and Cu(Mn) self forming barrier on low-k damage was also investigated. Among all the barriers studied in this work, the Ta-based barriers caused the most damage while the Cu(Mn) self forming barrier had the least damage to the low-k. The atomic masses for Ta, Ru, and Cu are 181, 101, and 64, respectively, corresponding with the observed degree of damage in the low-k material.     

Effects of fluoride residue on Cu agglomeration in Cu/low-k interconnects

We have investigated the effects of fluoride residue on the thermal stability of a Cu/barrier metal (BM)/porous low-k film (k < 2.3) structure. We confirmed that the Cu agglomerated more on a BM/inter layer dielectric (ILD) with a fluoride residue. To consider the effect of fluoride residue on Cu agglomeration, the structural state at the Cu/BM interface was evaluated with a cross-section transmission electron microscope (TEM) and atomic force microscope (AFM). And the chemical bonding state at the Cu/BM interface was evaluated with the interface peeling-off method and X-ray photoelectron spectroscopy (XPS). Moreover, we confirmed the oxidation of Cu with fluoride in accelerated conditions to clarify the effect of fluoride on Cu. Our experiments suggested that the fluoride residue led to the formation of a metal fluoride, and this accelerated the Cu agglomeration accompanying an increase in Cu oxidation.     

Mechanical properties of a plasma-modified porous low-k material

For 45 nm and beyond microelectronics technology nodes, the integration of porous low dielectric constant (low-k) materials is now required to reach integrated dielectric constant values lower than 2.7. However, porous low-k materials have lower mechanical strength in comparison with traditional dense materials and are also affected by chemical diffusion through the interconnected porosity during the various integration processes. Different types of plasma post-treatments which lead to surface modification of the porous low-k material with possible formation of a top surface layer, change of surface structure and “pore sealing” effect were applied. Highly sensitive instruments for mechanical investigation of thin layers, such as the Ultra Nano Hardness Tester (UNHT) and Nano Scratch Tester (NST) were applied for characterization of the effect of the plasma post-treatments on the mechanical behavior of a porous low-k material. Preliminary results are presented and discussed in this paper.     

Interconnects for nanoscale MOSFET technology: a review

In this paper,a review of Cu/low-k,carbon nanotube(CNT),graphene nanoribbon(GNR)and optical based interconnect technologies has been done,Interconnect models,challenges and solutions have also been discussed.Of all the four technologies,CNT interconnects satisfy most of the challenges and they are most suited for nanometer scale technologies,despite some minor drawbacks.It is concluded that beyond 32nm technology,a paradigm shift in the interconnect material is required as Cu/low-k interconnects are approaching fundamental limits.     

Optical, electrical and structural properties of spin-on MSQ low-k dielectrics over a wide temperature range

Looking onto application of low-k and ultra low-k materials within FEOL, high temperature load is one of the major challenges. But also temperature ranges below standard curing conditions are of special interest, e.g. for integration of transparent low-k materials into optical devices due to their small refractive index. In this work the development of the optical, electrical and structural properties of two spin-on MSQ low-k dielectrics over a low-temperature range has been investigated. Incorporation of porosity due to porogen removal for LK2000 causes a different behaviour of the electrical and optical parameters compared to ACCUGLASS™ within the low-temperature range. Both materials show unstable properties which normalize by getting closer to the standard curing conditions. Hydrophobizity of the surfaces is developing at curing temperatures of 400 °C and higher, what agrees to the lowering of the leakage current density. Optical, electrical and structural parameters fluctuate very sensitive on changing the curing temperature, so usage of those materials within a low-temperature range requires a very stable curing process to achieve reproducible material properties.     

Effect of porogen residue on electrical characteristics of ultra low-k materials

Porogen residue (sp² hybridized carbon) formed during UV curing of low-k materials increases leakage current and decreases breakdown voltage of low-k materials. The amount of porogen residue increases with increasing porosity of PECVD low-k films because of larger amount of co-deposited porogen. Electrical characteristics of PECVD ultra low-k films are significantly worse in comparison with CVD and SOG low-k film prepared without porogen. SOG low-k films prepared by self-assembling of nanocrystalline silica demonstrate very low leakage current. Removal of porogen residue significantly improves the electrical characteristics. Therefore, preparation of porogen residue free low-k films is an important challenge of future scaling of low-k materials.     

Theoretical study of mechanical properties of multi-layer ULSI interconnect dielectrics by surface acoustic wave method

The surface acoustic waves (SAWs) technique is becoming an attractive tool for accurately and nondestructively characterizing the mechanical property of the fragile low dielectric constant (low-k) thin film used in the advanced ULSI multi-layer interconnects. The dispersion features of SAWs propagating on the layered structure of low-k/SiO₂/Si substrate and low-k/Cu/Si substrate are investigated in detail. The influence of the film thickness on the dispersion curvature is provided as an instruction for an accurate and facile fitting process. Numerical results indicate that the mechanical property of low-k films is expected to determine effectively when the broadband frequency is up to 300 MHz.     

Band diagram for low-k/Cu interconnects: The starting point for understanding back-end-of-line (BEOL) electrical reliability

The starting point for describing the electrostatic operation of any semiconductor device begins with a band diagram illustrating changes in the semiconductor Fermi level and the alignment of the valence and conduction bands with other interfacing semiconductors, insulating dielectrics and metal contacts. Such diagrams are essential for understanding the behavior and reliability of any semiconductor device. For metal interconnects, the band alignment between the metal conductor and the insulating intermetal and interlayer dielectric (ILD) is equally important. However, relatively few investigations have been made. In this regard, we have investigated the band alignment at the most common interfaces present in traditional single and dual damascene low-k/Cu interconnect structures. We specifically report combined X-ray photoelectron spectroscopy and reflection electron energy loss spectroscopy (REELS) measurements of the Schottky barrier present at the ILD and dielectric Cu capping layer (CCL) interfaces with the Ta(N) via/trench Cu diffusion barrier. We also report similar measurements of the valence and conduction band offsets present at the interface between a-SiN(C):H dielectric CCLs and low-k a-SiOC:H ILDs (porous and non-porous). The combined results point to metal interfaces with the CCL having the lowest interfacial barrier for electron transport. As trap and defect states in low-k dielectrics are also important to understanding low-k/Cu interconnect reliability, we additionally present combined electron paramagnetic resonance (EPR) and electrically detected magnetic resonance (EDMR) measurements to determine the chemical identity and energy level of some electrically active trap/defect states in low-k dielectrics. Combined with the photoemission derived band diagrams, the EPR/EDMR measurements point to mid-gap carbon and silicon dangling bond defects in the low-k ILD and CCL, respectively, playing a role in electronic transport in these materials. We show that in many cases the combined band and defect state diagrams can explain and predict some of the observed reliability issues reported for low-k/Cu interconnects.     

Electroless CoWP as a Diffusion Barrier between Electroless Copper and Silicon

In this work, an electroless CoWP film deposited on a silicon substrate as a diffusion barrier for electroless Cu and silicon has been studied. Four different Cu 120 nm/CoWP/Si stacked samples with 30, 60, 75, and 100 nm electroless CoWP films were prepared and annealed in a rapid thermal annealing (RTA) furnace at 300°C to 800°C for 5 min. The failure behavior of the electroless CoWP film in the Cu/CoWP/Si sample and the effect of CoWP film thickness on the diffusion barrier properties have been investigated by transmission electron microscopy (TEM), scanning electron microscopy (SEM), X-ray diffraction (XRD), and sheet resistance measurements. The composition of the electroless CoWP films was 89.4 at.% Co, 2.4 at.% W, and 8.2 at.% P, as determined by energy dispersive X-ray spectrometer (EDS). A 30 nm electroless CoWP film can prevent copper penetration up to 500°C, and a 75 nm electroless CoWP film can survive at least up to 600°C. Therefore, increasing the thickness of electroless CoWP films effectively increases the failure temperature of the Cu/CoWP/Si samples. The observations of SEM and TEM show that interdiffusion of the copper and cobalt causes the failure of the electroless CoWP diffusion barriers in Cu/CoWP/Si during thermal annealing.     

The influence of N containing plasmas on low-k films

The use of low-k materials is essential for improving the quality of integrated circuits. Subsequent process steps may however modify this film to the extent that the final result is unacceptable. Organosilicate-based low-k films, with a nominal k-value of 2.3, were exposed to different post-CMP cleaning plasmas used for copper reduction. The resulting plasma damage was investigated and is reported in this paper. All the studied plasmas increased the density of the low-k film. TOFSIMS and FTIR analyses showed that they all removed CH₃ groups from the bulk, leading to water incorporation. The carbon depletion was more pronounced and deeper (100 nm) from a NH₃ plasma than from any other investigated plasma. N₂ + H₂ plasma removed somewhat less carbon from the low-k film (83 nm deep). The N₂ plasma removed carbon down to a depth of 60 nm into the film, while a pure H₂ plasma removed the least carbon of all the investigated plasmas, to a depth of only 35 nm. The combination of TOFSIMS and XPS indicated the incorporation of a significant amount of N in the films treated with the pure N₂ plasma. C-V measurements showed an increase of the dielectric constant, again mostly for the NH₃ plasmas. There was an intermediate and approximately equal increase of the dielectric constant for all N₂ containing plasmas, and the least increase was for the H₂ plasma. This increase of the dielectric constant was caused by the increase of density of the film, incorporation of water, and in the case of the N₂ plasma also the incorporation of N. This shows that the presence of N₂ in plasma may significantly damage low-k materials, and it should not therefore be treated as a mere carrier gas.     

Etching characteristics of photoresist and low-k dielectrics by Ar/O2 ferrite-core inductively coupled plasmas

We have investigated the characteristics of Ar/O₂ plasmas in terms of the photoresist (PR) and low-k material etching using a ferrite-core inductively coupled plasma (ICP) etcher. We found that the O₂/(O₂+ Ar) gas flow ratio significantly affected the PR etching rate and the PR to low-k material etch selectivity. Fourier transform infrared spectroscopy (FTIR) and HF dipping test indicated that the etching damage to the low-k material decreased with decreasing O₂/(O₂ + Ar) gas flow ratio.     

Electron fluence driven,Cu catalyzed,interface breakdown mechanism for BEOL low-k time dependent dielectric breakdown

During technology development, the study of low-k time dependent dielectric breakdown (TDDB) is important for assuring robust chip reliability. It has been proposed that the fundamentals of low-k TDDB are closely correlated with the leakage conduction mechanism of low-k dielectrics. In addition, low-k breakdown could also be catalyzed by Cu migration occurring mostly at the interface between capping layer and low-k dielectrics. In this paper, we first discuss several important experimental results including leakage modulation by changing the capping layer without changing the electric field, TDDB modulation by Cu-free and liner-free interconnect builds, 3D on-flight stress-induced leakage current (SILC) measurement, and triangular voltage sweep (TVS) versus TDDB to confirm the proposed electron fluence driven, Cu catalyzed interface low-k breakdown model. Then we review several other low-k TDDB models that consider only intrinsic low-k breakdown, especially the impact damage model. Experimental attempts on validation of various dielectric reliability models are discussed. Finally, we propose that low-k breakdown seems to be controlled by a complicated competing breakdown process from both intrinsic electron fluence and extrinsic Cu migration during bias and temperature stress. It is hypothesized that the amount of Cu migration during TDDB stress strongly depends on process integration. The different roles of Cu in low-k breakdown could take different dominating effects at different voltages and temperatures. A great care must be taken in evaluating low-k dielectric TDDB as its ultimate breakdown kinetics could be strongly dependent on interconnect space, process, material, stress field, and stress temperature.     

Surface properties restoration and passivation of high porosity ultra low-k dielectric (k ∼ 2.3) after direct-CMP

Surface hydrophilisation and effective k-value degradation have been reported in literature after direct-CMP of high porosity SiOC films (without a protective capping layer). In the sequel, attempts to restore ultra low-k (ULK) material initial properties after a standard CMP and post-CMP cleaning process are reported. Annealing treatment has shown to be valuable to remove residual organics and water absorbed at the ultra low-k material surface after direct-CMP. However, as the hydrophilicity of the polished surface remains unchanged, it does not prevent moisture uptake, leading to an increase in k-value with time. Therefore, in order to restore hydrophobic properties and to stabilize the surface in time, three silylating agents - containing chlorosilane reactive groups (-SiMe_nCl_3−n) as well as hydrophobic methyl functions (-CH₃) in their structure - have been employed in liquid, gas or dense CO₂ phases on the CMP-induced damaged ULK layers. While each of these organic treatments is efficient to restore hydrophobicity on post-CMP ULK surfaces, only one of them proved to be able to keep the k-value low (comparable to the ULK pristine k-value) and stable in time, without inducing significant change in porosity of the ULK material.     

Hybrid punch through approach to address electroless related integration issues of hybrid CoWP/SiCN barriers

Integration of CoWP self-aligned barriers in hybrid stack with SiCN liner in a standard 65 nm technology node integration scheme faces several issues. For example, bowing of upper metal level occurs due to the interaction between CoWP and etch plasma during SiCN opening step leading to lower line resistance compared to SiCN reference. Furthermore, wet cleaning after patterning step must be carefully processed in order to remove residues while keeping CoWP integrity. Electrical and reliability performance show that a clean recipe can be efficient to remove residues leading to low via resistance but in the same time, no electromigration improvement compared to SiCN reference is observed due to CoWP degradation and vice versa. To overcome integration issues, a new integration scheme called hybrid punch through (HPT) approach is proposed. In this approach, the patterning step is modified by SiCN open removal and it is followed by an adapted punch through process during metallization to open the via. HPT approach allows avoiding contact between CoWP and etch plasma or cleaning chemistry and leads to better electrical performance in terms of via and line resistances compared to standard scheme without degrading CoWP.     

Capacitance measurements and k-value extractions of low-k films

We review test vehicles and methods that are commonly used for capacitance measurements of low-k films and the general procedure for k-value extractions. We demonstrate that a considerable loss of accuracy may occur if metal-insulator-semiconductor (MIS) planar capacitors are used in high frequency (HF) capacitance-voltage (CV) measurements leading to significant underestimation of the k-value. We show that the lack of accuracy is due to parasitic impedance at the backside connection with the Si substrate and we provide a model. The effect of the parasitic impedance can be minimized by reducing the area of the gate electrode. Alternatively, samples can be provided with an ohmic back contact by means of one of the practical fabrication methods that are described. Quasi-static (Q-S) CV measurements did not exhibit any variation related to backside connection. However, we show that Q-S CV measurements loose accuracy for plasma-damaged low-k films because of increased dielectric leakage. Finally, issues related to capacitance measurements in dry atmosphere are addressed. We show that long (∼hours) transients can take place for plasma-damaged low-k films because of the slow release of water from the material underneath the metal gate, which acts as a cap. As a consequence, extracted k-value can significantly depend on sample resident time in the measurement chamber and on gate dimensions.     

Cu/low-k dielectric TDDB reliability issues for advanced CMOS technologies

With the wide application of low-k and ultra-low-k dielectric materials at the 90 nm technology node and beyond, the long-term reliability of such materials is rapidly becoming a critical challenge for technology qualification. Low-k time-dependent dielectric breakdown (TDDB) is usually considered as one of the most important reliability issues during Cu/low-k technology development because low-k materials generally have weaker intrinsic breakdown strength than traditional SiO₂ dielectrics. This problem is further exacerbated by the aggressive shrinking of the interconnect pitch size due to continuous technology scaling. In this paper, three critical issues of low-k TDDB characteristics during low-k development and qualification will be reviewed. In the first part, a low-k TDDB field acceleration model and its determination will be discussed. In the second part, low-k dielectric time-to-breakdown (t_BD) statistical distribution and TDDB area scaling law for reliability projection will be examined. In the last part, as low-k TDDB has been found to be sensitive to all aspects of integration, the effects of process variations on low-k TDDB degradation will be demonstrated. Some key aspects which need to be carefully addressed to control overall low-k TDDB performance from process and integration side will be discussed.     

Study of metal adhesion on porous low-k dielectric using telephone cord buckling

The interfacial adhesion energy between metal and porous low-k dielectrics is an important parameter for the reliability study of back-end of line integration. In this work, we have observed the spontaneous film delamination with telephone cord morphology after 130 nm thick Ta was sputtered onto methyl silsesquioxane (MSQ) low-k dielectric. The highly compressive stress inside the Ta film is the driving force for the spontaneous buckling. The adhesion failure was identified to be at Ta/MSQ interface by using focused ion beam and scanning electron microscopy. Pinned circular blister model was applied to fit the buckling morphology. The interfacial adhesion energy was extracted to be 7.90 J/m² at 87° phase angle. The Cu/MSQ interface was evaluated in a similar fashion by using a stressed overlayer Ta/Cu. The fracture energy was calculated to be 3.34 J/m² with the similar phase angle. The results suggest that an adhesion promoter between Cu and low-k dielectrics is essential for a mechanically stable structure.     

Reliability of copper low-k interconnects

For the implementation of copper and low-k materials into a tight pitch damascene interconnect architecture it is important to understand and correctly describe the underlying degradation mechanisms during reliability testing. Based on the understanding solutions can be proposed for avoiding fast degradation. While the physical understanding of electromigration mechanisms is less of a debate, technological challenges towards the fabrication of metal wires/vias able to carry the ever increasing current densities are enormous. Recently a number of novel metallization schemes including ruthenium and its alloys or self-forming barriers were proposed. As a consequence, some of the thermodynamic and kinetic behavior of the system can be modified when compared to the conventional Ta-based metallization. Another important component of the system is the insulating low-k dielectric. When scaling the critical dimensions into 50 nm ½ pitch and beyond, the impact of layout and line edge roughness becomes important. If a double patterning approach is used for printing a tight metal pitch, then misalignment between the different photos will exacerbate the layout induced effects. The choice of dielectric material, test structure design and damascene process steps will contribute on top of these effects. Based on recent understanding we review some aspects of novel metallization schemes and tight pitch copper/low-k interconnects from a reliability standpoint.     

An investigation of ultra low-k dielectrics with high thermal stability for integration in memory devices

For the PMD in a next generation memory device, two kinds of newly developed ultra low-k MSQ materials (k < 2.0) are shown to have good thermal stability, up to 600 °C, while the investigated HSQ (k = 2.9) material degraded at temperatures >500 °C. The thermal stability of the low-k MSQ is correlated with the amount of Si-X (X = H or CH₃), the ratio of Si-X to Si-O, and the structure of the Si-O bonds. With PE-SiO₂ and PE-SiN capping on HSQ, the k-value of  < 3.0 can be maintained up to 800 °C due to Si-H remaining in the film. Similarly, PE-SiC and PE-SiO₂ capping increases the k-value degradation onset temperature of the MSQ materials by 50 °C.