Circuit implications of the metal-gate polysilicon source-and-drain MOST process

The use of polysilicon layers as a diffusion source opens the way to a number of device innovations. One of these is the metal-gate `polysilicon source-and-drain' (PSD) MOST. Its main feature is a shrinkage in device size caused by the `automatic' (i.e., without any explicit contact window) connection between diffused regions and a polysilicon interconnection level. The advantages of this new process are elucidated in a comparison between PSD-MOST circuits and the standard `polysilicon self-aligned gate' (PSAG)-MOST circuits. Technological details have a mixed effect on device-circuit characteristics. By structuring the comparison into a device, a cell, and a circuit level, specific effects can be isolated and subsequently pointed out. It is shown, that PSD circuits potentially lead to a 33 percent higher packing density at a 25 percent higher switching speed, compared to standard PSAG circuits. Reliability has also been improved as the active area consumption is reduced by 50 percent together with a 75 percent decrease in the number of contact windows.     

Design of a novel double doping polysilicon gate MOSFET

In this paper, a novel design of the double doping polysilicon gate MOSFET device is proposed, which has a p+ buried layer near the drain, and relatively thicker D-gate oxide film (DDPGPD MOSFET). The detailed fabrication process for this device is designed using process simulation software called TSUPREM, and the device structure plan is further used in MEDICI simulation. The effect of gate doping concentration is investigated, and it is found that the device V_th is only influenced by the S-gate; furthermore, the device can get a larger driving current by increasing the doping concentration of D-gate. Compared to other conventional DDPG MOSFETs, the short-channel effects (SCEs) including the off-state current, the gate leakage current and the drain induced barrier lowering effect (DIBL) can be effectively suppressed by the p+ buried layer and thicker D-gate oxide film. Additionally, the other parameters of the device such as the driving current are not seriously affected by the proposed design modifications.     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

The effect of biased spacers on LDD MOSFET behavior

The concept of using LDD spacers that are independently biased with respect to the gate electrode is presented. It is shown that the lateral electric field is strongly influenced by the drain polysilicon spacer potential. Depending on the N^- dose, the peak substrate currents can be either enhanced or reduced by shorting the drain polysilicon spacer to the drain potential. Short-channel LDD MOSFETs have been fabricated with polysilicon LDD spacers shorted to the source and drain electrodes by titanium silicide     

Indirect fitting procedure to separate the effects of mobility degradation and source-and-drain resistance in MOSFET parameter extraction

A new procedure is presented to separate the effects of source-and-drain series resistance and mobility degradation factor in the extraction of MOSFET model parameters. It requires only a single test device and it is based on fitting the I_D(V_GS, V_DS) equation to the measured characteristics. Two types of bidimensional fitting are explored: direct fitting to the drain current and indirect fitting to the measured source-to-drain resistance. The indirect fitting is shown to be advantageous in terms of fewer number of iterations needed and wider extent of initial guess values range.     

A new MOSFET structure with self-aligned polysilicon source and drain electrodes

A new MOSFET structure whose source and drain electrodes are self-aligned to the gate electrode is proposed. The new structure utilizes a second layer of polysilicon which is defined by a preferrential etching to form the source and drain regions. Due to the self-alignment property of the source and drain regions, the total device size is decreased by about 50 percent over the conventional MOS transistors when the same design rule is used. Experimental results of the new structure are presented.     

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior     

A novel self-aligned offset-gated polysilicon TFT using high-/spl kappa/ dielectric spacers

In this letter, a novel self-aligned offset-gated Poly-Si thin-film transistor (TFT) using high-/spl kappa/ dielectric Hafnium oxide (HfO/sub 2/) spacers is proposed and demonstrated. The HfO/sub 2/ film is deposited by magnetron sputter deposition, and the HfO/sub 2/ spacers are formed by reactive ion etching. The permittivity of the deposited HfO/sub 2/ is approximately 20. Experimental results show that with the high vertical field induced underneath the high-/spl kappa/ spacers, an inversion layer is formed, and it effectively increases the on-state current while still maintaining a low leakage current in the off-state, compared to the conventional lightly doped drain or oxide spacer TFTs. The on-state current in the offset-gated Poly-Si TFT using the HfO/sub 2/ spacers is approximately two times higher than that of the conventional oxide spacer TFT.     

A novel elevated MOSFET source/drain structure

A vertically layered elevated drain structure is proposed which is suitable, in terms of reliability and performance for MOSFET scaling down to the 0.25-μm level without a reduction of the supply voltage below 3.3 V. In this structure, a low-doped polysilicon or crystalline silicon spacer (layer) is used to solve the hot-carrier problem. In contrast to existing device structures, which try to minimize the impact ionization rate, this structure rests on the idea that high-impact ionization and even high hot-carrier injection (HCl) rates can be tolerated as long as they are not detrimental to the device characteristics     

Effects of longitudinal and latitudinal grain boundaries on theperformance of large-grain polysilicon MOSFET

The effects of longitudinal and latitudinal polysilicon grain boundaries on the performance metal oxide semiconductor field effect transistors (MOSFETs) fabricated on large-grain polysilicon-on-insulator (LPSOI) have been investigated. Unlike conventional thin-film-transistors (TFTs) with random grain distribution, MOSFETs fabricated on the LPSOI film contains the combination of only longitudinal or latitudinal grain boundaries. Longitudinal GBs parallel to the direction of current flow has smaller impact to the current flow, but provided extra leakage current that caused early device shortage, especially in wide devices. The latitudinal GBs perpendicular to the direction of current flow offered higher resistance to the inversion carriers thus causing lower current drive, higher threshold voltage, and gentler subthreshold slope. The result of the study can be used to optimize device design for high performance on MOSFETs on the LPSOI substrate     

Tunable work function in fully nickel-silicided polysilicon gates for metal gate MOSFET applications

The work function of fully nickel-silicided polysilicon was investigated. The midgap work function (4.7 eV) was obtained for undoped mononickel-silicide (NiSi). It was shown that the implantation of both arsenic and antimony into the polysilicon before silicidation reduces the NiSi work function, and the change in work function is greater for antimony than for arsenic. The pile-up of these species at the oxide interface during the nickel silicidation is demonstrated to be the physical mechanism responsible for the work function shift. Both species activations before silicidation and silicidation conditions were found to affect the NiSi work function shift significantly. The nonactivated species have minimum effect and incomplete silicidation can have maximum work function shift. The doping effect of indium on the NiSi work function is reported for the first time. A shift of /spl sim/0.14 eV toward the valence band was obtained for 2.6-nm oxide capacitors. It was found that the work function shift caused by the indium doping is saturated at a relatively low dose, which may be related to the low solid solubility of indium in polysilicon.     

Degradation of submicron N-channel MOSFET hot electron reliabilitydue to edge damage from polysilicon gate plasma etching

The impact of poly-Si gate plasma etching on the hot electron reliability of submicron NMOS transistors has been explored. The results show that the gate oxide and SiO₂-Si interface near the drain junction have a susceptibility to hot electron injection that increases with overetch time. We show for the first time that this degradation of hot electron reliability is attributable to the edge type of gate oxide damage resulting from direct plasma exposure during overetch processing. We demonstrate that this type of damage does not scale with channel length and becomes even more important in shorter channel transistors     

Accounting for quantum effects and polysilicon depletion from weak to strong inversion in a charge-based design-oriented MOSFET model

This paper presents a simple, physics-based, and continuous model for the quantum effects and polydepletion in deep-submicrometer MOSFETs with very thin gate oxide thicknesses. This analytical design-oriented MOSFET model correctly predicts inversion and depletion charges, transcapacitances, and drain current, from weak to strong inversion and from nonsaturation to saturation. One single additional parameter is used for polysilicon doping concentration, while the quantum correction does not introduce any new parameter. Comparison to experimental data of deep-submicrometer technologies is provided, showing accurate fits both for I-V and C-V data. The model offers simple relationships among effective electrical parameters and physical device parameters, providing insight into the physical phenomena. This new model thereby supports device engineering, analog circuit design practice, as well as efficient circuit simulation.     

The origins of the performance degradation of implanted p+ polysilicon gated p-channel MOSFET with/without rapid thermalannealing

Some anomalous behaviors, such as punchthrough voltage reduction, leakage current increase, and transconductance (g_m) instability have been found in BF₂ implanted p⁺-polysilicon P-MOSFET's. These effects are supposed to be due to B-ion penetration. To prevent the B-ion penetration, RTA has been used. Experimental results show that RTA can improve the effect, however, the RTA process can also cause the generation of interface states, gate-induced-drain-leakage increase, and oxide quality degradation. All of the mechanisms of performance degradation are investigated and modeled in detail     

Improved current drivability with back-gate bias for elevated source and drain structured FD-SOI SiGe MOSFET

Fully depleted (FD) silicon-on-insulator (SOI) MOSFET structure with back-gate bias is suggested for high speed and low power consumption for portable communication application. Ni silicide is demonstrated for improving current drivability for low power consumption by reducing series resistance in the source and drain region. Threshold voltage adjustment is also achieved through applied back-gate bias. For the formation of the buried back-gate, the selection of impurity type as well as its doping concentration is controlled. Employing back-gate bias for FD-SOI NMOSFET, improved current drivability with variable threshold voltage is achieved. Short channel devices are fabricated and its electrical characteristics are obtained under various conditions.     

Influence of polysilicon deposition on fabrication of power polysilicon emitter bipolar transistors

The aim was to fabricate a polysilicon emitter bipolar transistor for power applications. To this end, different polysilicon deposition steps compatible with the power bipolar technology and their influence on electrical characteristics were studied.<>     

Characterization of polysilicon oxides thermally grown anddeposited on the polished polysilicon films

This work examines the characteristics of polyoxides thermally grown and deposited on polished polysilicon films. A well-controlled chemical mechanical polishing (CMP) process is also presented to achieve a planar surface morphology for polysilicon films. The thermally-grown and deposited polyoxides on the polished polysilicon films exhibit a lower leakage current, higher dielectric breakdown field, higher electron barrier height, lower electron trapping rate, lower density of trapped charges, and markedly higher charge to breakdown (Q_bd) than the conventional polyoxide. In particular, the deposited polyoxide on the polished polysilicon film has the highest dielectric breakdown field, lowest electron trapping rate, and highest charge to breakdown due to the planar polyoxide/polysilicon interface. In addition, experimental results indicate that the trapped charges of the polished samples are located in the polyoxides' upper portion, which differs from conventional polyoxides. Undoubtedly, the deposited polyoxide on the polished polysilicon film considered herein is the most promising candidate to yield optimum characteristics of polyoxide     

Tenth-micron polysilicon thin-film transistors

Small thin-film polysilicon transistors are of interest for load devices in static random-access memory (SRAM) cells of the near future. We present measured characteristics of thin-film transistors (TFT's) with gate lengths ranging from 7 to 0.12 μm made in large-grain polysilicon