Observation of bias-dependent capture-emission processes in MBE-grown GaAs layers

The capture-emission process in a semiconductor sample was greatly affected by a varying electric field in DLTS analysis. The sample was an n-type GaAs layer grown on a 〈100〉-oriented seimi-insulating substrate by molecular beam epitaxy. An E_c − 0.5 eV electron trap level was found under lower bias voltage (−6 V) while both E_c − 0.40 eV and E_c − 0.50 eV traps were observed under higher bias voltage (−7.0 to −8.0 V). Emission rates have been measured that increased with increasing bias voltage from 0 V to −5 V and then decreased when biases were higher than −5 V. In the capacitance transient, when it revealed a delay, two levels, namely at −0.4 and −0.5 eV, appeared in the DLTS signals. However, the EL2 trap (E_c − 0.78 eV), found on another sample, revealed monotonically increasing emission with increasing bias.An explanation of these phenomena was proposed in light of the interaction of these two levels due to the electric field effect.     

Germanium as a deep level in alxga1− xas grown by organometallic vapor phase epitaxy

Optoelectronic devices require materials which exhibit extremely low trap concentrations. The Al_xGa_1−xAs system has been used extensively for optoelectronic applications despite trap concentrations in the Al_xGa_1−xAs which limit the efficiency of the resulting devices. Deep level transient spectroscopy (DLTS) performed on Al_0.2Ga_0.8As layers grown by organometallic vapor phase epitaxy (OMVPE) has revealed three traps with concentrations >10¹³ cm⁻³ -E _c-E_t = 0.3, 0.5 and 0.7 eV. The dominant source of the 0.3 eV trap has proven to be a Ge impurity in arsine. SIMS analysis of Al_0.2Ga_0.8As samples show Ge as the only candidate for the impurity responsible for the 0.3 eV trap. DLTS and SIMS analysis performed on Al_0.2Ga_0.8As samples intentionally doped with Ge displayed a proportional increase in the 0.3 eV trap concentration with the Ge concentration and establishes that Ge is indeed the source of the 0.3 eV trap in Al_xGa_1−xAs. Comparison of C-V, SIMS and DLTS measurements performed on Al_xGa_1-xAs:Ge indicate that approximately 30% of elemental Ge incorporated created the 0.3 eV trap, DX_Ge.     

Effects of GaAs buffer layer and lattice-matching on deep levels in Zn(S)Se/GaAs heterostructures

The effects of GaAs buffer layer and lattice-matching on the nature of deep levels involved in Zn(S)Se/GaAs heterostructures are investigated by means of deeplevel transient spectroscopy (DLTS). The heterojunction diodes (HDs) where nZn(S)Se is grown on p⁺-GaAs by metalorganic vapor phase epitaxy are used as a test structure. The DLTS measurement reveals that when ZnSe is directly grown on a GaAs substrate, there exist five electron traps A-E at activation energies of 0.20, 0.23, 0.25, 0.37, and 0.53 eV, respectively. Either GaAs buffer layer and lattice-matching may reduce the incorporation of traps C, D, and E, implying that these traps are ascribed to surface treatment of GaAs substrate and to lattice relaxation. Concentration of trap B, which is the most dominant level, is proportional to the donor concentration. However, in the ZnSSe/GaAs sub. HD, another trap level, instead of trap B, locates at the almost same position as that of trap B, and it shows anomalous behavior that the DLTS peak amplitude changes drastically as changing the rate windows. This is explained by the defect generation through the interaction between sulfide and a GaAs substrate surface. For the trap A, the concentration is a function of donor concentration and lattice mismatch, and the origin is attributed to a complex of donor induced defects and dislocations.     

Interface trap and interface depletion in lattice-mismatched GaInAs/GaAs heterostructures

The effects of lattice mismatch on the deep traps and interface depletion have been studied for the Ga_0.92In_0.08As(p⁺)/GaAs(N) and Ga_0.92In_0.08As(n)/GaAs(SI) heterostructures grown by molecular beam epitaxy. We have used deep level transient spectroscopy (DLTS) and admittance spectroscopy (AS) and observed two hole traps, one at an energy ranging from 0.1 to 0.4 eV and the other at 0.64 eV, and two electron traps at 0.49 and 0.83 eV in the GalnAs/GaAsp ⁺-N junction sample. The hole trap appeared as a broad peak in the DLTS data and its energy distribution (0.1 ∼ 0.4 eV) was obtained by a simulation fitting of the peak. Concentration of this distributed hole trap increased as the in-plane mismatch increased, suggesting its relation to defects induced by lattice relaxation, whereas the other traps are from the bulk. The misfit dislocations are believed to be responsible for the interface trap. For the Ga_0.92In_0.08As(n)/GaAs(SI) samples, Hall effect measurements showed an increased interface depletion width of about 0.14 Μm for the 0.5 Μm thick layer and about 0.12 /gmm for the 0.25 Μm thick layer, while a corresponding GaAs/GaAs sample had only 0.088 Μm for the interface depletion width.     

Electron and hole traps in GaN p-i-n photodetectors grown by reactive molecular beam epitaxy

GaN p-i-n photodetectors grown on sapphire by reactive molecular beam epitaxy have been characterized by measurements of room-temperature current-voltage (I-V), temperature-dependent capacitance (C-V-T), and deep level transient spectroscopy (DLTS) under both majority and minority carrier injection. Due to what we believe to be threading dislocations, the reverse I-V curves of p-i-n photodetectors show typical electric-field enhanced soft breakdown characteristics. A carrier freeze-out due to the de-ionization of Mg-related deep acceptors has been found by C-V-T measurements. Three electron traps, B (0.61 eV), D (0.23 eV), and E₁ (0.25 eV) and one hole trap, H₃ (0.79 eV) have been revealed by DLTS measurements. The photodetectors with lower leakage currents usually show higher responsivity and lower trap densities of D and E₁.     

Evidence for causality between GaN RF HEMT degradation and the EC-0.57 eV trap in GaN

The degradation of industry-supplied GaN high electron mobility transistors (HEMTs) subjected to accelerated life testing (ALT) is directly related to increases in concentrations of two defects with trap energies of E_C-0.57 and E_C-0.75 eV. Pulsed I-V measurements and constant drain current deep level transient spectroscopy were employed to evaluate the quantitative impact of each trap. The trap concentration increases were only observed in devices that showed a 1 dB drop in output power and not the result of the ALT itself indicating that these traps and primarily the E_C-0.57 eV trap are responsible for the output power degradation. Increases from the E_C-0.57 eV level were responsible for 80% of the increased knee walkout while the E_C-0.75 eV contributed only 20%. These traps are located in the drain access region, likely in the GaN buffer, and cause increased knee walkout after the application of drain voltage.     

Deep electron levels in undoped polycrystalline CdTe annealed in liquid Cd

The method of deep-level transient spectroscopy (DLTS) is used to determine the set of deep electron levels in undoped n-CdTe polycrystals grown by chemical synthesis from vapor phase in highly nonequilibrium conditions and then subjected to annealing in liquid Cd. After annealing, the electron concentration is found to increase from ∼10⁸ to 10¹⁵ cm⁻³. Electron traps with deep levels E ₁ = 0.84 ± 0.03 eV and E ₂ = 0.71 ± 0.02 eV with total concentration ∼10¹⁴ cm⁻³ are dominant in the DLTS spectrum. The role of grain boundaries and intrinsic point defects in formation of deep-level centers and their effect on the value of conductivity after annealing are discussed. A relation between the level E ₁ and complexes of intrinsic point defects and relation of the level E ₂ to the Cd _i point defect are considered.     

Traps in 4H-SiC Field-Effect Transistors Characterized by Capacitance- and Current-Mode Deep-Level Transient Spectroscopy

Traps in SiC long-gate metal–semiconductor field-effect transistors (FATFETs) at different wafer positions have been characterized by deep-level transient spectroscopy (DLTS) based on capacitance (C-DLTS) or current (I-DLTS). Two major electron traps, Z _1/2 and V _1/2, of energies 0.68 eV and 0.91 eV, respectively, are found mainly in the SiC buffer layer, and several hole-like traps appear in the surface or interface regions. In some regions of the wafer, an electron trap EH_6/7 of energy 1.77 eV is prominent. Trap EH_6/7 as well as the hole-like traps are not uniformly distributed on the wafer.     

Study of grown-in defects and effect of thermal annealing in Al0.3Ga0.7As and GaAs LPE layers

Studies of the grown-in deep-level defects in the undoped n-Al_xGa_1-xAs (x = 0.3) and GaAs epitaxial layers prepared by the liquid phase epitaxy (LPE) techniques have been made, using DLTS, I-V and C-V measurements. The effect of 300 °C thermal annealing on the grown-in defects was investigated as a function of annealing time. The results showed that significant reduction in these grown-in defects can be achieved via low temperature thermal annealing process. The main electron and hole traps observed in the Al_0.3Ga_0.7As LPE layer were due to the E_c-0.31 eV and E_v+0.18 eV level, respectively, while for the GaAs LPE layer, the electron traps were due to the E_c-0.42 and 0.60 eV levels, and the hole traps were due to E_v+0.40 and 0.71 eV levels. Research supported in part by the Air Force Wright Aeronautical Laboratories, Aeropropulsion Lab., Wright Patterson Air Force Base, Ohio, subcontract through SCEEE, contract F33615-81-C-2011, task-4, and in part by AFOSR grant no. 81-0187.     

Study of electrically active defects in n-GaN layer

Deep level defects in both p⁺/n junctions and n-type Schottky GaN diodes are studied using the Fourier transform deep level transient spectroscopy. An electron trap level was detected in the range of energies at E_c−E_t=0.23–0.27 eV with a capture cross-section of the order of 10⁻¹⁹–10⁻¹⁶ cm² for both the p⁺/n and n-type Schottky GaN diodes. For one set of p⁺/n diodes with a structure of Au/Pt/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au and the n-type Schottky diodes, two other common electron traps are found at energy positions, E_c−E_t=0.53–0.56 eV and 0.79–0.82 eV. In addition, an electron trap level with energy position at E_c−E_t=1.07 eV and a capture cross-section of σ_n=1.6×10⁻¹³ cm² are detected for the n-type Schottky diodes. This trap level has not been previously reported in the literature. For the other set of p⁺/n diodes with a structure of Au/Ni/p⁺–GaN/n–GaN/n⁺–GaN/Ti/Al/Pd/Au, a prominent minority carrier (hole) trap level was also identified with an energy position at E_t−E_v=0.85 eV and a capture cross-section of σ_n=8.1×10⁻¹⁴ cm². The 0.56 eV electron trap level observed in n-type Schottky diode and the 0.23 eV electron trap level detected in the p⁺/n diode with Ni/Au contact are attributed to the extended defects based on the observation of logarithmic capture kinetics.     

硅中钛的若干物理性质

本文报道研究扩散掺钛的硅中深能级的结果。用DLTS法观测到三个与钛有关的深能级,即在n-Si(Ti)中有二个电子陷阱,能级位置分别为Ec0.23eV和Ec0.53eV,在p-Si(Ti)中有一个空穴陷阱,能级位置为Ev+0.32eV。详细的电容瞬态研究得到了这些能级在一定测试温度范围内的热激活能和俘获截面以及其它有关参量。本文还就测量结果对能级的键合性质和钉扎于那一能带做了讨论。     

Investigation of deep level defects in electron irradiated indium arsenide quantum dots embedded in a gallium arsenide matrix

Gallium arsenide diodes with and without indium arsenide quantum dots were electron irradiated to investigate radiation induced defects. Baseline and quantum dot gallium arsenide pn-junction diodes were characterized by capacitance–voltage measurements, and deep level transient spectroscopy. Carrier accumulation was observed in the gallium arsenide quantum dot sample at the designed depth for the quantum dots via capacitance–voltage measurements. Prior to irradiation, a defect 0.84 eV below the conduction band (E_C – 0.84 eV) was observed in the baseline sample which is consistent with the native EL2 defect seen in gallium arsenide. After 1 MeV electron irradiation three new defects were observed in the baseline sample, labeled as E3 (E_C – 0.25 eV), E4 (E_C – 0.55 eV), and E5 (E_C – 0.76 eV), consistent with literature reports of electron irradiated gallium arsenide. Prior to irradiation, the addition of quantum dots appeared to have introduced defect levels at E_C – 0.21, E_C – 0.38, and E_C – 0.75 eV denoted as QD–DX1, QD–DX2, and QD–EL2 respectively. In the quantum dot sample after 1 MeV electron irradiation, QD–E3 (E_C – 0.28 eV), QD–E4 (E_C – 0.49 eV), and QD–EL2 (E_C – 0.72 eV) defects, similar to the baseline sample, were observed, although the trap density was dissimilar to that of the baseline sample. The quantum dot sample showed a higher density of the QD–E4 defect and a lower density of QD–E3, while the QD–EL2 defect seemed to be unaffected by electron irradiation. These findings suggest that the quantum dot sample may be more radiation tolerant to the E3 defect as compared to the baseline sample.     

Electron trap behaviour in Te-doped GaAs0.6P0.4

An electron trap spectrum has been obtained in Te-doped GaAsP by DLTs and transient capacitance measurements. The two traps identified display non-exponential emission and capture characteristics, the capture rate depending on temperature. The dominant trap A has an activation energy, E_a = 0.20 ± 0.02 eV and a constant concentration in the epilayer of typically 0.1N_d, trap B has an activation energy, E_a = 0.4 eV.The defect is donor related and characterised by non-radiative capture and lattice-relaxation multiphonon emission. Photocapacitance measurements provide the electron photoionization cross-section of the centre, and in agreement, a phonon broadened lineshape theory gave a threshold of 0.62 eV supporting the large lattice relaxation model. Evidence for persistent photoconductivity is also presented.     

Interface states and deep-level centers in silicon-on-insulator structures

Deep-level centers in a split-off silicon layer and trap levels were studied by deep-level transient spectroscopy both at the Si/SiO₂ interface obtained by direct bonding and also at the Si(substrate)/〈thermal SiO₂〉 interface in the silicon-on-insulator structures formed by bonding the silicon wafers and delaminating one of the wafers using hydrogen implantation. It is shown that the Si/〈thermal SiO₂〉 interface in a silicon-on-insulator structure has a continuous spectrum of trap states, which is close to that for classical metal-insulator-semiconductor structures. The distribution of states in the upper half of the band gap for the bonded Si/SiO₂ interface is characterized by a relatively narrow band of states within the range from E _c −0.17 eV to E _c −0.36 eV. Furthermore, two centers with levels at E _c −0.39 eV and E _c −0.58 eV are observed in the split-off silicon layer; these centers are concentrated in a surface layer with the thickness of up to 0.21 μm and are supposedly related to residual postimplantation defects. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 35, No. 8, 2001, pp. 948–953. Original Russian Text Copyright ? 2001 by Antonova, Stano, Nikolaev, Naumova, Popov, Skuratov.     

Similarities of lag phenomena and current collapse in field-plate AlGaN/GaN HEMTs with different types of buffer layers

We make a two-dimensional transient analysis of field-plate AlGaN/GaN high electron mobility transistors (HEMTs) with a Fe-doped semi-insulating buffer layer, which is modeled that as deep levels, only a deep acceptor located above the midgap is included (E_C − E_DA = 0.5 eV, E_C: energy level at the bottom of conduction band, E_DA: deep acceptor's energy level). And the results are compared with a case having an undoped semi-insulating buffer layer in which a deep donor above the midgap (E_C − E_DD = 0.5 eV. E_DD: the deep donor's energy level) is considered to compensate a deep acceptor below the midgap (E_DA − E_V = 0.6 eV, E_V: energy level at the top of valence band). It is shown that the drain-current responses when the drain voltage is lowered abruptly are reproduced quite similarly between the two cases with different types of buffer layers, although the time region where the slow current transients occur is a little different. The lags and current collapse are reduced by introducing a field plate. This reduction in lags and current collapse occurs because the deep acceptor's electron trapping is reduced under the gate region in the buffer layer. The dependence of drain lag, gate lag and current collapse on the field-plate length and the SiN layer thickness is also studied, indicating that the rates of drain lag, gate lag and current collapse are quantitatively quite similar between the two cases with different types of buffer layers when the deep-acceptor densities are the same.     

Electrical characterization of defects introduced during electron beam deposition of W Schottky contacts on n-type 4H-SiC

We have studied the defects introduced in n-type 4H-SiC during electron beam deposition (EBD) of tungsten by deep-level transient spectroscopy (DLTS). The results from current-voltage and capacitance-voltage measurements showed deviations from ideality due to damage, but were still well suited to a DLTS study. We compared the electrical properties of six electrically active defects observed in EBD Schottky barrier diodes with those introduced in resistively evaporated material on the same material, as-grown, as well as after high energy electron irradiation (HEEI). We observed that EBD introduced two electrically active defects with energies E_C – 0.42 and E_C – 0.70 eV in the 4H-SiC at and near the interface with the tungsten. The defects introduced by EBD had properties similar to defect attributed to the silicon or carbon vacancy, introduced during HEEI of 4H-SiC. EBD was also responsible for the increase in concentration of a defect attributed to nitrogen impurities (E_C – 0.10) as well as a defect linked to the carbon vacancy (E_C – 0.67). Annealing at 400 °C in Ar ambient removed these two defects introduced during the EBD.     

Electron traps created by high temperature annealing in MBE n-GaAs

An electron trap with a thermal activation energy of 0.83 eV from the conduction band is common in the deep level transient spectroscopy (DLTS) spectra of vapor phase epitaxial (VPE) n-GaAs, but is not observed in the DLTS spectra of as-grown molecular beam epitaxial (MBE) n-GaAs. We show here that this trap is created during high temperature annealing of MBE samples with a Si₃N₄, encapsulant. The trap concentration is correlated with the annealing temperature and time, suggesting the outdiffusion of a constituent atom resulting in the formation of a vacancy or vacancy-complex. Other electron traps observed in the DLTS spectra of asgrown MBE n-GaAs are annealed out for temperatures at or above 800° C.     

Minority carrier diffusion lengths in bulkn-type gaas

Minority carrier hole diffusion lengths in as-grown and Ni- or Cu-diffused bulkn-GaAs, both LEC and HB, having carrier concentrations in the range 10¹⁶-10¹⁷cm⁻³ have been studied by surface photovoltage methods and trap concentrations determined by DLTS measurements. Data are available for a wide range of specimens and therefore a method of correlation ofL _p with electron trap concentrations has been developed that allows easy identification of the dominant recombination center. This is determined to be the level at aboutE _c -0.40 eV, termed EL5 in earlier studies of electron traps.     

DLTS characterisation of InGaAlP films grown using different V/III ratios

Deep levels in InGaAlP films grown using two different V/III ratios have been studied by employing deep level transient spectroscopy (DLTS). The two samples investigated have the same composition of (Al_0.3Ga_0.7)_0.51In_0.49P and a film thickness of 0.6 μm, but grown with V/III ratios 75 and 50. Two defect levels with activation energies 0.23 and 0.78 eV are detected by temperature-scan DLTS in the sample with a V/III ratio of 75, with the 0.78 eV level being the dominant peak. Their respective capture cross-sections are 1.2×10⁻¹⁶ and 3.8×10⁻¹³ cm⁻². The 0.78 eV trap level is also analysed using isothermal DLTS measurement and similar values of thermal signatures are obtained. The DLTS spectrum of the 0.78 eV trap level has been found to be broader than that expected for a point-type defect, implying that it may be associated with a complex or extended defect. The observation of logarithmic capture mechanism further supports this speculation. On the other hand, no peak corresponding to the 0.23 eV level appears in isothermal DLTS spectra, which is possibly due to the severe temperature dependence of capture rate and the system's limitation in the high-frequency regime. For the sample with a V/III ratio of 50, only one dominant electron trap level, with an activation energy of 0.42 eV and a capture cross-section of 1.4×10⁻¹⁷ cm⁻², is detected by isothermal DLTS method.     

Effect of surface passivation by SiN/SiO2 of AlGaN/GaN high-electron mobility transistors on Si substrate by deep level transient spectroscopy method

Device performance and defects in AlGaN/GaN high-electron mobility transistors have been correlated. The effect of SiN/SiO₂ passivation of the surface of AlGaN/GaN high-electron mobility transistors on Si substrates is reported on DC characteristics. Deep level transient spectroscopy (DLTS) measurements were performed on the device after the passivation by a (50/100 nm) SiN/SiO₂ film. The DLTS spectra from these measurements showed the existence of the same electron trap on the surface of the device.