V型电热硅微致动器动态频率特性

提出了V型电热硅微致动器的弯曲振动力学模型。考虑到微米尺度上的硅梁难以简化为质量块、弹簧振动模型,采用了连续体建模,据此可进行其模态分析及动态频率特性的理论研究。利用自行设计制造的在线动态测试机构,测试了V型电热硅微致器在不同激励电压驱动下的响应输出,结果表明其位移输出也是随交变驱动电压的变化而非同步地发生变化。     

基于柔性铰链支承的热驱动硅微机械手的力学模型及性能分析

微机械手是一种典型的微型执行器,是微型机电系统(MEMS)的重要研究内容之一.以基于柔性铰链的电热驱动硅微机械手为研究对象,建立了微夹钳的二次超静定力学模型,导出了钳口处输出位移的解析式,并在此基础上对硅微机械手的性能进行了分析.分析表明,微夹钳的输出位移与柔性铰链切割半径成正比,切割半径越大,输出位移越大;对各加载电压下的微夹钳输出位移,其试验和理论结果的变化趋势一致,即微夹钳输出位移随输入电压的增加基本呈线性增加.     

基于BP神经网络的U型电热微致动器仿真分析

以BP神经网络、随机有限元法为基础,对u型电热微致动器进行了仿真分析．首先利用有限元分析软件ANSYS对u型电热微致动器进行有限元分析得到具体结构尺寸对微致动器最大位移的影响,然后通过建立的BP神经网络来拟合响应与输入之间的关系,根据蒙特卡罗模拟原理获得足够多的样本值对训练后的网络进行误差分析,结果证明本文提出的分析方法是可行有效的．     

微致动器在流动控制中的应用研究

基于MEMS技术,研制了一种微气泡型致动器.对前缘布置有微致动器的三角翼进行了数值模拟和风洞实验,结果表明:微致动器可以改变三角翼前缘的旋涡流状态,扰动边界层,改变三角翼前缘分离涡位置,合理布置微致动器可以获得一定的滚转力矩,利用微致动器可以进行流动控制,进而改变飞行器的动力性能.     

基于新型压电致动器的微隔振平台系统

为实现微隔振平台的自适应控制,设计了具有驱动和传感功能的第三代压电致动器,针对其直接应用于微隔振系统隔振效果不是很理想的现状.从理论上分析了导致结果不理想的原因,提出一种改进方法,通过理论建模分析和试验研究,结果表明:该方法虽然降低了致动器位移增益.但具有较好的隔振效果.     

计算微致动器结构可靠度的新方法

为了解决微致动器结构功能函数不能明确表示的可靠度分析问题,以BP神经网络、响应面法为基础,提出了求解可靠度的几何分析新方法:对神经网络响应面法加以改进并利用其拟合极限状态函数,得到显示的结构功能函数表达式;利用均值波动法对微致动器局部应力最大处进行可靠度分析,求得结构可靠度因子β为3.353.与JC法比较,方法简便可行,为结构可靠度计算问题提供了新的有效的思路和方法.     

微光机电陀螺微致动器设计与有限元分析

提出了一种锆钛酸铅(PZT)薄膜微致动器的结构模型。该致动器采用高d33特性的压电陶瓷材料,用于对空间谐振式微光机电(MOEMS)陀螺微镜进行位移和角度的精确定位。建立了该致动器的简化模型并利用有限元方法分析其驱动能力。结果显示,当采用双层结构的PZT薄膜微致动器时,在外加电压50V作用下,环形PZT位移控制器中心位移可达到0.345μm;十字形角度控制器偏转角度可达3.29″,增加PZT薄膜的层数可以进一步增加致动器对微镜位移和角度的控制能力。通过对仿真结果进行分析可以得出结论,选用多层PZT薄膜材料制成的微致动器能够满足调整微镜位移和角度所需的范围和精度要求。     

刮板式微致动器性能研究

刮板式微致动器,是一种可以实现大位移、步进式MEMS纳米微致动器。结合刮板式微致动器的表面硅加工工艺,考虑支撑梁的反作用力建立了新的理论分析模型,分析了微致动器的临界电压、单步位移以及最大输出位移等几个重要性能参数,将理论模型的计算结果与已有的实验数据以及理论模型作了对比。结果表明,本文理论分析模型的的理论值与实验结果有较好的一致性。     

基于超磁致致动器的车削振动主动控制

设计了一种基于模糊PID控制器和超磁致伸缩致动器的车削振动主动控制系统,推导了超磁致伸缩致动器和专用刀架的数学模型,并在Matlab环境下进行建模仿真,当振动频率在50~100Hz时,仿真结果表明该控制系统能抑制振幅达50%以上;在现场车削试验中,以普通45#钢为车削工件,分别在转速1 500r/min、车削深度为0.07mm和转速3 000r/min,车削深度为0.04mm下,对车削振动进行主动控制,结果证明所设计的车削振动控制系统能够抑制振动幅度达30%以上。     

压电致动器的力学输出计算

针对单层压电致动器在电压激励下力学输出计算比较困难的现实问题,该文提出将压电致动器与质量-弹簧-阻尼系统有机结合,将压电片在电压激励下的形变转化为质量-弹簧-阻尼系统的位移,然后根据系统的微分方程,利用拉普拉斯变换和反变换,分别求出在正弦交流电和直流阶跃激励下的压电致动片的力学输出计算公式。最后分别用压电陶瓷致动片和PVDF致动片进行了验证,与已有的方法计算结果进行了比较,实验结果高度一致,说明该方法具有可行性、易行性与实用性。     

微电热驱动器中偏置层的分析

设计了一种电热微驱动器,根据几何关系、泰勒公式和材料力学求得偏置层结构末端的位移公式,并验证了采用镍作为偏置层材料的合理性.通过Coventorware软件中的有限元模块进行仿真分析,得出施加驱动电压为5 V,响应时间为5 ms,驱动器的初始温度为300 K时,得出偏置层宽度W1与驱动器位移d的曲线关系.通过验证驱动器的最大应力为235 MPa,小于镍的许用应力,确定驱动器在W1=20μm可以进行可靠的工作.分析偏置层厚度和宽度的加工误差对驱动器末端位移的影响,可得在对偏置层进行加工时要严格控制偏置层厚度H1的加工误差.     

Analysis and design of ribbon cables for high‐speed digital applications

Ribbon cables have been widely used as subsystem interconnections in a large number of digital systems, because they can convey numerous bits of a digital signal simultaneously. In this article, finite difference and finite difference time domain (FDTD) methods are used to analyze and optimize the electrostatic analysis design of ribbon cables, and measurements are used to verify the numerical results. © 2002 Wiley Periodicals, Inc. Int J RF and Microwave CAE 12: 148–158, 2002.     

Localized relaxation theory of circuits and its applications in electro-thermal analyses

In the high-performance IC design with increasing design complexity,it is a very important design content to efficiently analyze IC parameters.Thus,the electro-thermal (ET) analyses including power/ground (P/G) analysis and thermal analysis are hot topics in today’s IC research.Since ET analysis equation has a sparse,positive definite and strictly diagonally dominant coefficient-matrix,we prove that the ET analysis has the advantage of locality.Owing to this advantage,localized relaxation method is formally proposed,which has the same accuracy as the global relaxation done with the constraint of the same truncation error limitation.Based on the localized relaxation theory,an efficient and practical localized successive over-relaxation algorithm (LSOR2) is introduced and applied to solve the following three ET analysis problems.(1) Single-node statistical voltage analysis for over-IR-drop nodes in P/G networks;(2) single-node statistical temperature analysis for hot spots in 3D thermal analysis;(3) fast single open-defect analysis for P/G networks.A large amount of experimental data demonstrates that compared with the global successive over-relaxation (SOR) algorithm,LSOR2 can speed up 1-2 orders of magnitudes with the same accuracy in ET analyses.     

局部松弛电路理论及其在电热分析中的应用

在复杂度日益增高的高性能集成电路设计中,高效的性能分析是一项重要的设计内容,其中由电源线/地线网络(P/G)分析与芯片热分析构成的电热分析则是目前研究的热点问题.针对电热分析方程所具有的大规模稀疏(电导或热导)系数矩阵,根据该系数矩阵所具有的对称正定严格对角占优等特性,本文从理论上证明了电热分析具有局部性,在相同的截断误差限松弛结束条件下,局部松弛和全局松弛具有相同的松弛精度.基于局部松弛理论,本文提出了一个高效实用的局部过松弛(SOR)算法(LSOR2),并在文章最后将其用于如下的3个具体的电热分析问题研究:(1)P/G网中的过压降点电压变化统计分析;(2)3D热分析中的过热点温度变化统计分析;(3)单开路故障下的P/G网快速分析.实验数据表明:与全局SOR算法相比,在保证精度的前提下,LSOR2算法可以将电热分析的求解速度提高1-2个数量级.     

Optimization under uncertainty with applications to design of truss structures

Many real-world engineering design problems are naturally cast in the form of optimization programs with uncertainty-contaminated data. In this context, a reliable design must be able to cope in some way with the presence of uncertainty. In this paper, we consider two standard philosophies for finding optimal solutions for uncertain convex optimization problems. In the first approach, classical in the stochastic optimization literature, the optimal design should minimize the expected value of the objective function with respect to uncertainty (average approach), while in the second one it should minimize the worst-case objective (worst-case or min–max approach). Both approaches are briefly reviewed in this paper and are shown to lead to exact and numerically efficient solution schemes when the uncertainty enters the data in simple form. For general uncertainty dependence however, the problems are numerically hard. In this paper, we present two techniques based on uncertainty randomization that permit to solve efficiently some suitable probabilistic relaxation of the indicated problems, with full generality with respect to the way in which the uncertainty enters the problem data. In the specific context of truss topology design, uncertainty in the problem arises, for instance, from imprecise knowledge of material characteristics and/or loading configurations. In this paper, we show how reliable structural design can be obtained using the proposed techniques based on the interplay of convex optimization and randomization.     

Development of a compact displacement accumulation actuator device for both large force and large displacement

The design, fabrication, and testing of a compact displacement accumulation device is presented in this paper. The piezoelectric device provides both large displacement (mm) and large force (100 N). The device is based on conventional inchworm motor design that produces large displacement. The device integrates piezoelectric stacks for large force output and high-speed operation with MEMS ridges as a new clamping system. The device should be able to push and pull 450 N at 11 mm/s in a relatively compact size. FEM analysis is used for the design, EDM is used for the fabrication of a prototype, and conventional test techniques are used to evaluate performance. Stress and modal analysis are used to confirm that the device has an infinite fatigue life and a first modal frequency at 1309 Hz. Experimental data for clamping strength of the ridges and blocking force of the device validate that the device transfers the required load of 450 N. The device is successfully tested over a wide range of operating conditions at speeds up to 11 mm/s using open loop control. The stall load of the device is measured to be exceeding 2250 N. For the dynamic loading test, the device pushes test weights up to 50 N with the open loop control approach.     

Task mapping and flow priority assignment of real-time industrial applications for network-on-chip based design

Network-on-chip (NoC) is a paradigm shift for communication between cores in multi-processor systems. It has emerged as a solution for addressing the limitations of bus-based communication in multi-processor system design. The use of MPSoC (Multi-Processor System on Chip) based design of real-time safety-critical embedded systems (such as, Avionics, Automotive etc.) is really a challenge because of the requirement of time predictability and reliability of highest degree. Task mapping and flow priority assignment are two crucial steps for real-time NoC design. Most of the earlier work on priority assignment for on-chip communications are either based on exhaustive search or are heuristic in nature.In this paper, a search based explorative solution to the priority assignment problem has been proposed with a Genetic Algorithm (GA) based formulation that uses experimentally determined heuristics to converge faster with a better solution. Unlike other works in the area, proposed work considers the task execution time while assigning flow priorities. The paper proposes a combined priority assignment and task mapping solution. The approach has been validated with two real-time industrial applications - one from automotive domain, while the other one is from avionics.     

电容式微超声传感器的电极参数优化设计

建立了电容式微超声传感器(cMUT)的有限元模型,通过对模型进行静电-结构耦合仿真分析,研究了金属电极的结构参数包括电极面积、电极厚度、电极材料以及电极相对与薄膜的位置等参数的变化对传感器性能的影响.分析了电极参数与传感器吸合电压,静态电容,机电转换比以及机电耦合系数的关系,最后得到了优化的电极结构参数,即金属电极面积为传感器振动薄膜面积的一半时,传感器具有较低的吸合电压和较大带宽值及机电耦合系数.     

An improved direct labeling method for the max–flow min–cut computation in large hypergraphs and applications

Algorithms described so far to solve the maximum flow problem on hypergraphs first necessitate the transformation of these hypergraphs into directed graphs. The resulting maximum flow problem is then solved by standard algorithms. This paper describes a new method that solves the maximum flow problem directly on hypergraphs, leading to both reduced run time and lower memory requirements. We compare our approach with a state–of–the–art algorithm that uses a transformation of the hypergraph into a directed graph and an augmenting path algorithm to compute the maximum flow on this directed graph: the run–time complexity as well as the memory space complexity are reduced by a constant factor. Experimental results on large hypergraphs from VLSI applications show that the run time is reduced, on average, by a factor approximately 2, while memory occupation is reduced, on average, by a factor of 10. This improvement is particularly interesting for very large instances, to be solved in practical applications.