Behavioral modeling phase-locked loops for mixed-mode simulation

Phase-locked Loops(PLLs) are a class of feedback systems with wide range of applications. A PLL in its entirety can be viewed as a closed-loop servosystem, comprised of three major functional subsystems; 1) Phase detectors, 2) Loop filters and 3) Voltage/Current controlled oscillators. The overall characteristics of the phase-locked loop are dependent on the realization of individual subsystems which have mixed analog-digital implementations. In simulating a PLL, one has to deal with the mixed-signal nature of most implementations, as well as the problem of simulating the PLL over a large number of signal cycles. Long simulation run times plague the simulation of a PLL using a conventional simulator, sometimes making such simulation impractical. In the methodology described in this paper, these drawbacks are overcome by the use of behavioral models and a mixed-signal simulation platform. This paper presents a general mixed-mode behavioral simulation methodology and the derivation of behavioral simulation models for various kinds of PLLs. The top-down and bottom-up modeling paradigms are illustrated through the use of examples of actual PLL designs. The simulation models are generated for the AT&T Bell Laboratories mixed analog-digital simulator, ATTSIM.     

Fully coupled electrothermal mixed-mode device simulation of SiGeHBT circuits

It is well known that for the design and simulation of state-of-the-art circuits thermal effects like self-heating and coupling between individual devices must be taken into account. As compact models for modern or experimental devices are not readily available, a mixed-mode device simulator capable of thermal simulation is a valuable source of information, Considering self-heating and coupling effects results in a very complex equation system which can only be solved using sophisticated techniques. We present a fully coupled electrothermal mixed-mode simulation of an SiGe HBT circuit using the design of the μA709 operational amplifier. By investigating the influence of self-heating effects on the device behavior we demonstrate that the consideration of a simple power dissipation model instead of the lattice heat flow equation is a very good approximation of the more computation time consuming solution of the lattice heat flow equation     

Computer program to obtain the time response of sampled-data systems

A program is described which gives the sampled time response corresponding to any rational function F(z) expressed as the ratio of two polynomials.     

A novel mixed-mode current-conveyor-based filter

A new mixed-mode biquad circuit is presented. The circuit uses six single-output plus-type second-generation current-conveyors (CCII+s), a single dual-output CCII+, two grounded capacitors, eight resistors, at least two of them permanently grounded, and can realize lowpass, highpass, bandpass, notch, lowpass notch, highpass notch and allpass responses from the same topology. The circuit can be driven by voltage or current and its output can be voltage or current. The parameters ω₀ and ω₀/Q ₀ enjoy independent electronic tunability. Simulation results are included.     

Addressing substrate coupling in mixed-mode ICs: simulation andpower distribution synthesis

This paper describes new techniques for the simulation and power distribution synthesis of mixed analog/digital integrated circuits considering the parasitic coupling of noise through the common substrate. By spatially discretizing a simplified form of Maxwell's equations, a three-dimensional linear mesh model of the substrate is developed. For simulation, a macromodel of the fine substrate mesh is formulated and a modified version of SPICE3 is used to simulate the electrical circuit coupled with the macromodel. For synthesis, a coarse substrate mesh, and interconnect models are used to couple linear macromodels of circuit functional blocks. Asymptotic Waveform Evaluation (AWE) is used to evaluate the electrical behavior of the network at every iteration in the synthesis process. Macromodel simulations are significantly faster than device level simulations and compare accurately to measured results. Synthesis results demonstrate the critical need to constrain substrate noise and simultaneously optimize power bus geometry and pad assignment to meet performance targets     

A novel mixed-mode OTA-C universal filter

A novel mixed-mode biquad circuit is presented. The circuit uses six single-output- and one dual-output-operational transconductance amplifiers, two grounded capacitors; and can realize lowpass, highpass, bandpass, notch, lowpass-notch, highpass-notch and allpass responses from the same topology. The circuit can be driven by voltage or current and its output can be voltage or current. The parameters ω_o and ω_o/Q _o enjoy independent electronic tunability. Simulation results are included.     

SENSIM: A simulation program for solid-state pressure sensors

A simulation program is described which is capable of calculating the output response of silicon piezoresistive or capacitive pressure sensors as a function of both pressure and temperature. A thermoelastic plane-stress formulation is used in calculating the stress and deflection of the transducer diaphragm. Both analytical and finite-difference solution methods are available, depending on the sensor structure. Diaphragm thickness taper, oxide and package stress, and rim effects are simulated. For capacitive structures, the program accurately predicts the diaphragm deflection and pressure sensitivity as a function of pressure and temperature. Stepped diaphragm structures are shown to be capable of improving pressure sensitivity by as much as 50 percent. The package-induced thermal drift for electrostatically sealed glass-silicon devices is typically less than 0.05 mmHg/°C.     

A comprehensive two-dimensional VLSI process simulation program, BICEPS

Bell Integrated Circuit Engineering Process Simulator (BICEPS) is a comprehensive VLSI process-simulation program developed at Bell Laboratories. BICEPS incorporates the most up-to-date physical models and efficient numerical algorithms to make it a highly robust and general-purpose program. BICEPS can calculate doping profiles resulting from ion implantation, predeposition, oxidation, and epitaxy in one or two spatial dimensions as well as etching and deposition of oxide, nitride, and photoresist. In this paper, the physics of IC process simulation will be reviewed with an emphasis on the various physical models implemented in BICEPS. Calculation of the impurity profiles in VLSI devices involves the solution of a coupled set of nonlinear time-dependent partial differential equations, with moving boundaries and in more than one spatial dimension. The numerical techniques in obtaining a solution to this problem, namely, spatial discretization, time discretization, and the treatment of moving boundaries are also described in this paper. The capabilities of BICEPS are illustrated by the results of simulation of the fabrication of a typical NMOS transistor.     

一种新型智能化变电站二次系统仿真测试方案

随着我国电力技术的快速发展,智能化变电站已成为变电站的发展趋势。但是现有智能化变电站二次系统联调测试周期较长,调试设备和涉及环节较多,工作复杂,对智能化变电站工程的建设效率造成了严重的影响。针对这种情况,文中提出了一种新型的智能化变电站二次设备仿真测试方案,首先分析了系统整体架构;其次,利用等效仿真和仿真测试技术手段,进行了智能化变电站二次设备仿真测试,并且探讨了智能化变电站二次系统仿真测试方案的关键性技术。测试结果证明:该智能化变电站二次系统仿真测试方案完全能够达到保护装置测试要求及预期测试要求,大大地提高了测试效率。     

A mixed-mode ESD protection circuit simulation-design methodology

On-chip electrostatic discharge (ESD) protection design becomes a major design challenge as IC technologies continue to migrate into very-deep-submicron (VDSM) regime. However, trial-and-error approaches still dominate in ESD protection circuit design. This paper discusses a new mixed-mode ESD protection simulation-design methodology, aiming to design prediction, which involves multiple-level coupling in ESD protection simulation by solving complex electrothermal equations self-consistently at process, device, and circuit levels in a coupled fashion to investigate ESD protection circuit details without any pre-assumption. Practical ESD protection design examples, implemented in commercial 0.18/0.35-/spl mu/m CMOS and BiCMOS processes, are presented.     

基于HLA的仿真程序设计研究

在分布式交互仿真中,高层体系结构HLA以其灵活性、开放性和突出的互操作和重用性成为当今的分布式交互仿真的标准IEEE1516。研究基于HLA的程序设计方法对于开发分布式交互仿真系统具有重要意义。本文从HLA的对象模型模板(OMT)和接口规范实现的运行支撑环境(RTI)所提供的6种服务入手,结合相应设计实例,给出了设计的步骤和一般方法。     

A low-jitter mixed-mode DLL for high-speed DRAM applications

This paper presents a salient clock deskewing method with a mixed-mode delay-locked loop (MDLL) for high-speed synchronous DRAM applications. The presented method not only solves the resolution problem of conventional digital deskewing circuits, but also improves the jitter performance to the level of well-designed analog deskewing circuits, while keeping the power consumption and locking speed of digital deskewing circuits. The whole deskewing circuit is fabricated in a 3.3-V 0.6-μm triple-metal CMOS process and occupies a die area of 0.45 mm². Measured rms jitter is 6.38 ps. The power consumption of the entire chip, including I/O peripherals, is 33 mW at 200 MHz with a 3.3-V supply     

A mixed-mode polynomial cellular array processor hardware realization

A mixed-mode cellular array processor is presented in which the processing units (PUs) are coupled with programmable polynomial (linear, quadratic, and cubic) first neighborhood feedback terms. It combines analog and digital processing so that the couplings and the polynomial terms are implemented with analog blocks whereas the integrator is digital, and analog-to-digital and digital-to-analog converters are used to interface between them. A 10-mm/sup 2/, 1.027 million transistor cellular array processor with 2/spl times/72 PUs and 36 layers of memory in each was manufactured using a 0.25-/spl mu/m digital CMOS process. The array processor can perform gray scale Heun's integration of spatial convolutions with linear, quadratic, and cubic activation functions for a 72/spl times/72 data while keeping all input-output operations during processing local. One complete Heun's iteration round takes 166.4 /spl mu/s and the power consumption during processing is 192 mW. Experimental results of statistical variations in the multipliers and polynomial circuits are shown.     

SuperNEC: antenna and indoor-propagation simulation program

SuperNEC is a hybrid MoM-UTD antenna and electromagnetic simulation program, developed by Poynting Software (Pty) Ltd. The UTD primitives available in the code are dielectrically coated, multi-faceted plates and elliptical cylinders. The MoM primitives supported are wire segments. The program is capable of running in parallel on a heterogeneous network of processors. A Matlab-based, interactive graphical user interface is used to define the geometry to be simulated, as well as to view the simulation results. The program has been extensively verified using a multitude of test cases, which include comparison to published results and measurements     

The TNS program: A computer simulation package for the intelsat TDMA network

The TNS (TDMA Network Simulation) program is a computer simulation package developed for the evaluation, test and analysis of all the protocols in the INTELSAT TDMA network. The TNS program faithfully simulates the dynamic operation of the network, taking account of the satellite motion, and makes it even possible to simulate the network operation under some abnormal conditions, such as terminal function failure and transponder failure. This paper describes the TNS program in terms of its design approach, its capabilities, its structure, its input and output data, and its operation. An example simulation for the whole system start-up procedure assuming the Atlantic Ocean region is also presented.     

Time-optimal control of sampled-data systems

The matrix pseudoinverse is used to obtain a minimum-time control law for a general nth-order linear time-invariant completely state-controllable sampled-data system with r inputs. The control law is unique only in certain special cases. In the general case several time-optimal control sequences may exist; the particular control law obtained is shown to require minimum energy.     

鼠笼电机程控混合模型仿真研究

磁链观测是矢量控制中的一个关键任务,电流模型在转速较低时比较精确,电压模型在转速较高时比较精确。结合两种模型使其依靠程序自动切换,在转速较低时使用电流模型,在转速较高时采用电压模型,可以对磁链进行准确的观测。以Matlab/Simulink为工具,采用程控自动切换混合模型对异步电机矢量控制算法进行了仿真。仿真结果验证了程控自动切换的可行性和矢量控制调速的动态响应快、硬特性强、稳态脉动小的良好性能。     

A behavioral model of A/D converters using a mixed-mode simulator

A mixed-mode behavioral model of analog-to-digital (A/D) converters is described. A generalized model structure is introduced. The basic function of an A/D converter is to convert an analog voltage into a digital code, for example, a binary number. Three conversion methods (successive approximation, flash, and dual integration) which are commonly used in A/D converters are modeled and can be selected simply by specifying a parameter of the model. For brevity, only the successive-approximation method is described. The modeling considerations of various parts in the A/D converter, including the input amplifier, D/A converter, comparator, and the synchronization problem, are described. The model has been implemented in the Saber mixed-mode simulator. Simulation results are given     

A fast-lock mixed-mode DLL using a 2-b SAR algorithm

In this paper, a fast-lock mixed-mode delay-locked loop (MMDLL) is presented. The digital part of the MMDLL utilizes a 2-b SAR algorithm to achieve short lock time compared to the conventional RDLL, CDLL, and SARDLL, while the analog part helps to reduce the residue phase error introduced by the digital part and improve the output jitter performance. The measured RMS and peak-to-peak jitters and the static phase error are 6.6, 47, and 12.4 ps, respectively, for a 100-MHz input clock. The power consumption is 15.8 mW in the locked state at a 2.7-V supply voltage. The maximum lock time is 13.5 clock cycles (135 ns) when the residue phase error is within 1 LSB (156 ps)