首页 | 本学科首页   官方微博 | 高级检索  
相似文献
 共查询到20条相似文献,搜索用时 31 毫秒
1.
Despite the progress made in digital signal processing during the last decades, the constraints imposed by high data rate communications are becoming ever more stringent. Moreover mobile communications raised the importance of power consumption for sophisticated algorithms, such as channel equalization or decoding. The strong link existing between computational speed and power consumption suggests an investigation of signal processing with energy efficiency as a prominent design choice. In this work we revisit the topic of signal processing with analog circuits and its potential to increase the energy efficiency. Channel equalization is chosen as an application of nonlinear signal processing, and a vector equalizer based on a recurrent neural network structure is taken as an example to demonstrate what can be achieved with state of the art in VLSI design. We provide an analysis of the equalizer, including the analog circuit design, system-level simulations, and comparisons with the theoretical algorithm. First measurements of our analog VLSI circuit confirm the possibility to achieve an energy requirement of a few pJ/bit, which is an improvement factor of three to four orders of magnitude compared with today’s most energy efficient digital circuits.  相似文献   

2.
Design techniques for low-power, nondigital nonmicrowave circuits are presented. The major objectives in improving analog CAD are described. The current status of CAD for analog circuits is discussed, and interesting trends are examined. An approach to CAD-compatible analog design is discussed. These designs also apply to mixed analog/digital VLSI design environments, particularly to circuits used in signal processing  相似文献   

3.
A new realization for adaptive signal processing units is proposed which uses a special subset of signed-digit number representations (SDNRs). This signed binary number representation (SBNR) captures all of the efficiencies of SDNR arithmetic and, in addition makes circuit realizations less complex. Furthermore, a natural interface between analog and digital numbers is provided. The serial online processing nature of SBNR utilizes the MSB first. An area/time complexity for VLSI implementations in comparable systolic array architectures contrasts the effectiveness of five different primitive VLSI cells and organizations.  相似文献   

4.
A new technique for the design of analog VLSI is described. Borrowing from digital design technology concepts, an analog processor is described which can be digitally programmed to execute a small but powerful set of analog operations. At a very high level of abstraction these instructions can be used to perform mathematical processing on analog signals directly rather than through the traditional processing chain of sampling, A/D conversion, digital processing, and D/A conversion. A key feature of the technique is the conversion of signals into logarithmic form, and the practical problems associated with this are discussed and their solutions outlined. Finally implementation of these techniques in BiCMOS, CMOS, and bipolar technologies is discussed with conclusions.  相似文献   

5.
A new technique for the design of analog VLSI is described. Borrowing from digital design technology concepts, an analog processor is described which can be digitally programmed to execute a small but powerful set of analog operations. At a very high level of abstraction these instructions can be used to perform mathematical processing on analog signals directly rather than through the traditional processing chain of sampling, A/D conversion, digital processing, and D/A conversion. A key feature of the technique is the conversion of signals into logarithmic form, and the practical problems associated with this are discussed and their solutions outlined. Finally implementation of these techniques in BiCMOS, CMOS, and bipolar technologies is discussed with conclusions.  相似文献   

6.
模拟VLSI电路故障诊断的相关分析法   总被引:1,自引:0,他引:1  
谢永乐 《半导体学报》2007,28(12):1999-2005
为了提高模拟VLSI电路的测试精度,提出了一种基于数字信号处理的模拟VLSI电路测试方法,将测试响应经余弦调制实现的数字滤波器组完成子带滤波,随后对各子带滤波序列进行能量计算和相关分析,实现模拟响应的数字特征提取,对国际标准电路中的19个故障的实验表明:子带滤波序列的能量计算适合诊断硬故障; 相关分析既可诊断硬故障,又可诊断软故障,实验还表明该方法对故障的分辨率远高于文献[7]。  相似文献   

7.
Smith  S.G. 《Electronics letters》1986,22(14):750-752
A class of serial/parallel architectures for inner-product computation is described, based on carry-save accumulator arrays. In their basic form such arrays form carry-save multiply/adders. A simple modification of the coefficient feed allows flexible extension to short vector inner-product computation using distributed arithmetic. These modules may be cascaded to handle longer vectors, forming high-level VLSI digital signal processing subsystems.  相似文献   

8.
This paper relates theoretical investigations in digital signal processing (DSP) to the design of a VLSI digital filter bank (DFB). Emphasis is on a top-down approach to identify multilevel parallelisms inherent in a generic DSP algorithm and a new VLSI architecture. System level control and communication requirements are examined. Finite word length effects on filter accuracy are identified. The complexity of filter modules is reduced by partitioning large filter functions into a sum of smaller subfunctions. A memory intensive architecture minimizes design time. Up to 100 DRF modules are configured in parallel to perform signal processing up to 20 MHz. This VLSI DFB out performs sequential von Neumann architectures by several orders of magnitude using the same level of VLSI technology.  相似文献   

9.
Combining the Residue Number System as a computational tool and VLSI as a fabrication medium promises to provide modular and cost efficient implementation of many digital signal processing algorithms. In this paper, a memory model has been developed. It is a low level model, which is used to derive relationships between the size of each modulus (in the chosen number system), and both chip area and time required for implementing the corresponding look-up tables. The memory model allows the selection of the most efficient layout for memories which do not have power of two dimensions. A set of multi-look-up table modules has been proposed as building block units for implementing digital signal processing algorithms. A procedure has been developed to optimize the area and time of those modules.  相似文献   

10.
In this work a test strategy for analog circuits based on spectral analysis is proposed. The test strategy is blind, in the sense that only statistical information about the input signal is needed, but no sampling of the input signal is required. This feature allows the test of analog circuits with minimum analog hardware addition. In the context of Systems-on-Chip, this strategy needs only the inclusion of a small random signal generator, and transfers most of the signal processing to the digital domain, allowing the use of a purely digital tester or a digital BIST technique. This paper presents the underlying principle of the method and experimental test results for linear analog systems.  相似文献   

11.
Digital radio transmission systems use complex modulation schemes that require powerful signal processing techniques to correct channel distortions and to minimize bit-error rates (BERs). Combined analog and digital processors are investigated for minimizing the mean square error (MSE) of the radio receiver. The analog filters are implemented using acousto-optic (AO) processing since rapidly adaptable, inverse channel filters can be produced for either minimum or nonminimum phase channels. A specific architecture is identified and a laboratory system is tested to verify the ability of the processor to track and correct time-varying channels. Computer simulations are used to show that hybrid analog and digital equalization allows an increase in the modulation capacity of radio, relative to all digital equalization, while maintaining similar equipment signatures  相似文献   

12.
We investigate the estimation of fault probabilities and yield for very large scale integration (VLSI) implementations of neural computational models. Our analysis is limited to structures that can be mapped directly onto silicon as truly distributed parallel processing systems. Our work improves on the framework suggested by Feltham and Maly and is also applicable to analog or mixed analog/digital VLSI systems  相似文献   

13.
A wide-band, fast settling CMOS complementary folded cascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder cascode (FC) or mirrored cascode (MC) approaches for VLSI amplifiers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm2), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a DC gain of approximately 50 dB, with a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF  相似文献   

14.
A technique is presented for deriving all of the different control signals needed for focusing and radial tracking in a digital servosystem for compact disc (CD) players, as well as the full band data from the disc. Because of the different natures of all those signals, different bandwidth and dynamic range, complex analog anti-aliasing circuits, and several types of A/D (analog-to-digital) converters would normally be required to convert the signals from the analog to digital domain. With the proposed technique it is possible to carry out the conversion of the high-frequency data as well as the low-frequency control signals with only a single type of multibit sigma-delta (ΣΔ) A/D converter in combination with digital signal processing. The use of ΣΔ type A/D conversion also has other advantages such as its suitability for integration in a CMOS VLSI process and the fact that the requirements for the anti-aliasing filters in front of the converters are relaxed due to the oversampling technique  相似文献   

15.
In this article, recent research activities on the development of electronic neural networks in Japan are reviewed. Most of the largest Japanese electronic companies have developed VLSI neural chips using analog, digital or optoelectronic circuits. They have run various neural networks on them. Recently, in Japan, digital approach becomes active. Several fully-digital VLSI chips for on-chip BP learning have been developed, and 2.3 GCUPS (Giga Connection Updates per Second) learning speed has already been attained. Although the numbers of neurons and synapses containable in single digital chips are small, a large neural network can be developed by cascading the chips. By cascading 72 chips, a fully interconnected PDM (Pulse Density Modulating) digital neural network system has been developed. The behavior of the system follows simultaneous nonlinear differential equations and the processing speed amounts to 12 GCPS (Giga Connections per Second).Intensive researches on analog and optoelectronic approaches have also been carried out in Japan. An analog VLSI neural chip attains 28 GCUPS on-chip learning speed and 1 TCPS (Tera Connections per Second) processing speed for Boltzmann machine with 1 bit digital output. For the optoelectronic approach, although the network size is small, 640 MCUPS BP learning speed has been attained.  相似文献   

16.
A forecast of the practical and promising devices, circuits, and systems that can be expected in the next one to five years is presented. It is based on a survey of a group of distinguished practitioners throughout the industry. The forecasts cover the areas of lasers and electrooptics, integrated optoelectronics, electron devices, digital integrated circuits, high-frequency and microwave devices, VLSI signal and image processing systems, analog ICs and signal processing, power electronics and systems, neural systems and applications, and medical image and signal processing. A particularly optimistic outlook is seen for lasers, fiber optics, optoelectronic ICs, and optical switching and processing. Digital ICs and power electronics are also expected to make steady gains. In addition, flat panel displays will attract a fair amount of activity, with the liquid-crystal and electroluminescent types emerging as the leaders in this decade. Looking further out, advances in artificial and biological neural systems represents a natural extension to more sophisticated problem-solving in speech processing, vision and communications  相似文献   

17.
This paper reviews the problem of translating signals into symbols preserving maximally the information contained in the signal time structure. In this context, we motivate the use of nonconvergent dynamics for the signal to symbol translator. We then describe a biologically realistic model of the olfactory system proposed by W. Freeman (1975) that has locally stable dynamics but is globally chaotic. We show how we can discretize Freeman's model using digital signal processing techniques, providing an alternative to the more conventional Runge-Kutta integration. This analysis leads to a direct mixed-signal (analog amplitude/discrete time) implementation of the dynamical building block that simplifies the implementation of the interconnect. We present results of simulations and measurements obtained from a fabricated analog VLSI chip  相似文献   

18.
Advanced digital receiver principles and technologies for PCS   总被引:1,自引:0,他引:1  
The synergy between digital radio communications and VLSI signal processing is revolutionizing the design of wireless terminals. Driving this synergy are certain fundamental paradigms in modern communication theory, digital signal processing, and VLSI design. The authors discuss the modern centers-of-gravity model, which they believe is emerging as the basis for the successful design and implementation of advanced digital communication systems. Central to this model are design principles that enable engineers to systematically derive digital receiver structures and explore algorithm and architecture trade-offs using sophisticated tools. Digital signal processing technology is critical in the implementation of these digital receiver structures efficiently. Finally, CAD tools for digital communications system design and design space exploration are shown to be of crucial importance in the efficient execution of these designs  相似文献   

19.
Computationally very expensive dynamic-programming matching of data sequences has been directly implemented in a fully-parallel-architecture VLSI chip. The circuit operates as digital logic in the signal domain, while analog processing is carried out in the time domain based on the delay-encoding-logic scheme. As a result, a high-speed low-power best-match-sequence search has been established with a small chip area. The typical matching time of 80 ns with the power dissipation of 2 mW has been demonstrated with fabricated prototype chips.  相似文献   

20.
Artificial neural network chips can achieve high-speed performance in solving complex computational problems for signal and information processing applications. These chips contain regular circuit units such as synapse matrices that interconnect linear arrays of input and output neurons. The neurons and synapses may be implemented in an analog or digital design style. Although the neural processing has some degree of fault tolerance, a significant percentage of processing defects can result in catastrophic failure of the neural network processors. Systematic testing of these arrays of circuitry is of great importance in order to assure the quality and reliability of VLSI neural network processor chips. The proposed testing method consists of parametric test and behavioral test. Two programmable analog neural chips have been designed and fabricated. The systematic approach used to test the chips is described, and measurement results on parametric test are presented.This research was partially supported by DARPA under Contract MDA 972-90-C-0037 and by National Science Foundation under Grant MIP-8904172.  相似文献   

设为首页 | 免责声明 | 关于勤云 | 加入收藏

Copyright©北京勤云科技发展有限公司  京ICP备09084417号