Atom Electronics: A proposal of nano-scale devices based on atom/molecule switching

This paper describes the possibility of atom/molecule switching devices, which are candidates to supersede the present metal-oxide-semiconductor (MOS) devices and to establish the new era of Atom Electronics. They are Atom Relay Transistors (ART) and Molecular Single Electron Switching (MOSES) devices, with total dimensions of a few nm and an operation speed of more than Tera (10¹²) Hz. Using these devices, it is estimated that a supercomputer, with 10⁷ gates of logic circuit and 10⁹ bits of memory, would be integrated in an area 200 μm square and operating at more than Tera (10¹²) Hz. ART and MOSES devices are evaluated on the basis of the characteristics necessary for information processing integrated circuit devices, together with other nano scale devices, and are found to be the most promising candidates that supersede the present metal oxide semiconductor (MOS) devices for information processing in the next decade. This paper also describes several technologies which could contribute to the establishment of Atom Electronics, including beam assisted scanning tunneling microscope (BASTM) which makes it possible to observe insulator surfaces, micromachine scanning tunneling microscope (μ-STM) by which the vacuum tunneling gap is successfully observed and the Needle Formation and Tip Imaging (NFTI) method which makes possible the in-situ evaluation of the tip apex of an STM.     

Monitoring of low-dose ion implantation in silicon

Monitoring of low-dose arsenic or boron ion implantation (doses: 5×10¹⁰ to 1×10¹³ cm^-2) in silicon, which is required for threshold voltage control of MOS transistors, is studied. The thermal-wave (TW) signal intensity decreases monotonically with decreasing dose. The lowest detection limit for As⁺ and B⁺ implantations is 5×10¹⁰ and 1×10¹¹ cm^-2, respectively. Correlation of the TW signal intensity versus damage density, TW intensity versus dose, and laser Raman intensity versus dose is obtained. The TW intensity is also correlated with the sheet conductance, and the threshold voltage of the transistor. Therefore, this technique is useful as a nondestructive, highly sensitive dose monitor for low-dose implantation to achieve tight threshold voltage control in MOS transistors     

Device characterization on monocrystalline silicon grown over SiO2by the ELO (epitaxial lateral overgrowth) process

MOS and lateral bipolar transistors have been fabricated on epitaxial silicon layers which have been laterally overgrown over SiO2. These device characteristics were than compared to those measured on devices fabricated on homoepitaxial silicon and bulk silicon. The measurements indicate essentially identical MOS device characteristics for all three materials with a typical hole field effect mobility of about 180 cm²/vs. Lifetime measurements using pulsed C-V techniques showed essentially the same values for ELO material and homoepitaxial material with the ELO value being about 20 µS for 10¹⁵cm^-3doping level. These lifetime values correlate will with diode and bipolar transistor measurements.     

A 2-GHz low-phase-noise integrated LC-VCO set with flicker-noiseupconversion minimization

A fully integrated 2-GHz very low-phase-noise LC-tank voltage-controlled oscillator (VCO) set with flicker noise upconversion minimization is presented. Using only integrated planar inductors, the measured phase noise is as low as -125.1 dBc/Hz at 600-kHz offset and -138 dBc/Hz at 3 MHz. The excellent phase-noise performance is achieved by means of an in-house-developed integrated inductor simulator optimizer. To minimize the upconversion of flicker noise to 1/f³ phase noise, a flicker-noise upconversion factor is defined, which can easily be extracted from circuit simulation. The technique is applied to demonstrate the relationship between the flicker-noise upconversion and the overdrive level of the oscillators' MOS cross-coupled pair and to develop circuit balancing techniques to even further reduce the flicker-noise upconversion. The 1/f³ phase-noise corner is minimized to be less than 15 kHz. The VCO's are implemented in a three-metal layer, 0.65-μm BiCMOS process, using only MOS active devices     

High-sensitivity capacitive sensing interfacing circuit for monolithic CMOS M/NEMS resonators

A simple and high-sensitivity 0.35 mum CMOS readout circuit for resonant M/NEMS with capacitive sensing is presented. The proposed readout scheme presents an equivalent transimpedance gain of 140 dB Omega (at 1 MHz) and an input referred noise of 29 nV/Hz^1/2. Detection of submicrometre-scale cantilever vibrations in the MHz range is demonstrated with a displacement resolution of 33 ffn/Hz^1/2.     

Monolithic CMOS MEMS Oscillator Circuit for Sensing in the Attogram Range

This letter presents the design, fabrication, and demonstration of a CMOS/microelectromechanical system (MEMS) electrostatically self-excited resonator based on a submicrometer-scale cantilever with ~1 ag/Hz mass sensitivity. The mechanical resonator is the frequency-determining element of an oscillator circuit monolithically integrated and implemented in a commercial 0.35 mum CMOS process. The oscillator is based on a Pierce topology adapted for the MEMS resonator that presents a mechanical resonance frequency of ~6 MHz, a relative low quality factor of 100, and a large motional resistance of ~25 M. The MEMS oscillator has a frequency stability of ~1.6 Hz resulting in a mass resolution of ~1 ag (1 ag = 10^-18 g in air conditions.     

Room temperature single electron effects in a Si nano-crystalmemory

An MOS memory based on Si nano-crystals has been fabricated. We have developed a repeatable process of forming uniform, small-size and high-density Si nano-crystals and spherical nano-crystals of about 4.5 nm in diameter with density of 5×10¹¹/cm² were obtained. Threshold voltage shift of 0.48 V corresponding to single electron storage in individual nano-crystals is obtained. For the first time, room temperature single electron effects are observed. These prove the feasibility of practical Si nano-crystal memory     

All-MOS voltage-to-current converter

A new resistorless voltage-to-current converter utilizing only MOS transistors to achieve voltage-to-current conversion with less than ±0.5% nonlinearity is described. The circuit uses MOS transistors in linear and saturation regions to produce an output current linearly related to the input voltage. The output current is proportional to the carrier mobility tracking the process variations. This circuit is suitable for submicron technologies where the availability of a linear resistor with moderate sheet resistance is not guaranteed. The circuit is fabricated using 0.6-μm n-well CMOS technology, consumes less than 200 μA, and occupies 200 mm² of area     

MOS and bipolar VLSI technologies using electron-beam lithography

Key issues for micrometer and submicrometer MOS and bipolar device fabrication are discussed, including lithography, device and circuit scaling limitations, and process considerations. Lithographic requirements are presented in terms of an overall technology-machine, resist and pattern transfer methods-and an electron-beam alice writing technology is described which satisfies those needs. Viable micrometer and submicrometer MOS and bipolar process technologies are demonstrated by scaling complex LSI circuits to VLSI density using electron lithography. For the MOS case, scaling of static memories is discussed in detail, including fabrication of a 4K SRAM with 1.5-µm minimum feature sizes, 12-15-ns access times, and a chip size of only 6K mil². A discussion of bipolar device and process scaling issues is highlighted by the successful fabrication of a scaled 16-bit integrated injection logic (I²L) microprocessor with 1.25-µm minimum feature sizes and a clock frequency of 10 MHz with a chip current of only 250 mA.     

An inherently linear and compact MOST-only current divisiontechnique

A technique is presented for dividing currents accurately and linearly by using MOS transistors only. This technique is valid in all operating regions of an MOS transistor. With this technique, a volume control circuit is realized with an attenuation of 0 to -84 dB in steps of 2 dB. The measured THD is better than -85 dB and the dynamic range is better than 100 dB. The chip is realized in a standard digital CMOS process and chip area is 0.22 mm²     

Low-power bandgap references featuring DTMOSTs

This paper describes two CMOS bandgap reference circuits featuring dynamic-threshold MOS transistors. The first bandgap reference circuit aims at application in low-voltage, low-power ICs that tolerate medium accuracy. The circuit runs at supply voltages down to 0.85 V while consuming only 1 μW; the die area is 0.063 mm² in a standard digital 0.35-μm CMOS process. The second bandgap reference circuit aims at high accuracy operation (σ=0.3%) without trimming. It consumes approximately 5 μW from a 1.8-V supply voltage and occupies 0.06 mm² in a standard 0.35-μm CMOS process     

一种驱动MOS管工作在饱和区的硅基OLED微显示像素电路

硅基OLED微显示中为了在极小的像素面积内实现微小的OLED工作电流,其像素驱动电路的驱动MOS管一般工作在亚阈值区,存在OLED电流对驱动MOS管的阈值电压和栅源电压失配敏感、外围电路复杂等问题,如果驱动MOS管工作在饱和区则可避免这些问题,但为了获得微小的驱动电流,必须采用尺寸大的倒比MOS管,这又与极小的像素面积冲突。本文提出了一种采用脉宽调制(PWM)技术、驱动MOS管工作在饱和区的OLED微显示像素驱动电路,PWM信号减少了一帧内OLED的实际工作时间,OLED的脉冲电流变大,使驱动MOS倒比管的尺寸减小;由于PWM信号占空比小,同时实现了OLED微小的平均像素驱动电流和亮度。结果表明PWM信号占空比为3%时,实现的OLED驱动电流和像素亮度范围分别为27pA~2.635nA、2.19~225.1cd/m~2,同时采用双像素版图共用技术,在15μm×15μm的像素面积内实现了像素驱动电路的版图设计。     

LASOS—laser annealed silicon on sapphire

Laser annealing techniques were successfully incorporated into standard MOS/SOS processing to increase transistor channel mobility and processing yield. Silicon islands were photolithographically defined and chemically etched (by KOH) on standard SOS wafers. The islands were exposed to radiation from an excimer laser (λ = 2490 Å) having a pulse duration of 25 ns, a beam size in the range of 0.1-0.2 cm², and an energy density in the range of 0.5 - 1.0 J/cm². Using standard processing techniques MOS transistors were fabricated and characterized. It was found that exposure at an energy density of ∼0.80 J/cm²results in rounding the Si island edges, thus eliminating the "V"-shaped groove profile of the gate oxide and improving Al step coverage. The electrical characteristics of MOS transistors fabricated over laser annealed islands exhibited a 30-percent increase in channel mobility with a small negative shift (<0.2 V) in the transistor threshold voltage.     

Measurements of intrinsic efficiency and parameters of an electronbeam pumped ArXe laser

Measurements of the output energy and intrinsic efficiency of an electron-beam-pumped ArXe laser operating on the 1.73-μm line are reported. A 220-kV electron beam was used to pump either an 11×11×50 cm³ or an 11×11×25 cm³ active volume. Small-signal gain, nonsaturable loss, and saturation flux were deduced from a Rigrod analysis of the output energies as a function of output coupler reflectivity. Electron beam pump powers ranging from 2.2 to 16.2 kW/cm³ were employed. At a pump power of 2.2 kW/cm³ a small signal of 0.035 cm^-1 , a gain-to-loss ratio of 272, and a saturation flux of 2.1 kW/cm ² were determined. Intrinsic efficiencies of 4% were obtained at the lower pump powers. From the measurements of the laser output it is clear that the secondary electrons have a significant impact on the laser kinetics and efficiency     

Molecular beam epitaxial GaAs/AlGaAs heterojunction bipolartransistors on (311)A GaAs substrates with all-silicon doping

The authors have investigated the characteristics and reproducibility of Si-doped p-type (311)A GaAs layers for application to heterojunction bipolar transistors (HBTs) grown by molecular beam epitaxy (MBE). The authors obtained p=2.2×10¹⁹ cm^-3 in a layer grown at 670°C. They have used all-Si doping to grow n-p-n transistors. These devices exhibit excellent DC characteristics with β=230 in a device with base doping of p=4×10¹⁸ cm^-3     

A 0.65-ns, 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM

An ultrahigh-speed 72-kb ECL-CMOS RAM macro for a 1-Mb SRAM with 0.65-ns address-access time, 0.80-ns write-pulse width, and 30.24-μm ² memory cells has been developed using 0.3-μm BiCMOS technology. Two key techniques for achieving ultrahigh speed are an ECL decoder/driver circuit with a BiCMOS inverter and a write-pulse generator with a replica memory cell. These circuit techniques can reduce access time and write-pulse width of the 72-kb RAM macro to 71% and 58% of those of RAM macros with conventional circuits. In order to reduce crosstalk noise for CMOS memory-cell arrays driven at extremely high speeds, a twisted bit-line structure with a normally on MOS equalizer is proposed. These techniques are especially useful for realizing ultrahigh-speed, high-density SRAM's, which have been used as cache and control storages in mainframe computers     

A review and projection of semiconductor components for digital storage

Evolution of present integrated-circuit technology over the remainder of the decade should result in semiconductor memories which are competitive with moving-surface memories and other alternatives in many digital storage applications requiring 10⁷-10¹⁰bits capacity. This paper considers MOS, MNOS, CCD, and bipolar component approaches to this objective. Cost, reliability, and power consumption, as affected by technological choices, receive attention. Alternative device technologies and circuit designs are examined. The one-transistor MOS RAM is seen to have potential for considerable growth. Packaging and interconnection methods for low cost and high reliability are considered; evolution of existing techniques is expected. Reliability and maintainability characteristics are seen to be controlled by device technology, component organization, and packaging characteristics. Testing, screening, and error-correction techniques are considered. Projections of component characteristics are extended to outline hypothetical designs for 4-million-bit and 256-million-bit storage systems which might be built by 1980. Features include 64K-bit MOS RAM components on die of area under 100 mm², system selling price of 40 m¢/bit, power consumption well below 1 µW/bit, system MTBF greater than 10⁵h, and physical density on the order of 16000 bits/ cm³. The basis for projected parameters is explained. The advantages and drawbacks of these hypothetical systems relative to moving-surface magnetic storage systems are outlined.     

Simple low-frequency optical fiber accelerometer with largerotating machine monitoring applications

A simple fiber optic accelerometer with large rotating equipment monitoring applications is presented. The sensor is optimized for detection of mechanical vibrations in the frequency range 0.2-140 Hz. The minimum detectable acceleration is 0.025 m/s² root mean square (rms), and it has low transverse sensitivity. The transducer operating principle, based on a fiber optic cantilever beam without any selamic mass on it, is simple and easy to construct, and the intensity-modulation and compensation techniques developed require simple electronic processing and provide very good stability and accuracy. Other advantages of the system are its robustness, compact size, and cost-effectiveness, which make it appropriate for industrial applications, specially for those where harsh environments are involved. The complete process of research and development of the sensor has been carried out, from the theoretical study of its operation principles, through the design, fabrication, experimental characterization and enhancement, to its starting up in a high-power electric station for hydrogenerator monitoring     

A 1.5-ns access time, 78-μm2 memory-cell size, 64-kbECL-CMOS SRAM

A 1.5-ns access time, 78-μm² memory-cell size, 64-kb ECL-CMOS SRAM has been developed. This high-performance device is achieved by using a novel ECL-CMOS SRAM circuit technique: a combination of CMOS cell arrays and ECL word drivers and write circuits. These ECL word drivers and write circuits drive the CMOS cell arrays directly without any intermediate MOS level converter. In addition to the ultrahigh-speed access time and relatively small memory-cell size, a very short write-pulse width of 0.8 ns and sufficient soft-error immunity are obtained. This ECL-CMOS SRAM circuit technique is especially useful for realizing ultrahigh-speed high-density SRAMs, which have been used as cache and control storages of mainframe computers     

电容式微波功率检测系统的灵敏度特性研究

为了提高电容式微波功率检测系统的综合性能,首先建立了MEMS悬臂梁的力学解析模型,研究了MEMS悬臂梁在静电力与弹性力综合作用下的运动规律,并建立了灵敏度的解析模型。研究结果表明,灵敏度主要受悬臂梁至下拉极板的初始间距、梁板长度影响。其中,灵敏度与间距成反相关关系,与梁板长度成正相关关系。在34~36 GHz的Ka波段内,根据力学解析模型和灵敏度模型,灵敏度的仿真结果分别为4.4 fF/W @34 GHz、4.1 fF/W @35 GHz、3.7 fF/W @36 GHz,实验测试结果分别为5.0 fF/W @34 GHz、4.5 fF/W @35 GHz、4.0 fF/W @36 GHz。灵敏度的仿真结果与测试结果比较吻合,这对改善电容式微波功率检测系统的综合性能具有一定的指导意义。