A 1.1-mW 10-bit 50-MSample/s hybrid two-step ADC in 0.13-µm CMOS technology

This paper presents a hybrid two-step analog-to-digital converter (ADC) that employs a successive approximation register (SAR) ADC and a time-to-digital converter (TDC)-based ADC as coarse and fine converters, respectively. By exploiting the respective advantages of the SAR and TDC architectures, the two-step ADC is realized without a high-gain amplifier for high linearity of a multiplying digital-to-analog converter. Thus, the proposed architecture can implement a low-power ADC without compromising operational speed. In addition, two digital error corrections are used to compensate for TDC error and the final ADC output, respectively. A 10-bit 50 MS/s ADC is fabricated in a 0.13-μm complementary metal–oxide–semiconductor process and occupies a 0.12-mm² die area. Furthermore, it consumes only 1.1 mW and achieves a signal-to-noise distortion ratio and spurious-free dynamic range of 53.67 and 60 dB, respectively, resulting in a 53.7 fJ/conversion-step at a 25-MHz full-scale input.     

Data Converter for Multistandard Mobile Phones

This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures. The entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm². A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.     

A 2.5-V 12-b 54-Msample/s 0.25-μm CMOS ADC in 1-mm2with mixed-signal chopping and calibration

This paper describes a two-step analog-to-digital converter (ADC) with a mixed-signal chopping and calibration algorithm. The ADC consists primarily of analog blocks, which do not suffer from the matching limitations of active devices. The offset on two residue amplifiers limits the accuracy of the ADC. Background digital offset extraction and analog compensation is implemented to continuously remove the offset of these critical analog components. The calibrated two-step ADC achieves -70 dB THD in the Nyquist band, with a 2.5-V supply. The ADC is realized in standard single-poly 5-metal 0.25-μm CMOS, measures 1.0 mm² , and dissipates 295 mW     

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at P_in = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.     

A 25-GS/s 6-bit time-interleaved SAR ADC with design-for-test memory in 40-nm low-leakage CMOS

This paper presents a 25-GS/s 6-bit time-interleaved (TI) SAR ADC in a 40-nm CMOS low-leakage (LL) process. The prototype utilizes 4 × 12 hierarchical sampling architecture to reduce the complexity of track-and-hold circuits and the timing skew calibration. The single-channel SAR ADC adopts asynchronous processing with two alternate comparators. A partially active reference voltage buffer is designed to reduce the power consumption. The method based on sinusoidal signal approximation is employed to calibrate timing skew errors. To characterize the ultra-high-speed ADC, an on-chip design-for-test memory is designed. At 25 GS/s, the ADC achieves the SNDR of 32.18 dB for low input frequency and 27.28 dB for Nyquist frequency. The chip consumes 800 mW and occupies 1.3 × 2.6 mm², including the TI ADC core and memory.     

一种10bit双通道流水线SAR ADC设计

为了提高模数转换器的采样频率并降低其功耗,提出一种10 bit双通道流水线逐次逼近型（SAR）模数转换器（ADC）。提出的ADC包括两个高速通道,每个通道都采用流水线SAR结构以便低功率和减小面积。考虑到芯片面积、运行速度以及电路复杂性,提出的处于第二阶段的SAR ADC由1 bit FLASH ADC和6 bit SAR ADC组成。提出的ADC由45 nm CMOS工艺制作而成,面积为0.16 mm2。ADC的微分非线性和积分非线性分别小于0.36 最低有效位（LSB）和0.67 LSB。当电源为1.1 V时,ADC的最大运行频率为260 MS/s。运行频率为230 MS/s和260 MS/s的ADC的功率消耗分别为13.9 mW和17.8 mW。     

Contention‐based geographic forwarding in asynchronous duty‐cycled wireless sensor networks

In asynchronous duty‐cycled wireless sensor networks, it is desirable that the data forwarding scheme is adaptive to the dynamics caused by the uncertainty of sensor nodes’ working schedules. Contention‐based forwarding is designed to adapt to the dynamic environments. In this work, we are interested in the contention‐based geographic forwarding (CGF) for two asynchronous duty‐cycling (ADC) models, which we refer to as uninterruptible ADC (U‐ADC) and interruptible ADC (I‐ADC). We propose a new residual time‐aware routing metric for CGF in the I‐ADC model and present a residual time‐aware forwarding scheme using this metric. We evaluate the performance of CGF in both asynchronous duty‐cycling models. Simulation results show that CGF in the U‐ADC model provides a shorter delivery delay while suffering from a high sender effective duty cycle problem. CGF in the I‐ADC model incurs a very long data delivery delay, but it can achieve a good load balancing among nodes. It is also demonstrated that the proposed residual time‐aware forwarding scheme lowers the effects of the performance degradation caused by the pure asynchronous duty‐cycling operation. Copyright © 2011 John Wiley & Sons, Ltd.     

An efficient threshold voltage generation for SAR ADCs

In this paper, a new architecture for successive-approximation register (SAR) analog-to-digital converters (ADCs) is presented. In the proposed scheme, the threshold voltage for each comparison is divided into two parts. This results in appreciably less switching energy and less total capacitance without a substantial increase in digital complexity compared to the conventional SAR ADC. Analytical calculations and circuit level simulation results in the context of a 10-bit 100 kS/s ADC are provided to verify the usefulness of the proposed SAR ADC scheme revealing 87 % less switching power and 40 % less total capacitance in comparison with the conventional SAR ADC.     

1GS/s pipelined delta sigma modulator ADC using residue averaging technique

A two stage pipelined delta sigma modulator (PDSM) ADC is presented for broadband, high-resolution applications, which incorporate a first, order delta sigma modulator in each stage and combines the most significant bits of the first stage with the second stage output. A key feature of the PDSM ADC architecture is a SINC filter residue averaging technique, which results in mitigating the effect of track/hold and analog, subtract circuit errors, DAC non-linearity, and component mismatch. The input bandwidth of 62.5 MHz and the sampling frequency of 1 GHz result in an over sampling ratio of 8 for the first order modulators. MATLAB simulations for the two stage ADC show 13–15 bit resolution. A transistor level design in 0.18 um CMOS for the two stage ADC was captured with Cadence tools and simulations show 12 bit resolution with a 50 MHz input.     

高速ADC及由其构成的并行/交替式数据采集系统的非线性研究

本文研究了高速ADC及由其构成的并行/交替式数据采集系统的DNL(微分非线性)与INL(积分非线性)及有关测试理论与方法.根据统计学方法由单片ADC的DNL和INL导出了并行/交替式数据采集系统的DNL和INL的数学表达式;并且采用统计直方图方法分别对单片ADC和由双片ADC组成的并行/交替式数据采集系统进行了计算机仿真.结果表明,并行/交替式数据采集系统的DNL与INL小于每一通道单片ADC的DNL和INL.     

A 10-b 20-Msample/s low-power CMOS ADC

A single-ended input but internally differential 10 b, 20 Msample/s pipelined analog-to-digital converter (ADC) is demonstrated with 4 mW per stage using a single 5 V supply. The prototype ADC made of an input sample and hold (S/H) plus 8 identical unscaled pipelined stages consumes 50 mW including power consumed by a bias generator and two internal buffer amplifiers driving common-mode bias lines. Key circuits developed for this low-power ADC are a dynamic comparator with a capacitive reference voltage divider that consumes no static power, a source-follower buffered op amp that achieves wide bandwidth using large input devices, and a self-biased cascode biasing circuit that tracks power supply variation. The ADC implemented using a double-poly 1.2 μm CMOS technology exhibits a DNL of ±0.65 LSB and a SNDR of 54 dB while sampling at 20 MHz. The chip die area is 13 mm²     

8位CMOS双通道流水线ADC仿真设计

设计了一种8位1.2V,1GS/s双通道流水线A/D转换器(ADC)。所设计ADC对1.5位增益D/A转换电路(MDAC)中的流水线双通道结构进行改进,其中设置有双通道流水线时分复用运算放大器和双/单通道快闪式ADC,以简化结构并提高速度;在系统前置采样/保持器中加设由单一时间信号驱动的开关线性化控制(SLC)电路,以解决两条通道之间的采样歪扭和时序失调问题。用90nm标准CMOS工艺对所设计的流水线ADC进行仿真试验,结果表明,室温下所设计ADC的信噪比SNR为32.7dB,无杂散动态范围SFDR为42.3dB,它的分辨率、功耗PD和采样速率SR分别为8位、23mW和1GS/s,从而满足了高速、高精度和低功耗的应用需要。     

A 12-bit 1.0/2.0 GS/s Pipeline ADC in 0.18 µm SiGe BiCMOS

A 12-bit time-interleaved 1.0/2.0 GS/s pipeline analogue–digital converter (ADC) is presented and implemented in 0.18 µm SiGe BiCMOS. Such an ADC consists of two identical channels, each of which can operate at 1 GS/s. The two same channels can be interleaved to achieve 2 GS/s speed. In one-channel ADC, four lanes of pipeline ADCs with 250 MS/s are interleaved to realise 1 GHz conversion. To avoid the timing skew-induced error among the four lanes, a dedicated T/H is adopted in one channel. A clock buffer with low jitter is presented to provide a low-voltage swing clock for the T/H by using SiGe devices. The proposed timing system generates the phases needed accurately. A single reference buffer is employed in one-channel ADC to avoid the gain mismatches among the four lanes. An analogue mux with the proposed switch chooses the mode of interleaving or non-interleaving. A trimming digital–analogue converter is employed to eliminate the gain mismatches between the two channels. The measured SNDR and SFDR for one-channel ADC @ 1 GS/s are 60 and 76 dB with Nyquist input. For the interleaved two channels @ 2 GS/s, SNDR and SFDR can achieve 58 and 61 dB with Nyquist input.     

16-level CVNS memory with fast ADC

A novel 16-level current-mode DRAM based on the continuous valued number system (CVNS) representation is introduced. The refreshing circuitry of this DRAM is designed using analogue to digital converter (ADC) and digital to analogue converter modules. Each ADC generates two bits of the output simultaneously which decreases the delay time of the ADC module. Error correction codes are used to increase the noise margin by a factor of two. The proposed memory can be used in hardware implementation of CVNS based systems.     

Comparative analysis of readout large-scale integrated circuits with an analog-to-digital converter in the cell for a photodetector of the far infrared range

The design of a 14-bit delta-sigma analog-to-digital converter (ADC) with pipelined readout is considered. Basic concepts of the design of array photodetectors of the infrared (IR) range with an ADC in the accumulating cell are analyzed. The presence of an ADC in the readout large-scale integrated circuit (LSIC) cell provides an opportunity to increase the accumulation time by more than an order of magnitude and improve the threshold characteristics. A method for optimization of the ADC area by using an LFSR counter operating in two modes (digital code generation and serial readout) is proposed.     

Comparator-based binary-search ADC architectures for UWB receivers

Recently, modern wireless communication applications have pushed ADCs power consumption into the range of fJ/conversion step by introducing circuit and architectural level enhancements. In this paper we propose improvements to binary-search topologies and demonstrate them on two ADC designs. The first one, a 4-bit ADC, uses 2 ^N  ? 1 comparators arranged in N stages, and a set of N time-interleaved track-and-holds is introduced along with a pipelined operation of the comparators, leading to an increase of the ADC throughput rate. The second is a 5-bit ADC in which the number of comparators is reduced to N. The reduction is possible because we employ reconfigurable comparator with multiple thresholds, thus splitting the comparison range. As the implementation of accurate threshold voltages has a critical impact on ADC performance, an effective design methodology based on optimization through genetic algorithms was used for the comparators. Monte Carlo simulations performed on the first ADC show that, sampling at 1.5 GSps, the ADC consumes 4.2 mW, providing 3.67 effective bits, leading to a figure of merit (FOM) of 219 fJ/conversion step. With the reduction in the number of comparators, the second ADC consumes 5 mW providing 4.6 effective bits and a FOM of 138 fJ/conversion step at the same sampling rate.     

12位Sigma-Delta模数转换器的降采样滤波器设计

一种由SNR（信噪比）驱动的滤波器设计,用于12位Sigma-Delta模数转换器。Sigma-Delta模数转换器包括Sigma-Delta调制器和降采样滤波器两部分,首先用Sigma-Delta调制器对信号进行过采样率量化,然后通过降采样滤波器进行数字信号处理,将信号还原到原始采样率并去除量化噪声。和传统的模数转换器相比,Sigma-Delta模数转换器具有采样率高、精度高、面积小等优点。Sigma-Delta模数转换器的滤波器设计有降采样率和滤波性能两个指标要求,该设计方法由SNR驱动并采用了两种滤波器方案,设计结果在MATLAB里进行了仿真,其SNR大于74 dB,达到12位Sigma-Delta模数转换器的要求。     

一种基于FLASH的混合式11位ADC设计

时域延迟线架构ADC的非线性问题,导致其无法达到较高的分辨率。针对该问题,提出了一种将Flash和延迟线架构相结合的新型低功耗11位ADC。该新型混合ADC架构由两个模块构成,分别为4位Flash ADC架构和7位延迟线ADC架构,因此同时具有 Flash ADC 和延迟线 ADC 的准确性和高效性。采用 CHARTERED 65 nm Dual Gate Mixed Signal CMOS Process设计并绘制出混合式ADC版图。实验测试结果显示,在供应电压为1.1 V和采样效率为100 Msample/s的条件下,混合式ADC产生的信噪失真比( SNDR)为60 dB,消耗功率为1.6 mW。在无需任何校准技术的情况下,混合式ADC产生的品质因数( FOM)为19.4 fJ/分级转换。此外,利用不匹配的3σ设备进行了蒙特卡罗试验,结果表明,SNDR值低于其ADC架构。     

A 1-V 5-bit 0.5 GS/s time-based flash ADC in 0.18 µm CMOS technology

A novel low-voltage rail-to-rail parallel time-based analog-to-digital converter (ADC) is proposed. The proposed ADC works like a conventional flash ADC except that the process is performed in the time-domain. Since the operation of analog integrated circuits at low supply voltages is limited, converting the voltage signals to the time domain improves the efficiency of the circuit. In this paper, a constant-delay ladder is utilized to make the reference delay-times to compare with the input signal. A 1-V 5-bit 500 MS/s ADC has been designed and simulated in 0.18 µm CMOS technology consumed 3.66 mW. The simulation results show 0.3lsb and 0.2lsb for INL and DNL respectively. Signal-to-noise and distortion ratio (SNDR) of the proposed ADC is 26.7 dB at Nyquist frequency. The rail-to-rail operation and linearity of the voltage-to-time converter (VTC) improved the efficiency of the ADC comparing to the similar time-based ADCs. The figure-of-merit (FoM) of the ADC is about 0.31 (pJ/conv.step).

     

An 8/10 bit 200/100MS/s configurable asynchronous SAR ADC

This paper presents an asynchronous 8/10 bit configurable successive approximation register analog-to-digital converter (ADC). The proposed ADC has two resolution modes and can work at a maximal sampling rate of 200 and 100MS/s for 8 bit mode and 10 bit mode respectively. The ADC uses a custom-designed 1 fF unit capacitor to reduce the power consumption and settling time of capacitive DAC, a dynamic comparator with tail current to minimize kickback noise and improve linearity. Moreover, asynchronous control technique is utilized to implement the ADC in a flexible and energy-efficient way. The proposed ADC is designed in 90 nm CMOS technology. At 100MS/s and 1.0 V supply, the ADC consumes 1.06 mW and offers an ENOB of 9.56 bit for 10 bit mode. When the ADC operates at 8 bit mode, the sampling rate is 200MS/s with 1.56 mW power consumption from 1.0 supply. The resulted ENOB is 7.84 bit. The FOMs for 10 bit mode at 100MS/s and 8 bit mode at 200MS/s are 14 and 34 fJ/conversion-step respectively.