A service-based architecture for dynamically reconfigurable workflows

In the last few years, business process management systems have been employed for handling information systems of ever increasing complexity. As a consequence, the adoption of modelling languages enabling smooth and seamless transitions among the various phases of the process lifecycle, the ability of exploiting coordination schema over distributed execution contexts and the support for dynamic evolution and reconfiguration have become software engineering issues of great importance. This paper proposes the use of PN-Engine, a decentralized Petri nets execution engine, as a business process enactment engine. PN-Engine, which is based on the Jini service architecture, supports the decentralized execution of process models specified as Petri nets (PNs) enhanced with modular constructs and offers suitable mechanisms for dealing with the aforementioned design issues. PN-Engine allows to deploy and enact a new version of an existing process model without requiring the stopping/removal of older instances that are still running. The paper presents a novel approach enabling a decentralized migration procedure where concurrent portions of older instances migrate asynchronously to the new process model. Advantages of the proposed approach are demonstrated by means of an example concerning a workflow for a wine-production process.     

Virtualization of reconfigurable coprocessors in HPRC systems with multicore architecture

HPRC (High-Performance Reconfigurable Computing) systems include multicore processors and reconfigurable devices acting as custom coprocessors. Due to economic constraints, the number of reconfigurable devices is usually smaller than the number of processor cores, thus preventing that a 1:1 mapping between cores and coprocessors could be achieved. This paper presents a solution to this problem, based on the virtualization of reconfigurable coprocessors. A Virtual Coprocessor Monitor (VCM) has been devised for the XtremeData XD2000i In-Socket Accelerator, and a thread-safe API is available for user applications to communicate with the VCM. Two reference applications, an IDEA cipher and an Euler CFD solver, have been implemented in order to validate the proposed architecture and execution model. Results show that the benefits arising from coprocessor virtualization outperform its overhead, specially when code has a significant software weight.     

A reconfigurable manager for dynamically reconfigurable hardware

Dynamic reconfiguration has been a technology solution in search of the right problem to solve. Effective use of the technology requires new programming and task management models. This article describes an approach to dynamic reconfiguration that reduces reconfiguration latency to the point where dynamic multimedia applications can now exploit such platforms.     

CuNoC: A dynamic scalable communication structure for dynamically reconfigurable FPGAs

The growing complexity of integrated circuits imposes to the designers to change and direct the traditional bus-based design concepts towards NoC-based. Networks on-chip (NoCs) are emerging as a viable solution to the existing interconnection architectures which are especially characterized by high level of parallelism, high performances and scalability. The already proposed NoC architectures in the literature are destined to System-on-chip (SoCs) designs. For a FPGA-based system, in order to take all benefits from this technology, the proposed NoCs are not suitable. In this paper, we present a new paradigm called CuNoC for intercommunication between modules dynamically placed on a chip for the FPGA-based reconfigurable devices. The CuNoC is based on a scalable communication unit characterized by unique architecture, arbitration policy base on the priority-to-the-right rule and modified XY adaptive routing algorithm. The CuNoC is namely adapted and suited to the FPGA-based reconfigurable devices but it can be also adapted with small modifications to all other systems which need an efficient communication medium. We present the basic concept of this communication approach, its main advantages and drawbacks with regards to the other main already proposed NoC approaches and we prove its feasibility on examples through the simulations. Performance evaluation and implementation results are also given.     

A pipeline virtual environment architecture for multicore processor systems

We present a novel architecture to develop Virtual Environments (VEs) for multicore CPU systems. An object-centric method provides a uniform representation of VEs. The representation enables VEs to be processed in parallel using a multistage, dual-frame pipeline. Dynamic work distribution and load balancing is accomplished using a thread migration strategy with minimal overhead. This paper describes our approach, and shows it is efficient and scalable with performance experiments. Near linear speed-ups have been observed in experiments involving up to 1,000 deformable objects on a six-core i7 CPU. This approach’s practicality is demonstrated with the development of a medical simulation trainer for a craniotomy procedure.     

A novel folded-torus based network architecture for power-aware multicore systems

Multicore computers are expected to be used to process a higher volume of data in the future. Current mesh-like multicore architecture is inadequate to increase memory-level-parallelism because of its poor core-to-core interconnection topology. In some architecture, each node has communication and computation components – switching component of such a node consumes power while the node is only computing and vice versa. In this paper, we propose a folded-torus based topology to improve performance and energy saving. In this architecture, nodes are separated between network switches and computing cores. Using folded-torus concept, we develop a scheme to connect the components (switches and cores) of a multicore architecture. Experimental results show that the proposed architecture outperforms Raw Architecture Workstation (RAW), Triplet Based Architecture (TriBA), and Logic-Based Distributed Routing (LBDR) architecture by reducing the switches more than 53%, the power consumption by up to 71%, and the average delay by up to 58%.     

Multi-constraints self-adaptation for reconfigurable multimedia embedded systems

The application of multimedia in embedded systems (ES), such as Virtual reality and 3-D imaging, represents the current trend in ES development. Coupling multimedia with ES has raised new multimedia-related challenges that have been added to the common ES constraints. These challenges deal with the real-time, quality, performance and efficient processing requirements of multimedia applications. The integration of self-adaptation in ES development has been, for many years, a paramount solution to cope with these issues. Although there has been extensive research on the topic of ES self-adaptation, the related works still lack global approaches that better deal with multimedia-related constraints. Coordinating different adaptation mechanisms, monitoring multiple system constraints and supporting multi-application contexts are still underexplored. The aim of the present work is to fill in these gaps by providing a global adaptation approach that offers better adaptation decisions with fair resource sharing among competing multimedia applications. With the above challenges in mind, we propose a multi-constraints combined adaptation approach that targets multimedia ES. It addresses four critical system constraints: maximizing the overall system‘s Quality of Application (QoA) under the real-time constraint, the remaining system energy and the available network bandwidth. It coordinates the adaptation at both application and architecture levels. To test and validate the proposed technique, a videophone system is designed on a Xilinx FPGA development board. It executes two complex multimedia applications. The validation results show the aptitude of the proposed system to successfully reconfigure itself at run-time in response to its constraints.

     

A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip

We address routing in Networks-On-Chip (NoC) architectures that use irregular mesh topologies with Long-Range Links (LRL). These topologies create difficult conditions for routing algorithms, as standard algorithms assume a static, regular link structure and exploit the uniformity of regular meshes to avoid deadlock and maintain routability. We present a novel routing algorithm that can cope with these irregular topologies and adapt to run-time LRL insertion and topology reconfiguration. Our approach to accommodate dynamic topology reconfiguration is to use a new technique that decomposes routing relations into two stages: the calculation of output ports on the current minimal path and the application of routing restrictions designed to prevent deadlock. In addition, we present a selection function that uses local topology data to adaptively select optimal paths.The routing algorithm is shown to be deadlock-free, after which an analysis of all possible routing decisions in the region of an LRL is carried out. We show that the routing algorithm minimises the cost of sub-optimally placed LRL and display the hop savings available. When applied to LRLs of less than seven hops, the overall traffic hop count and associated routing energy cost is reduced. In a simulated 8 × 8 network the total input buffer usage across the network was reduced by 6.5%.     

Security model oriented attestation on dynamically reconfigurable component-based systems

As more and more component-based systems (CBS) run in the open and dynamic Internet, it is very important to establish trust between clients and CBS in mutually distrusted domains. One of the key mechanisms to establish trust among different platforms in an open and dynamic environment is remote attestation, which allows a platform to vouch for its trust-related characteristics to a remote challenger. This paper proposes a novel attestation scheme for a dynamically reconfigurable CBS to reliably prove whether its execution satisfies the specified security model, by introducing a TPM-based attestation service to dynamically monitor the execution of the CBS. When only parts of the dynamic CBS are concerned, our scheme enables fine-grained attestation on the execution of an individual component or a sub-system in the dynamic CBS, such that it involves only minimal overhead for attesting the target parts of the CBS. With flexible attestation support, the proposed attestation service can attest a CBS at the granularity from an individual component to the whole CBS. As a case study, we have applied the proposed scheme on OSGi systems and implemented a prototype based on JVMTI for Felix. The evaluation results show that the proposed scheme is both effective and practical.     

High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms

The potential computational power of today multicore processors has drastically improved compared to the single processor architecture. Since the trend of increasing the processor frequency is almost over, the competition for increased performance has moved on the number of cores. Consequently, the fundamental feature of system designs and their associated design flows and tools need to change, so that, to support the scalable parallelism and the design portability. The same feature can be exploited to design reconfigurable hardware, such as FPGAs, which leads to rethink the mapping of sequential algorithms to HDL. The sequential programming paradigm, widely used for programming single processor systems, does not naturally provide explicit or implicit forms of scalable parallelism. Conversely, dataflow programming is an approach that naturally provides parallelism and the potential to unify SW and HDL designs on heterogeneous platforms. This study describes a dataflow-based design methodology aiming at a unified co-design and co-synthesis of heterogeneous systems. Experimental results on the implementation of a JPEG codec and a MPEG 4 SP decoder on heterogeneous platforms demonstrate the flexibility and capabilities of this design approach.     

A reconfigurable architecture for autonomous visual-navigation

Abstract. This paper describes the design of a reconfigurable architecture for implementing image processing algorithms. This architecture is a pipeline of small identical processing elements that contain a programmable logic device (FPGA) and double port memories. This processing system has been adapted to accelerate the computation of differential algorithms. The log-polar vision selectively reduces the amount of data to be processed and simplifies several vision algorithms, making possible their implementation using few hardware resources. The reconfigurable architecture design has been devoted to implementation, and has been employed in an autonomous platform, which has power consumption, size and weight restrictions. Two different vision algorithms have been implemented in the reconfigurable pipeline, for which some experimental results are shown. Received: 30 March 2001 / Accepted: 11 February 2002 RID="*" ID="*" This work has been supported by the Ministerio de Ciencia y Tecnología and FEDER under project TIC2001-3546 Correspondence to: J.A. Boluda     

飞思卡尔推出QorIQ通信平台首款八核微处理器行业最高标准

<正> 飞思卡尔半导体推出 QorIQ P4080多核处理器——一个旨在为嵌入式多核空间中的性能、功效和编程性设定新标准的非常先进的八核通信处理器。P4080多核处理器是飞思卡尔新 QorIQ 平台的标志性成员,基于45纳米处理技术。它集成了增强的 PowerArchitecture~(TM)内核、三级缓存分层、创新 CoreNet~(TM)片上结构和数据路径加速,可在最大30W 的功率电路内提供     

A unified link-layer fault-tolerant architecture for network-based many-core embedded systems

Reliability is an important design concern for modern many-core embedded systems. Specifically, on-chip interconnecting systems are vulnerable to permanent channel faults and transient data transmission faults which may significantly impact the overall system performance. In this work, a Unified Link-layer Fault-tolerant NoC (ULF-NoC) architecture is proposed. ULF-NoC is developed for NoC equipped with bidirectional channels and features wormhole switching (instead of store-and-forward switching) and packet-based retransmission. An intelligent buffer controller is developed that does not require separate, dedicated buffer spaces to support packet retransmissions. Extensive simulations using both synthetic and real world data traffics demonstrated marked performance of the proposed ULF-NoC solution.     

Execution models for reconfigurable embedded real‐time systems

This paper deals with the verification and assignment into the execution environment of Reconfigurable Control Applications following the Component‐based International Industrial Standard IEC61499. According to this Standard, a Function Block (FB) is an event‐triggered component and an application is an FB network that has to meet temporal properties according to user requirements. If a reconfiguration scenario is applied at run‐time, then the FB network implementing the application is totally changed or modified. To cover all possible cases, we classify such scenarios into three classes and we define an agent‐based architecture designed with nested state machines to automatically handle all possible reconfigurations. To verify and assign Function Blocks corresponding to each reconfiguration scenario into the execution environment, we define an approach based on the exploration of reachability graphs to verify temporal properties. This approach constructs feasible Operating System tasks encoding the FB network that corresponds to each scenario. Therefore, the application is considered as sets of Operating System (OS) tasks where each set is to load in memory when the corresponding reconfiguration scenario is applied by the agent. We developed the tool X ‐Assign supporting these contributions that we apply on the FESTO production system available in our research laboratory. Copyright © 2009 John Wiley and Sons Asia Pte Ltd and Chinese Automatic Control Society     

Embedded-TM: Energy and complexity-effective hardware transactional memory for embedded multicore systems

We investigate how transactional memory can be adapted for embedded systems. We consider energy consumption and complexity to be driving concerns in the design of these systems and therefore adapt simple hardware transactional memory (HTM) schemes in our architectural design. We propose several different cache structures and contention management schemes to support HTM and evaluate them in terms of energy, performance, and complexity. We find that ignoring energy considerations can lead to poor design choices, particularly for resource-constrained embedded platforms. We conclude that with the right balance of energy efficiency and simplicity, HTM will become an attractive choice for future embedded system designs.     

Software development for high-performance, reconfigurable, embedded multimedia systems

Reconfigurable platforms can be very effective for lowering production costs because they allow the reuse of architecture resources across a variety of applications. We show how to program a reduced-instruction-set-computing (RISC) microprocessor with a reconfigurable functional unit, focusing on DSP applications and using the example of a turbodecoder. We have developed a complete design flow, including a methodology and compilation tool chain, to address the instruction set hardware-software codesign problem for a processor with a runtime reconfigurable unit. The flow starts from a system-level specification (usually a software program) of the application and partitions it into software and hardware domains to achieve the best speed, power, and area performance, while satisfying resource constraints imposed by the target platform architecture. We describe a methodology and a set of tools that allow extensive design exploration for hardware-software codesign with the goal of improving the overall utilization of reconfigurable multimedia platforms.     

TEODOLINDA. A communication architecture for hospital information systems

This paper is focused on a system for the release and distribution of messages and services among hospital units, which extends hospital information systems features in the field of communication and supports hospital organisation to fulfil healthcare commitments.     

Termination detection for dynamically distributed systems with non-first-in-first-out communication

We propose a new algorithm for detecting termination of distributed systems. The algorithm works correctly whether the system is static or dynamic, whether the interprocess communication is synchronous or asynchronous, and whether the communication channels are first-in-first-out or not. The algorithm requires, in the worst case, O(nm) control messages in all, where n is the number of processes in the system and m is the total number of messages transmitted during the operation of the system. After the system terminates, the algorithm is able to detect the termination using only O(n) control messages; it is optimal if the system concerned is static.