Arbitrary dual-band unequal Wilkinson power divider based on negative refractive index transmission lines

This paper focused on the application of negative refractive index transmission line (NRI-TL) in dual-band unequal Wilkinson power divider (WPD) with controllable frequency and power dividing ratio. Theory and design procedure of the dual-band NRI-TL are presented in details. For demonstration, two dual-band unequal Wilkinson power dividers (WPDs) with power dividing ratio of 2 : 1 and operating frequencies of 0.9 and 1.8 GHz are designed, fabricated and tested. The first unequal divider is based on 2-stage NRI-TLs and the second one is based on 4-stage NRI-TLs. In addition, these two types of NRI-TLs are presented to demonstrate that by increasing the number of NRI-TL unit-cells the phase response of the NRI-TLs converge to the desired characteristic. The good agreement between measured and simulated results confirmed the design concept and derived closed-form design equations. Measurements show that the first divider has 18.37% and 21.86% relative bandwidths and the second one has 33.52% and 29.12% relative bandwidths at 0.9 and 1.8 GHz, respectively. The design concept of this paper can be extended to equal dual-band power dividers with arbitrary frequency ratio.     

Low-loss active inductor with independently adjustable self-resonance frequency and quality factor parameters

This work presents a new low-loss active inductor whose self-resonance frequency and quality factor parameters can be adjusted independently from each other. In order to achieve this property, a new input topology has been employed which consists of cascode structure with a diode connected transistor. Furthermore, the proposed input topology makes the device robust in terms of its performance over variation in process, voltage and temperature. Additionally, RC feedback is used to cancel series-loss resistance of the active inductor, which allows self-resonant enhancement as well. Schematic and post-layout simulation results show the theoretical validity of the design. To validate the design feasibility for process, voltage and temperature changes, Monte Carlo and temperature analysis are done. Suggested structure shows inductor behavior in the frequency range of 0.3–11.3 GHz. Maximum quality factor is obtained as high as 2.1k at 5.9 GHz. Total power consumption is as low as 1 mW with 1.8 V power supply.     

Low power dissipation SiGe HBT dual-band variable gain amplifier

A dual-band variable gain amplifier operating at 0.9 GHz and 2.4 GHz was designed based on high performance RF SiGe HBT for large amount of signals transmission and analysis. Current steering was adopted in gain-control circuit to get variable trans-conductance and then variable gain. Emitter degeneration and current reuse were considered in amplifying stage for low noise figure and low power dissipation respectively. A single-path circuit resonating at two frequency points simultaneously was designed for input impedance matching. PCB layout parasitic effects, especially the via parasitic inductor, were analyzed theoretically and experimentally and accounted for using electro-magnetic (EM) simulation. The measurement results show that a dynamic gain control of 26 dB/16 dB in a control voltage range of 0.0–1.4 V has been achieved at 0.9/2.4 GHz respectively. Both S₁₁ and S₂₂ are below than –10 dB in all the control voltage range. Noise figures at both 0.9 GHz and 2.4 GHz are lower than 5 dB. Total power dissipation of the dual-band VGA is about 16.5 mW at 3 V supply.     

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner

A 1 V, 69–73 GHz CMOS power amplifier based on improved Wilkinson power combiner is presented. Compared with the traditional one, the proposed Wilkinson power combiner could lower down the insertion loss and reduce the die area by eliminating the quarter-wavelength transmission lines while preserving the characteristics of Wilkinson power combining and good port isolation. The presented power amplifier has been implemented in 65 nm CMOS process and achieves a measured saturated output power of 10.61 dBm and a peak power added efficiency of 8.13% at 73 GHz with only 1 V power supply. The die area including pads is 1.23×0.45 mm², while the power combiner only occupies 200×80 μm².     

Floating active inductor based Class-C VCO with 8 digitally tuned sub-bands

A fully integrated floating active inductor based voltage-controlled oscillator (VCO) is presented. The active inductor employs voltage differencing transconductance amplifier (VDTA) as a building block. The designed VCO achieves frequency tuning by varying the bias current through the VDTA and utilizes a Class-C topology for improving the phase noise performance. The inductor-less VCO is designed and implemented in a 45-nm CMOS process and its performance is estimated using Virtuoso ADE of Cadence. Operating at a supply voltage of ±1 V, the proposed VCO consumes 0.44–1.1 mW corresponding to the oscillation frequency of 1.1–1.8 GHz thereby exhibiting a tuning range of 48.27%. The phase noise of the VCO lies in the range of −94.12 to −98.37 dBc/Hz at 1 MHz offset resulting in a FOM of −172.14 to −176.69 dBc/Hz.     

Optimized 2.4 GHz voltage controlled oscillator with a high-Q MWCNT network-based pulse-shaped inductor

This paper focuses on the use of a high-Q Multi-Wall Carbon Nano-Tube (MWCNT)-based pulse-shaped inductor in the implementation of an LC differential voltage-controlled oscillator (LCVCO). The topology integrates a micro-scaled capacitor and a MWCNT network-based inductor together with the CMOS circuits. The CMOS circuits were designed to enhance the quality factor and to control the oscillation amplitude. The high quality factor of the inductor improves the overall quality factor and phase noise of the oscillator. The measurement results show that the LCVCO operates at 2.3982 GHz and achieves a phase noise of ?133.3 dBc/Hz at 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.07 GHz to 2.77 GHz (29.16%) with an ultra low power consumption of 1.7 mW from a 0.6 V supply voltage. The output power level of the VCO is ?10 dBm, with an improved quality factor of 49.     

A broadband Doherty power amplifier with harmonic suppression

In this paper, the design and implementation of the broadband, Doherty power amplifier (DPA) with 2nd and 3rd harmonics suppression, with theoretical analysis is presented. In the proposed structure a novel harmonic suppressed Wilkinson power divider used in DPA, which results in harmonic suppression with high level of attenuation. Moreover the proposed DPA has major advantages in terms of the linearity and works on a wideband frequency range (2.1–2.7 GHz) with minimum 40% drain efficiency (DE). The linearity of the proposed DPA is increased extremely, which significant improvement (7 dBm) is achieved from the main amplifier. In the proposed DPA, the main and the auxiliary amplifiers are implemented using Class-AB and Class-C topology respectively with equal MRF6S27015N MOTOROLA transistors in LDMOS technology.     

A 24-dB Ku-band low-power linearized 90-nm amplifier with a built-in output buffer

In this paper, we present a 90-nm high gain (24 dB) linearized CMOS amplifier suitable for applications requiring high degree of port isolation in the K_u-band (13.2–15.4 GHz). The two-stage design is composed of a low-noise common-gate stage and a gain-boosting cascode block with an integrated output buffer for measurement. Optimization of input stage and load-port buffer parameters improves the front-end's linear coverage, port return-loss, and overall gain without burdening its power demand and noise contribution. With low gate bias voltages (0.65–1.2 V) and an active current source, <?10 dB port reflection loss and 3.25–3.41 dB NF are achieved over the bandwidth. The input reflection loss of the overall amplifier lies between ?35 and ?10 dB and the circuit demonstrates a peak forward gain of 24 dB at 14.2 GHz. The output buffer improves the amplifier's forward gain by ～9 dB and pushes down the minimum output return loss to ?22.5 dB while raising the front-end NF by only 0.05 dB. The effect of layout parasites is considered in detail in the 90-nm process models for accurate RF analysis. Monte Carlo simulation predicts 9% and 8% variation in gain and noise figures resulting from a 10% mismatch in process. The K_u-band amplifier including the buffer block consumes 7.69 mA from a 1.2-V supply. The proposed circuit techniques achieve superior small signal gain, GHz-per-milliwatt, and range of linearity when compared with simulated results of reported microwave amplifiers.     

A resistive-feedback LNA in 65 nm CMOS with a gate inductor for bandwidth extension

In order to get a wideband and flat gain, a resistive-feedback LNA using a gate inductor to extend bandwidth is proposed in this paper. This LNA is based on an improved resistive-feedback topology with a source follower feedback to match input. A relative small inductor is connected in series to transistor׳s gate, which boosts transistor׳s effective transconductance, compensates gain loss and then leads the proposed LNA with a flat gain and wider bandwidth. Moreover, the LNA׳s noise is partially inhibited by the gate inductor, especially at high frequency. Realized in standard 65-nm CMOS process, this LNA dissipates 12 mW from a 1.5-V supply while its core area is 0.076 mm². Across 0.4–10.6 GHz band, the proposed LNA provides 9.5±0.9 dB power gain (S₂₁), better than −11-dB input matching, 3.5-dB minimum noise figure, and higher than −17.2-dBm P_1 dB.     

3.1–10.6 GHz ultra-wideband LNA design using dual-resonant broadband matching technique

This paper presents an ultra-wideband low noise amplifier design using the dual-resonant broadband matching technique. The proposed LNA achieves a 10.2 dB gain with ±0.9 dB gain flatness over a frequency range of 3.1–10.6 GHz and a ?3-dB bandwidth of 2.4–11.6 GHz. The measured noise figure ranges from 3.2 to 4.7 dB over 3.1–10.6 GHz. At 6.5 GHz, the measured IIP3 and input-referred P1dB are +6 dBm and ?5 dBm, respectively. The proposed LNA occupies an active chip area of 0.56 mm² in a TSMC 0.18 μm RF-CMOS process and consumes 16 mW from a 1.8 V supply.     

Low-power CMOS LC QVCO using zero-biased transistor coupling of MWCNT network-based VCO structure

This paper presents design, analysis and implementation of a 2.4 GHz QVCO (Quadrature Voltage Controlled Oscillator), for low-power, low-voltage applications. Cross coupled LC VCO (Inductor–Capacitor Voltage Controlled Oscillator) topology realized using integration of a micro-scaled capacitor and a MWCNT (Multi-Wall Carbon Nano-Tube) network based inductor together with the CMOS circuits is utilized together with MOS transistors as coupling elements to realize QVCO. With the passive coupling achieved from the MOS transistors, power consumption is minimized while maintaining a small chip area. The variable capacitors and the inductors are designed using ANSYS and imported through DAC components in ADS (Advanced Design software). Accurate simulation of the QVCO is performed in the software environments and the results are provided. The measurement results show that the QVCO provides quadrature signals at 2.4 GHz and achieves a phase noise of −130 dBc/Hz 1 MHz away from the carrier frequency. The VCO produces frequency tuning from 2.1 GHz to 2.60 GHz (20.83%) with a control voltage varying from 0 to 0.3 V. It achieves a peak to peak voltage of 0.59 V with an ultra low power consumption of 3.8 mW from a 0.6 V supply voltage. The output power level of the QVCO is −10 dBm, with an improved quality factor of 45. The phase error of the QVCO is measured as 3.1°.     

Optimum design of a wideband planar N-way fork power divider with arbitrary power division and input-to-output impedance matching

An effective design procedure based on method of least squares is proposed for multi-section and multi-output fork power divider/combiner with arbitrary power division ratios among its outputs in a specified frequency bandwidth together with impedance matching among its arbitrary source/load impedances. Transmission and scattering matrices are obtained for its equivalent circuit. An error function is constructed based on design specifications on its output power division ratios, isolations among output ports, return losses at its input and output ports and source/load impedances in a desired frequency bandwidth. The design procedure is fully developed, which determines the widths and lengths of microstrip line sections and resistor values. A design example is described for unequal power division ratio and unequal input/output impedances. A 3-section and 3-output fork power divider is designed for equal power division and load/source impedances for 2–12 GHz band. It is fabricated and measured. Variations of its transmission coefficients are less than 0.5 dB, isolations at its outputs are better than −15 dB and reflection coefficients at its ports are better than −10 dB. Excellent agreement is observed among the results of the proposed design procedure, full wave computer software and measurement data.     

A high-gain low-power 2–14 GHz ultra-wide-band CMOS LNA for wireless receivers

In this paper, a 2–14 GHz CMOS LNA for ultra-wide-band (UWB) wireless systems is presented. To achieve a good and flat high power gain along with a low noise figure and a high input return loss, the proposed LNA adopts a capacitive cross-coupling common-gate (CG) topology with extra cascaded transistors and inductance. Over the entire 2–14 GHz bandwidth, it exhibits a return loss less than ?10 dB and a small-signal gain of 9 dB. With an input intercept point of ?3 dBm at 5 GHz, it consumes only 9 mW from a 1.5 V supply voltage.     

Design of a microstrip diplexer with a novel structure for WiMAX and wireless applications

In this paper, a novel combination of coupled lines, loops, step impedance and low impedance sections are used to design a compact microstrip diplexer. The designing method is based on obtaining transmission matrices and finding the effective parameters in tuning the resonance frequencies. T-shape tapped lines feed structures are added to three terminals of the proposed diplexer to decrease insertion losses at the both passbands without increasing the overall size. The proposed diplexer with a total size of 573.11 mm² operates at 2.6 GHz for IEEE 802.16 and 802.20 WiMAX technology and 6 GHz for wireless applications. The insertion losses at the lower and higher resonance frequencies are 0.6 dB and 0.9 dB, respectively. The proposed structure is simulated, fabricated and measured. The measurement results are in a good agreement with the simulations.     

Miniature Four-Way and Two-Way 24 GHz Wilkinson Power Dividers in 0.13 μm CMOS

This letter presents 24 GHz four-way and two-way miniature Wilkinson power dividers (PDs) in a standard CMOS technology. The chip area is significantly reduced using a lumped-element design, and the effective areas of four-way and two-way Wilkinson dividers are 0.33 times 0.33 mm² and 0.12 times 0.29 mm², respectively. The four-way Wilkinson divider results in an insertion loss <2.4 dB, an input/output return loss better 15.5 dB, and a port-to-port isolation >24.7 dB from 22 to 26 GHz. The two-way Wilkinson divider results in an insertion loss <1.4 dB, an input/output return loss better 8.9 dB, and a port-to-port isolation >14.8 dB from 22 to 26 GHz. To the author's knowledge, this is the first demonstration of 24 GHz four-way Wilkinson PD in a standard CMOS technology.     

Improved performance step impedance lowpass filter

Performances of the conventional Butterworth step impedance lowpass filters (LPF) are significantly improved by placing transmission zero either closer to the cut-off frequency (f_c) or away from it. It is achieved by using transverse resonance width of the capacitive line sections. We report method of designing transverse resonance type LPF (TR-LPF) for 5 to 11-pole filters. At f_c = 2.5 GHz, we obtained selectivity in the range 113.3–56.66 dB/GHz and 20–60 dB rejection BW in the range 9.61–7.29 GHz. The TR-LPF can suppress the stopband signal by 60 dB up to 5f_c. Insertion loss in passband is within 0.72 dB. Improved performance of TR-LPF can be designed for f_c up to 7.5 GHz.     

A wideband RF receiver with extended statistical element selection based harmonic rejection calibration

In this paper we present a wideband harmonic rejection (HR) RF receiver design. Both gain mismatch and phase mismatch of the HR mixer have been calibrated using a design and calibration method called extended statistical element selection to achieve best-in-class HR ratio (HRR) performance. The achieved concurrent 3rd order HRR and 5th order HRR are greater than 80 dB and 70 dB, respectively, after calibration. The even order HRR is also calibrated to greater than 80 dB. A single calibration performed at 750 MHz was further observed to be effective over more than two octaves of bandwidth with greater than 70 dB HRR. The receiver was manufactured in 65 nm CMOS technology. Input RF frequency range was 0.15–1 GHz and the receiver consumes 64 mW at 1 GHz. Noise figure is 3.2 dB and out-of-band IIP3 is −7 dBm at a total gain of 48 dB.     

A novel low power UWB cascode SiGe BiCMOS LNA with current reuse and zero-pole cancellation

A low power cascode SiGe BiCMOS low noise amplifier (LNA) with current reuse and zero-pole cancellation is presented for ultra-wideband (UWB) application. The LNA is composed of cascode input stage and common emitter (CE) output stage with dual loop feedbacks. The novel cascode-CE current reuse topology replaces the traditional two stages topology so as to obtain low power consumption. The emitter degenerative inductor in input stage is adopted to achieve good input impedance matching and noise performance. The two poles are introduced by the emitter inductor, which will degrade the gain performance, are cancelled by the dual loop feedbacks of the resistance-inductor (RL) shunt–shunt feedback and resistance-capacitor (RC) series–series feedback in the output stage. Meanwhile, output impedance matching is also achieved. Based on TSMC 0.35 μm SiGe BiCMOS process, the topology and chip layout of the proposed LNA are designed and post-simulated. The LNA achieves the noise figure of 2.3–4.1 dB, gain of 18.9–20.2 dB, gain flatness of ±0.65 dB, input third order intercept point (IIP₃) of ?7 dBm at 6 GHz, exhibits less than 16 ps of group delay variation, good input and output impedances matching, and unconditionally stable over the whole band. The power consumption is only 18 mW.     

Miniaturized active stepped impedance planar inverted-F antenna using common ground

This paper presents a compact active integrated antenna (AIA) comprising of class-A power amplifier (PA) and stepped impedance planar inverted-F antenna (PIFA). In the proposed design, a common ground is used for both PA and PIFA, resulting a compact antenna of size 0.14λ₀ × 0.11λ₀ × 0.01λ₀ (λ₀ is free space wavelength at 0.85 GHz). Moreover, it is demonstrated that by using the stepped impedance radiator the operating frequency of the active PIFA is shifted down from its natural resonant frequency of 1.36 GHz to 0.85 GHz, offering an extensive size reduction of 80%. This active integration increases the passive antenna gain through the effective loading of the antenna to the power amplifier. The measured result indicates that the active and passive antennas achieved the gain of 15.7 dB and 3.81 dBi, respectively after the integration. In addition, the maximum SAR value of antenna is found to be 0.64 W/kg.     

High-power continuous-wave operation of a fiber optical parametric oscillator in L and U bands

Fiber optical parametric oscillators (OPOs), based on a highly-efficient four-wave mixing process in a χ⁽³⁾ medium, are reviewed. Their capability to provide very large tuning ranges with high output power is discussed. A novel architecture for CW fiber OPOs is presented, which has allowed us to significantly extend the performance of these devices. To do so we used: (i) a highly-nonlinear fiber (HNLF) as the parametric gain medium; (ii) a narrowband tunable intracavity filter; (iii) a high output coupling fraction from the feedback loop (up to 3 dB). With these features, we have been able to obtain excellent performance in terms of output power and tuning range, even with a reduced pump power. With only about 2 W of pump power, we have obtained the following performances: (i) tuning range of 254 nm; (ii) output power in excess of 1 W at some wavelengths; (iii) external conversion efficiency in excess of 60% at some wavelengths; (iv) linewidth as low as 8 GHz.This architecture of fiber OPO can be used for providing narrow linewidth tunable high-power CW radiation over hundreds of nanometers. Such sources could find applications in remote sensing, optical communication, nonlinear optics, etc.