多元LDPC码串行译码算法在光纤通信中的应用

将串行BP译码算法用在多元LDPC码中,降低了在光纤传输系统中的译码延时.详细介绍了在多元LDPC码中的串行BP译码算法和光纤通信系统的仿真模型.给出了在采用串行BP算法的LDPC译码器中,译码最大迭代数量对译码性能的影响,比较了采用传统的BP算法扣串行BP算法时LDPC译码器的性能.结果表明,采用串行BP算法确实能够提升LDPC译码器的收敛速度.     

无短环不规则QC_LDPC码的快速编码及联合译码

基于不规则部分并行结构设计了一种高吞吐量,低复杂度,码长码率可变且去除四环的低密度奇偶校验LDPC码及其译码结构实现方案,该编码结构可针对不同码长的不规则部分并行结构LDPC码进行扩展,译码器采用缩放最小和定点(Sum-Min)算法实现译码,中间信息节点存储器地址采用格雷码编码,降低动态功耗;采用Xilinx公司的Virtex-5XC5Vt X150T-ff1156FPGA芯片设计了一款码长1 270,码率1 2的不规则部分并行LDPC码的编码器和译码器。综合结果表明:该编码器信息吞吐量为2.52 Gb/s,译码器在10次迭代的情况下信息吞吐率达到44 Mb/s。     

LDPC码的全并行概率译码

针对LDPC码和积译码算法运算量大、电路实现复杂度高,介绍一种新的LDPC译码实现结构——概率译码器。该结构结合随机运算思想,运算量大幅降低,电路布线实现压力减小,吞吐量显著提高,针对该算法的内部路由可能出现的死锁问题引入了边存储器（EM,Edge Memory）概念。在AWGN信道下,对上述方法进行了仿真验证,给出了新方案和旧算法的性能分析比较,结果显示该算法的性能相比传统LDPC译码器有近0.2 dB的性能损失,但译码复杂度得到显著降低。     

适用于BPSK系统的抗跳周LDPC译码算法

采用BPSK调制方式的系统发生跳周现象后,输入LDPC译码器的信息序列符号与原序列符号相反,导致译码器失效。提出了基于置信传播算法的抗跳周LDPC译码算法。该算法通过增加一次迭代译码的运算量,根据校验节点与变量节点之间传递的信息对初始似然比信息进行修正,可以消除跳周对译码器的影响。仿真结果表明在不发生跳周时,抗跳周LDPC译码算法与传统译码算法性能相同,即抗跳周LDPC译码算法对初始似然比信息的修正不会导致译码性能损失。在跳周发生时,传统译码算法失效。对校验节点奇数度的码字采用抗跳周译码算法可以完全克服跳周带来的影响,译码性能与无跳周发生时相同。     

基于FPGA的不可分层LDPC码译码器

针对不可分层LDPC码无法采用分层译码算法的问题,设计了一种新型的LDPC码分层译码器。与传统分层译码器的结构不同,新结构在各层间进行并行更新,各层内进行串行更新。通过保证在不同分层的同一变量节点不同时进行更新,达到分层译码算法分层递进更新的目标。选用Altera公司的CycloneⅢ系列EP3C120器件,实现码率3/4,码长8 192的(3,12)规则不可分层QC-LDPC码译码器的布局布线,在最大迭代次数为5次时,最高时钟频率可以达到45.44 MHz,吞吐量可以达到47.6 Mbps。     

同步部分并行结构的准循环LDPC码译码器

该文根据准循环LDPC码的结构特点,提出了一种同步部分并行结构的译码器。在译码器中,校验节点处理单元和变量节点处理单元同时并行工作,使得迭代过程中新产生的软信息能够被提前使用,加快迭代的收敛速度。同时,采用差分演化的方法对各节点处理单元的起始位置进行优化,进一步提高了译码器的性能。仿真结果表明,该方案在译码性能和复杂度上都要优于现有其他方案,适合高速译码器的实现。     

卷积LDPC码流水线译码器的改进方法

较高的译码复杂度和较长的初始译码时延是卷积LDPC码流水线译码器两个潜在的问题。本文提出一种通过在计算校验节点信息时引入乘积因子的方法降低各节点信息之间的相关性,从而提高译码效率,一定程度上降低了译码迭代次数。仿真结果表明,该译码算法缩短了译码器的初始时延,同时也降低了译码复杂度,从而使得译码器的性能得到改善。     

标准低密度奇偶校验码译码算法中量化结构

DVB-S2标准低密度奇偶校验码(LDPC)译码器在深空通信中面临着低复杂度、高灵活性及普适性方面的迫切需求。通过对LDPC译码算法中量化结构的研究,提出一种动态自适应量化结构的设计方法。该方法在常规均匀硬件量化的基础上,提出了修正化Min-Sum译码算法中的数据信息初始化及迭代译码的动态自适应量化结构,解决了DVB-S2标准LDPC码译码时存在的校验节点运算与变量节点运算之间的复杂度不平衡的问题,并由此提高了译码器的译码性能。实验证明,以DVB-S2标准LDPC码中码长为16 200,码率为1/2的为例,提供动态自适应量化结构与常规的均匀量化结构相比,节省硬件资源为4%。此外,动态自适应量化结构支持动态可配置功能,保证了DVB-S2标准LDPC译码器的灵活性及普适性。     

RS码与LDPC码的联合迭代译码

针对RS码与LDPC码的串行级联结构,提出了一种基于自适应置信传播(ABP)的联合迭代译码方法.译码时,LDPC码置信传播译码器输出的软信息作为RS码ABP译码器的输入;经过一定迭代译码后,RS码译码器输出的软信息又作为LDPC译码器的输入.软输入软输出的RS译码器与LDPC译码器之间经过多次信息传递,译码性能有很大提高.码长中等的LDPC码采用这种级联方案,可以有效克服短环的影响,消除错误平层.仿真结果显示:AWGN信道下这种基于ABP的RS码与LDPC码的联合迭代译码方案可以获得约0.8 dB的增益.     

CCSDS标准LDPC部分并行译码器实现

针对CCSDS标准中近地通信的LDPC码,为了提高准循环低密度奇偶校验（QC-LDPC）译码器的吞吐率和资源利用率,设计实现了一种低复杂度高速并行译码器。译码器整体采用流水线结构,通过改进校验节点与变量节点的更新方式,在不增加运算复杂度的情况下使信息处理所消耗的时间更短,压缩单次迭代所需时间,提高了译码器的吞吐量。以现场可编程门阵列（FPGA）作为实现平台,仿真并实现了基于归一化最小和算法的（8176,7154） LDPC译码器。结果表明,当译码器工作频率为200 MHz、迭代次数为10次的情况下,译码吞吐量可达到160 Mbit/s,满足大多数场景的应用需求。     

Design of low-density parity check codes for MIMO systems with doubly-iterative receivers

In this paper, the Multiple Input Multiple Output (MIMO) doubly-iterative receiver which consists of the Probabilistic Data Association detector (PDA) and Low-Density Parity-Check Code (LDPC) decoder is developed. The receiver performs two iterative decoding loops. In the outer loop, the soft information is exchanged between the PDA detector and the LDPC decoder. In the inner loop, it is exchanged between variable node and check node decoders inside the LDPC decoder. On the light of the Extrinsic Information Transfer (EXIT) chart technique, an LDPC code degree profile optimization algorithm is developed for the doubly-iterative receiver. Simulation results show the doubly-receiver with optimized irregular LDPC code can have a better performance than the one with the regular one.     

Overlapped message passing for quasi-cyclic low-density parity check codes

In this paper, a systematic approach is proposed to develop a high throughput decoder for quasi-cyclic low-density parity check (LDPC) codes, whose parity check matrix is constructed by circularly shifted identity matrices. Based on the properties of quasi-cyclic LDPC codes, the two stages of belief propagation decoding algorithm, namely, check node update and variable node update, could be overlapped and thus the overall decoding latency is reduced. To avoid the memory access conflict, the maximum concurrency of the two stages is explored by a novel scheduling algorithm. Consequently, the decoding throughput could be increased by about twice assuming dual-port memory is available.     

Low Complexity Decoder Architecture for Low-Density Parity-Check Codes

In this paper, we propose a low complexity decoder architecture for low-density parity-check (LDPC) codes using a variable quantization scheme as well as an efficient highly-parallel decoding scheme. In the sum-product algorithm for decoding LDPC codes, the finite precision implementations have an important tradeoff between decoding performance and hardware complexity caused by two dominant area-consuming factors: one is the memory for updated messages storage and the other is the look-up table (LUT) for implementation of the nonlinear function Ψ(x). The proposed variable quantization schemes offer a large reduction in the hardware complexities for LUT and memory. Also, an efficient highly-parallel decoder architecture for quasi-cyclic (QC) LDPC codes can be implemented with the reduced hardware complexity by using the partially block overlapped decoding scheme and the minimized power consumption by reducing the total number of memory accesses for updated messages. For (3, 6) QC LDPC codes, our proposed schemes in implementing the highly-parallel decoder architecture offer a great reduction of implementation area by 33% for memory area and approximately by 28% for the check node unit and variable node unit computation units without significant performance degradation. Also, the memory accesses are reduced by 20%.     

A scalable LDPC decoder ASIC architecture with bit-serial message exchange

We present a scalable bit-serial architecture for ASIC realizations of low-density parity check (LDPC) decoders. Supporting the architecture's potential, we describe a decoder implementation for a (256,128) regular-(3,6) LDPC code that has a decoded information throughput of 250 Mbps, a core area of 6.96 mm² in 180-nm 6-metal CMOS, and an energy efficiency of 7.56 nJ per uncoded bit at low signal-to-noise ratios. The decoder is fully block-parallel, with all bits of each 256-bit codeword being processed by 256 variable nodes and 128 parity check nodes that together form an 8-stage iteration pipeline. Extrinsic messages are exchanged bit-serially between the variable and parity check nodes to significantly reduce the interleaver wiring. Parity check node processing is also bit-serial. The silicon implementation performs 32 iterations of the min-sum decoding algorithm on two staggered codewords in the same pipeline. The results of a supplementary layout study show that the reduced wiring congestion makes the decoder readily scaleable up to the longer kilobit-size LDPC codewords that appear in important emerging communication standards.     

An Efficient Memory-Address Remapping Technique for High-Throughput QC-LDPC Decoder

This paper presents an efficient memory-address remapping technique for a high-throughput quasi-cyclic low-density parity check (QC-LDPC) decoder. In general, an LDPC decoder needs a large size of embedded memories for the temporal storage of the check node process (CNP) and variable node process (VNP) outputs. To increase the decoder throughput, overlapping the CNP and VNP operations is necessary; however, the parallel operations are mainly restricted by the embedded memory bandwidth. This work presents an efficient memory management approach in an LDPC decoder, where the memory-address conflicts and redundant memory-read operations are effectively reduced by using a proposed memory-address remapping technique. As a result, parallel variable node unit operations significantly increase, leading to higher throughput. When the proposed approach is applied to the various code rates of IEEE std. 802.16-2009, increases in decoding speed of up to 1.52X per iteration are achieved for overlapped message passing algorithm-based architecture, along with considerable reductions in the number of memory-read accesses. Using a 0.13- \(\upmu \) m CMOS process, a QC-LDPC decoder with multi-code rates is implemented, and the experimental results show that the proposed decoder achieves considerable throughput area ratio increase with energy savings compared to the conventional approaches.     

一种提高LDPC译码器吞吐率的译码算法

为了设计高效的LDPC译码器,结合准循环结构LDPC的校验矩阵H的规律性、乘性修正最小和译码算法不需要估计信道质量的特点和部分并行译码实现复杂度低的特点,介绍了一种新的译码算法——交迭的部分并行译码算法,这种译码算法相对于采用部分并行结构的BP译码算法,不但降低了硬件实现的复杂度,减少了存储资源的开销,而且提高了译码器的吞吐率。     

Configurable Multi-Rate Decoder Architecture for QC-LDPC Codes Based Broadband Broadcasting System

In this paper we present a Base-matrix based decoder architecture for multi-rate QC-LDPC codes proposed in broadband broadcasting system. We use the Modified Min-Sum Algorithm (MMSA) as the decoding algorithm in this architecture, which lowers the complexity of the LDPC decoder while keeping almost the same performance or even better. Based on this algorithm, we designed a novel check node processing unit to reduce the complexity of the decoder and facilitate the multiplex of the processing units. The decoder designed with hardware constraints is not only scalable in throughput, but also easily configurable to support different QC-LDPC codes flexible in code rate and code length.