Spatial distribution of interface traps in DeMOS transistors

The spatial distribution of interface traps in a p-type drain extended MOS transistor is experimentally determined by the analysis of variable base-level charge pumping spectra. The evolution of the interface trap distribution can be monitored as a function of the hot-carrier stress time. A double peaked interface trap density distribution, located in the spacer oxide, is extracted. The interface trap density in the poly overlapped drift region is constant as a function of stress time. No channel degradation is observed.     

New aspects and mechanism of kink effect in static back-gatetransconductance characteristics in fully-depleted SOI MOSFETs onhigh-dose SIMOX wafers

An extraordinary kink phenomenon in static back-gate transconductance characteristics of fully-depleted SOI MOSFETs has been experimentally investigated and characterized for the first time. This kink phenomenon has been observed in both NMOS and PMOS on high-dose SIMOX wafers under steady-state conditions at room temperature. It was also found that the back-gate characteristics for both NMOS and PMOS show anomalous shift phenomenon in drain current-back gate voltage (I _D-V_G2) curve at the back-gate voltage corresponding to the kink phenomenon. This kink phenomenon has been attributed to the presence of energetically-localized trap states at SOI/BOX interface. In order to clarify the energy level of the trap states at SOI/BOX interface corresponding to the kink, we have developed a new formula of surface potential in thin-film SOI MOS devices, in which the potential drop across semiconductor-substrate is taken into account. By using this new formula, me have demonstrated that high-dose SIMOX wafers have donor-like electron trap states at ~0.33 eV above the Si midgap with the density of ~N6.0~10¹² cm^-2 eV ^-1 and donor-like hole trap states at ~0.35 eV below the Si midgap with density of ~1.5×10¹² cm^-2 eV^-1 at SOI/BOX interface     

Chemical reaction concerns of gate metal with gate dielectric in Tagate MOS devices: an effect of self-sealing barrier configurationinterposed between Ta and SiO2

Chemical reaction of gate metal with gate dielectric for Ta gate MOS devices has been experimentally investigated both by electrical and physical measurements: capacitance-voltage (C-V), current-voltage (I-V), transmission electron microscopy (TEM), energy dispersive X-ray (EDX), electron diffraction measurements. In spite of the chemical reaction of Ta with SiO₂ consuming ~1-nm-thick in gate oxide, the interface trap densities of ~2×10¹⁰ cm^-2 eV ^-1 at midgap and ideal channel mobility characteristics have been observed in the Ta gate MOS devices with 5.5-nm-thick thermal oxide gate dielectric. Considering the experimental data with theoretical calculation based on thermodynamics together, a barrier layer model has been developed for the Ta gate MOS systems. The physical mechanism involved is probably self-sealing barrier layer formation resulting from the chemical reaction kinetics in the free-energy change of Ta-Si-O system     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

Frequency response of charge transfer in MOS inversion layers

The dynamics of charge transfer from a reservoir into an MOS inversion layer, which limits the frequency response of an MOS transistor or a charge-coupled device, is investigated. Using Berman and Kerr's model of space-charge capacitance in the semiconductor, a small-signal distributed model is developed for an MOS structure which transfers charge in an inversion channel due to a variation in the gate voltage. The dynamics of the charge transfer is characterized by a time constant which is determined by the length of the inversion channel and its mobility. Experimental data of gate capacitance vs frequency, taken from a test structure with a diffused source/drain well, are satisfactorily fitted by theoretical curves derived from the model. The channel mobility is precisely determined from the adjusted time constant. The influence of interface states on the capacitance-frequency relationship is also briefly discussed.     

Effect of oxide resistance on the characterization of interface trap density in MOS structures

The oxide resistance in a practical MOS capacitor is generally not high enough to be negligible in the evaluation of interface trap density based on the qruasi-static capacitance-voltage (C–V) curve. The importance of the effects of oxide resistance ranging from 10¹³ to 10¹⁶ Ω on the C–V curve and the corresponding interface trap density is theoretically shown. To obtain the oxide resistance in MOS structures the newly reported charge-then-decay method is suggested. From the oxide resistance found, one can compare the distribution curves of interface trap density before and after removing the oxide resistance effect. It is found that the results obtained after removing the oxide resistance effect are more consistent than those without removing it. It addition, the removal of the oxide resistance effect for a sample having a hysteresis C–V behavior is also discussed.     

Study of the Drain Leakage Current in Bottom-Gated Nanocrystalline Silicon Thin-Film Transistors by Conduction and Low-Frequency Noise Measurements

The drain leakage current in n-channel bottom-gated nanocrystalline silicon (nc-Si) thin-film transistors is investigated systematically by conduction and low-frequency noise measurements. The presented results indicate that the leakage current, controlled by the reverse biased drain junction, is due to Poole-Frenkel emission at low electric fields and band-to-band tunneling at large electric fields. The leakage current is correlated with single-energy traps and deep grain boundary trap levels with a uniform energy distribution in the band gap of the nc-Si. Analysis of the leakage current noise spectra indicates that the grain boundary trap density of 8.5 times 10¹² cm ^-2 in the upper part of the nc-Si film is reduced to 2.1 times 10¹² cm^-2 in the lower part of the film, which is attributed to a contamination of the nc-Si bulk by oxygen     

Origins and characterization of low-frequency noise in GaAsMESFET's grown on InP substrates

An experimental study of the low-frequency noise in GaAs MESFET's grown on InP substrates is reported. The influence of the biases applied to the gate, backgate, and drain in the ohmic region is investigated in order to identify and characterize the 1/f noise origin. We find that this noise can be explained by carrier number fluctuations in the channel and related to trapping phenomena. The traps responsible for this noise are located near the channel-buffer interface. Moreover, the noise behavior exhibits for a well-defined gate voltage, corresponding to the case where the drain current flows near the channel-buffer interface, a GR-type (Lorentzian) noise spectrum emerging from a quite general 1/f noise. This last spectrum corresponds to a single trap level with a density of N_T=10¹⁶ cm^-3 and a time constant τ=1.8 ms which may be attributed to crystal defects present in the GaAs layers     

Back-gated buried oxide MOSFETs in a high-voltage bipolartechnology for bonded oxide/SOI interface characterization

A novel back-gated P-MOSFET structure is fabricated in a high-voltage complementary bipolar technology using BESOI (bonded etch back SOI) substrates. The P+ buried layer regions, used for the PNP BJT are used as the source and drain regions, the N- epi as the channel region, the silicon handle wafer as the gate, and the BOX (buried oxide) as the gate oxide. The P-MOSFET was used to characterize the interface between the BOX and the SOI. The devices exhibit high sub-threshold slope which is attributed to a high interface state density of about 2×10¹²/cm² at the bonding interface. Bias-temperature stress measurements show an effective mobile charge density of 4×10¹⁰/cm² in the buried oxide     

Characterization of low 1/f noise in MOS transistors

By careful processing MOS transistors have been fabricated with a low value of the interface states density (2 × 10¹⁰/cm²eV). Consequently the1/fnoise in these devices is low and in the same order of magnitude as for junction FETs. The experimental values of the equivalent noise voltage and the equivalent noise current are compared to an expression derived from straight physical arguments. From the comparison it is concluded that the noise equivalent voltage in saturated operation is proportional to the effective gate voltage, the interface state density, and inversely proportional to the gate input capacitance. Moreover, it is concluded that a proper heat treatment not only reduces the number of states but also removes the near bandedge peaks, which usually appear in the trap distribution function.     

Enhancement mode InP MISFET's with sulfide passivation andphoto-CVD grown P3N5 gate insulators

High performance enhancement mode InP MISFET's have been successfully fabricated by using the sulfide passivation for lower interface states and with photo-CVD grown P₃N₅ film used as gate insulator. The MISFET's thus fabricated exhibited exhibited pinch-off behavior with essentially no hysteresis. Furthermore the device showed a superior stability of drain current. Specifically under the gate bias of 2 V for 10⁴ seconds the room temperature drain current was shown to reduce from the initial value merely by 2.9% at the drain voltage of 4 V. The effective electron mobility and extrinsic transconductance are found to be about 2300 cm ²/V·s and 2.7 mS/mm, respectively. The capacitance-voltage characteristics of the sulfide passivated InP MIS diodes show little hysteresis and the minimum density of interface trap states as low as 2.6×10¹⁴/cm² eV has been attained     

Gate and drain currents in off-state buried-type p-channel LDDMOSFETs

The buried-type p-channel LDD MOSFETs biased at high positive gate voltage exhibit novel characteristics: (1) the ratio of the drain to gate currents is about 1×10^-3 to 5×10^-3; and (2) the gate and drain currents both are functions of only the gate voltage minus the n-well bias. Such characteristics are addressed based on the formation of the surface n ⁺ inversion layer due to the punchthrough of the buried channel to the underlying shallow p-n junction. The measured gate current is due to the Fowler-Nordheim tunneling of electrons from this inversion layer surface and the holes generated within the high-field oxide constitute the drain current. The n⁺ inversion layer surface potential is found to be equal to the n-well bias plus 0.55 V. As a result, both the oxide field and the gate and drain currents are independent of drain voltage     

A high-speed buried channel MOSFET isolated by an implanted silicon dioxide layer

This paper describes a high-speed buried channel MOSFET dielectrically isolated from the substrate through the use of oxygen implantation technology. An implanted silicon dioxide layer is formed just beneath the surface. An n-type epitaxial layer is grown on the remaining thin single-crystal layer at the surface. Then, buried channel MOSFET's are formed on the n-type layer. The interface between the implanted SiO2and the upper silicon is abrupt, and the interface charge density is 6.9 × 10¹⁰cm^-2. The effective carrier mobility calculated from the drain conductance is 750 cm²/V . s. Leakage current which should be inherent in this device structure can not be observed. Submicron MOSFET's show much smaller threshold voltage shifts than conventional ones, and this agrees with the results of two-dimensional numerical calculation. A ring oscillator composed of MOSFET's with 1-µm channel length shows a minimum delay time of 95 ps and a power delay product of 310 fJ at VDDof 15 V.     

p-Channel MOS transistor in indium antimonide

A p-channel MOS transistor in InSb single crystal, operating at 77 K, is described. The source and drain are defined by etching a mesa structure in a cadmium diffused p layer into a tellurium-doped InSb substrate. The gate is formed by evaporation of chromium gold on top of a layer of SiO2, deposited at 215°C. The MOS transistor is characterized by a threshold voltage of -3 V and an effective hole mobility of 330 cm². V^-1.s^-1.     

Effects of deliberate copper contamination from the platingsolution on the electrical characteristics of MOSFETs

N-channel and p-channel metal-oxide-semiconductor (MOS) transistors of various (W/L) ratios down to 0.24-μm channel length have been used to investigate the effects of deliberate backside copper (Cu) contamination on the MOS field-effect transistor (MOSFET) electrical parameters. The backside of the wafer was flooded with copper sulphate (CuSO₄) solution and air-dried. High-temperature annealing was carried out to drive Cu into silicon. It was discovered that the backside Cu contamination did not result in any undesirable effects on the MOS device performance. The MOS device parameters such as threshold voltage V_TO, transconductance G_m, drain saturation current I_DSAT, off-current I_off, and junction leakage current for n⁺/p and p+/n diodes displayed no significant degradation, even after 5 h of annealing at 400°C in nitrogen ambient. Secondary ion mass spectroscopy data shows that Cu diffused into silicon only over a short distance, leading to little or no degradation of MOSFETs and junction diodes     

Interfacial electronic traps in surface controlled transistors

Carrier recombination at interfacial electronic traps under a surface controlling gate electrode is analyzed using the Shockley-Reed-Hall steady-state recombination kinetics to provide a theoretical basis for quantifying the direct-current current-voltage (DCIV) method for monitoring and diagnosis of MOS transistor reliability, design, and manufacturing processes. Analytical expressions for DCIV lineshape, linewidth, peak gate-voltage and peak amplitude are derived for the determination of interface trap densities, energy level, and spatial location. DCIV peaks in the intrinsic to flat band gate-voltage range originate from carrier recombination at interface traps located over the channel region. Additional peaks in the surface accumulation gate-voltage range originate from interface traps covering the gated p-n-junction space-charge region. Effects on the DCIV line shape from minority carrier injection level and diffusion are described. Examples are given for the determination of the quantum density of states of process-residual interface traps of unstressed MOS transistors as well as hot-carrier-generated interface traps of stressed MOS transistors     

Short-channel MOSFET VT-VDScharacteristics model based on a point charge and its mirror images

Short-channel MOS transistordV_{T}/dV_{DS}characteristics are expressed by an analytic function of fundamental device parameters. The expression is derived from a simple model of short-channel MOS transistors in threshold condition, which is based on a point charge and its mirror images. With this expression,dV_{T}/dV_{DS}is found to be proportional to1/L^{2}-1/L^{4}, whereLis channel length. Following factors are also found, wherein the source and drain junction depth effect is only logarithmic ondV_{T}/dV_{DS}characteristics,dV_{T}/dV_{SUB}anddV_{T}/dV_{DS}are closely related in short-channel MOS transistors, and short-channel effects are expected to be smaller in MOS transistors on SOS than on bulk silicon, due to a large number of Si/sapphire interface states. This model is simple, and it can be applied to short-channel MOS transistor designing and circuit simulations.     

Submicrometer Inversion-Type Enhancement-Mode InGaAs MOSFET With Atomic-Layer-Deposited Al2O3 as Gate Dielectric

High-performance inversion-type enhancement-mode n-channel In_0.53Ga_0.47As MOSFETs with atomic-layer-deposited (ALD) Al₂O₃ as gate dielectric are demonstrated. The ALD process on III-V compound semiconductors enables the formation of high-quality gate oxides and unpinning of Fermi level on compound semiconductors in general. A 0.5-mum gate-length MOSFET with an Al₂O₃ gate oxide thickness of 8 nm shows a gate leakage current less than 10^-4 A/cm² at 3-V gate bias, a threshold voltage of 0.25 V, a maximum drain current of 367 mA/mm, and a transconductance of 130 mS/mm at drain voltage of 2 V. The midgap interface trap density of regrown Al₂O₃ on In_0.53Ga_0.47As is ~1.4 x 10¹²/cm² ldr eV which is determined by low-and high-frequency capacitance-voltage method. The peak effective mobility is ~1100 cm² / V ldr s from dc measurement, ~2200 cm²/ V ldr s after interface trap correction, and with about a factor of two to three higher than Si universal mobility in the range of 0.5-1.0-MV/cm effective electric field.     

Examination of oxide damage during high-current stress of n-MOStransistors

Damage to n-channel MOSFETs under different levels of drain current stress is compared. It is shown that the post-stress I _d-V_gs characteristics show distinctly different behavior for different stresses. These differences are interpreted in terms of the location of the stress damage along the Si-SiO₂ interface. It is shown that damage from low drain current stress occurs at the Si-SiO₂ interface just inside the drain junction, under strong gate control. Damage from high drain current stress occurs at the Si-SiO₂ interface deeper inside the drain junction region, under weak gate control. The damage localization interpretation is supported by simulations and by localized Fowler-Nordheim injection experiments. It is further shown that at intermediate levels of drain current injection, the damage occurs at the Si-SiO₂ interface in both drain regions. The differences are explained in terms of the bipolar action at high drain current levels, which forces the channel charge away from the Si-SiO₂ interface at the drain junction edge     

High quality SiO2/Si interfaces of poly-crystallinesilicon thin film transistors by annealing in wet atmosphere

A new post-metallization annealing technique was developed to improve the quality of metal-oxide-semiconductor (MOS) devices using SiO ₂ films formed by a parallel-plate remote plasma chemical vapor deposition as gate insulators. The quality of the interface between SiO₂ and crystalline Si was investigated by capacitance-voltage (C-V) measurements. An H₂O vapor annealing at 270°C for 30 min efficiently decreased the interface trap density to 2.0×10¹⁰ cm^-2 eV^-1, and the effective oxide charge density from 1×10 ¹² to 5×10⁹ cm^-2. This annealing process was also applied to the fabrication of Al-gate polycrystalline silicon thin film transistors (poly-Si TFT's) at 270°C. In p-channel poly-Si TFT's, the carrier mobility increased from 60-400 cm² V^-1 s^-1 and the threshold voltage decreased from -5.5 to -1.7 V