An empirical evaluation of performance-memory trade-offs in timewarp

The performance of the Time Warp mechanism is experimentally evaluated when only a limited amount of memory is available to the parallel computation. An implementation of the cancelback protocol is used for memory management on a shared memory architecture, viz., KSR to evaluate the performance vs. memory tradeoff. The implementation of the cancelback protocol supports canceling back more than one memory object when memory has been exhausted (the precise number is referred to as the salvage parameter) and incorporates a non-work-conserving processor scheduling technique to prevent starvation. Several synthetic and benchmark programs are used that provide interesting stress cases for evaluating the limited memory behavior. The experiments are extensively monitored to determine the extent to which various factors may affect performance. Several observations are made by analyzing the behavior of Time Warp under limited memory: (1) Depending on the available memory and asymmetry in the workload, canceling back several memory objects at one time (i.e. a salvage parameter value of more than one) improves performance significantly, by reducing certain overheads. However, performance is relatively insensitive to the salvage parameter except at extreme values. (2) The speedup vs. memory curve for Time Warp programs has a well-defined knee before which speedup increases very rapidly with memory and beyond which there is little performance gain with increased memory. (3) A performance nearly equivalent to that with large amounts of memory can be achieved with only a modest amount of additional memory beyond that required for sequential execution, if memory management overheads are small compared to the event granularity. These results indicate that contrary to the common belief, memory usage by Time Warp can be controlled within reasonable limits without any significant loss of performance     

An evaluation of design trade-offs in a high-performance, media-on-demand server

We present a high-performance solution to the I/O retrieval problem in a distributed multimedia system. Parallelism of data retrieval is achieved by striping the data across multiple disks. We identify the components that contribute to media data-retrieval delay. The variable delays among these have a great bearing on the server throughput under varying load conditions. We present a buffering scheme to minimize these variations. We have implemented our model on the Intel Paragon parallel computer. The results of component-wise instrumentation of the server operation are presented and analyzed. Experimental results that demonstrate the efficacy of the buffering scheme are presented. Based on our experiments, a dynamic admission-control policy that takes server workloads into account is proposed.     

Software quality trade-offs: A systematic map

BackgroundSoftware quality is complex with over investment, under investment and the interplay between aspects often being overlooked as many researchers aim to advance individual aspects of software quality.AimThis paper aims to provide a consolidated overview the literature that addresses trade-offs between aspects of software product quality.MethodA systematic literature map is employed to provide an overview of software quality trade-off literature in general. Specific analysis is also done of empirical literature addressing the topic.ResultsThe results show a wide range of solution proposals being considered. However, there is insufficient empirical evidence to adequately evaluate and compare these proposals. Further a very large vocabulary has been found to describe software quality.ConclusionGreater empirical research is required to sufficiently evaluate and compare the wide range of solution proposals. This will allow researchers to focus on the proposals showing greater signs of success and better support industrial practitioners.     

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.     

Customizing floating-point units for FPGAs: Area-performance-standard trade-offs

The high integration density of current nanometer technologies allows the implementation of complex floating-point applications in a single FPGA. In this work the intrinsic complexity of floating-point operators is addressed targeting configurable devices and making design decisions providing the most suitable performance-standard compliance trade-offs. A set of floating-point libraries composed of adder/subtracter, multiplier, divisor, square root, exponential, logarithm and power function are presented. Each library has been designed taking into account special characteristics of current FPGAs, and with this purpose we have adapted the IEEE floating-point standard (software-oriented) to a custom FPGA-oriented format. Extended experimental results validate the design decisions made and prove the usefulness of reducing the format complexity.     

Robust high-order repetitive control: Optimal performance trade-offs

High-order repetitive control has previously been introduced to either improve the robustness for period-time uncertainty or reduce the sensitivity for non-periodic inputs of standard repetitive control schemes. This paper presents a systematic, semidefinite programming based approach to compute high-order repetitive controllers that yield an optimal trade-off between these two performance criteria. The methodology is numerically illustrated through trade-off curves for various controller orders and levels of period-time uncertainty. Moreover, existing high-order repetitive control approaches are shown to correspond to specific points on these curves.     

Design trade-offs in self-management technology: the HeartMan case

ABSTRACT

Health self-management technology has the potential to significantly improve the Quality of Life of patients suffering from chronic diseases. However, designing the technology involves numerous highly context-dependent design decisions. In this paper, we analyse a case study of self-monitoring technology in the field of congestive heart failure. We analyse the design process of the technology from the perspective of design trade-offs. Three important trade-offs related to health self-monitoring technology are described in detail, related to patient autonomy, technology appropriation, and patient well-being. For each of the trade-offs, various mediating factors that influence design decisions are described in detail. On a practical level, this analysis can inform future developments in self-management technology. In addition, this design trade-off analysis provides intermediary knowledge that can contribute to a better theoretical understanding of health self-management technology.     

Energy trade-offs analysis using equal-energy maps

Energy consumption has become a factor limiting further progress of supercomputing. Grasping the relationships determining the transformation of energy into computations is often difficult. Therefore, we propose a new method of visualizing the relationships as two-dimensional maps similar to isotherms or isobars in weather maps. Complex models of energy consumption are projected onto two-dimensional maps with isolines representing points of equal energy consumption. As an illustration of the concept, we present isoenergy maps for three models of parallel computations. The first two models are derived from Amdahl’s and Gustafson’s laws of parallel performance. The third model applies to divisible loads representing data-parallel computations in distributed systems. Equal-energy maps for the three models provide qualitative and quantitative insights into the interactions between certain energy-saving approaches, and their consequent limitations.     

Computing trade-offs in robust design: Perspectives of the mean squared error

Researchers often identify robust design as one of the most effective engineering design methods for continuous quality improvement. When more than one quality characteristic is considered, an important question is how to trade off robust design solutions. In this paper, we consider a bi-objective robust design problem for which Pareto solutions of two quality characteristics need to be obtained. In practical robust design applications, a second-order polynomial model is adequate to accommodate the curvature of process mean and variance functions, thus mean-squared robust design models, frequently used by many researchers, would contain fourth-order terms. Consequently, the associated Pareto frontier might be non-convex and supported and non-supported efficient solutions needs to be generated. So, the objective of this paper is to develop a lexicographic weighted-Tchebycheff based bi-objective robust design model to generate the associated Pareto frontier. Our numerical example clearly shows the advantages of this model over frequently used weighted-sums model.     

Time-space trade-offs for compressed suffix arrays

Given a binary string of length n, we give a representation of its suffix array that takes O(nt(lgn)^1/t) bits of space such that given i,1?i?n, the ith entry in the suffix array of the string can be retrieved in O(t) time, for any parameter 1?t?lglgn. For t=lglgn, this gives a compressed suffix array representation of Grossi and Vitter [Proc. Symp. on Theory Comput., 2000, pp. 397-406]. For t=O(1/ε), this gives the best known (in terms of space) compressed suffix array representation with constant query time. From this representation one can construct a suffix tree structure for a text of length n, that uses o(nlgn) bits of space which can be used to find all the k occurrences of a given pattern of length m in O(m/lgn+k) time. No such structure was known earlier.     

Performance trade-offs for microprocessor cache memories

Design trade-offs for integrated microprocessors caches are examined. A model of cache utilization is introduced to evaluate the effects on cache performance of varying the block size. By considering the overhead cost of sorting address tags and replacement information along with data, it is found that large block sizes lead to more cost-effective cache designs than predicted by previous studies. When the overhead cost is high, caches that fetch only partial blocks on a miss perform better than similar caches that fetch entire blocks. This study indicates that lessons from mainframe and minicomputer design practice should be critically examined to benefit the design of microprocessors     

Fundamental trade-offs in aggregate packet scheduling

In this paper, we investigate the fundamental trade-offs in aggregate packet scheduling for support of guaranteed delay service. In our study, we consider two classes of aggregate packet scheduling algorithms: the static earliest time first (SETF) and dynamic earliest time first (DETF). Through these two classes of aggregate packet scheduling (and together with the simple FIFO packet scheduling algorithm), we show that, with additional timestamp information encoded in the packet header for scheduling purposes, we can significantly increase the maximum allowable network utilization level, while, at the same time, reducing the worst-case edge-to-edge delay bound. Furthermore, we demonstrate how the number of the bits used to encode the timestamp information affects the trade-off between the maximum allowable network utilization level and the worst-case edge-to-edge delay bound. In addition, the more complex DETF algorithms have far superior performance than the simpler SETF algorithms. These results illustrate the fundamental trade-offs in aggregate packet scheduling algorithms and shed light on their provisioning power in support of guaranteed delay service.     

Analyzing packaging trade-offs during system design

Integrating packaging trade-off analysis with functional verification and architectural design results in a complete virtual prototyping solution far optimizing complex electronic systems. The authors discuss the role of packaging costs in system design and present examples highlighting packaging design trade-offs     

Approximation trade-offs in a Markovian stream warehouse: An empirical study

A large amount of the world's data is both sequential and low-level. Many applications need to query higher-level information (e.g., words and sentences) that is inferred from these low-level sequences (e.g., raw audio signals) using a model (e.g., a hidden Markov model). This inference process is typically statistical, resulting in high-level sequences that are imprecise. Once archived, these imprecise streams are difficult to query efficiently because of their rich semantics and large volumes, forcing applications to sacrifice either performance or accuracy. There exists little work, however, that characterizes this trade-off space and helps applications make an appropriate choice.In this paper, we study the effects – on both efficiency and accuracy – of various stream approximations such as ignoring correlations, ignoring low-probability states, or retaining only the single most likely sequence of events. Through experiments on a real-world RFID data set, we identify conditions under which various approximations can improve performance by several orders of magnitude, with only minimal effects on query results. We also identify cases when the full rich semantics are necessary. This study is the first to evaluate the cost vs. quality trade-off of imprecise stream models.We perform this study using Lahar, a prototype Markovian stream warehouse. A secondary contribution of this paper is the development of query semantics and algorithms for processing aggregation queries on the output of pattern queries—we develop these queries in order to more fully understand the effects of approximation on a wider set of imprecise stream queries.     

Beyond the trade-offs on Facebook: the underlying mechanisms of privacy choices

The theory of privacy calculus in terms of the trade-offs between benefits and risks is believed to explain people’s willingness to disclose private information online. However, the phenomenon of privacy paradox, referring to the preference-behavior inconsistency, misfits the risk–benefit analysis. The phenomenon of privacy paradox matters because it reflects an illusion of personal control over privacy choices. The anomaly of privacy paradox is perhaps attributed to cognitive heuristics and biases in making privacy decisions. We consider the stability-instability of privacy choices is better used to explain the underlying mechanisms of paradoxical relationship. A rebalanced trade-off, referring to the embeddedness of “bridging” and “bonding” social support in privacy calculus, is derived to develop the risk–benefit paradigms to explain the underlying mechanisms. In this study we address the underlying mechanisms of privacy choices in terms of self-disclosure and user resistance. To test the hypotheses (or mechanisms) of the research model, we developed the instrument by modifying previous scales. A general sample of 311 experienced Facebook users was collected via online questionnaire survey. From the empirical results, perceived benefits based on information support rather than emotion support can motivate self-disclosure willingness. In contrast, privacy risks rather than privacy concerns inhibit the willingness to disclose private information. The risk–benefit paradigms instead of the imbalanced trade-offs help to explain the instability of privacy choices where privacy calculus sticks with the stability view. Implications for the theory and practice of privacy choices are discussed accordingly.

     

Evaluating early prototypes in context: trade-offs, challenges, and successes

We would like to say that experience prototyping and Wizard of Oz prototyping, taken together, constitute a suitable alternative to true contextual evaluation for early prototypes, one gaining realism at the expense of impartiality, the other impartiality at the expense of realism. As our experiences show, however, each pervasive application design poses unique challenges that you must consider when applying these approaches. Regardless, it's often a good trade-off to sacrifice some measure of realism to evaluate early prototypes. Evaluation of early pervasive computing prototypes in context is a pragmatic exercise, but one that is nonetheless informed by general approaches that reflect and adapt to the challenges of pervasive application development.     

Performance and robustness trade-offs in PID control

Control design is a rich problem which requires consideration of many issues such as load disturbance attenuation, set-point tracking, robustness with respect to process variations and model uncertainty, and effects of measurement noise. The purpose of this paper is to provide insight into the trade-offs between performance and robustness explicitly. This is accomplished by introducing plots that show the trade-offs for PI and PID control. These also provide valuable understanding of design compromises used for common PI design methods.