可工作于77 K低温下的CMOS缓冲器

设计了用于制冷型红外读出电路系统的输出缓冲器,该缓冲器能在读出电路5 MHz的读出速度下驱动约20 pF的电容,可以在低温77 K下工作。对运放的增益,频率特性等进行了详细地阐述,并考虑了低温77 K时MOSFET参数的变化带来的影响。最后,给出了修改CMOS常温模型参数后的仿真结果,芯片采用0.35μm,3.3 V CMOS工艺实现,并给出了77 K下的测试结果,满足红外读出电路系统要求。     

可重构的低温共烧陶瓷电容高频等效电路模型

低温共烧陶瓷电容元件在微波多芯片组件设计中具有重要地位,其模型是系统仿真的关键.根据电容的物理结构特点,提出了一个可重构的高频电容模型,并给出其模型参数的计算公式.最后用ADS对双层电容和四层电容等效电路模型的S参数和用三维电磁场仿真软件的仿真结果做了对比,结果表明,其双层电容等效电路模型可以准确到4 GHz,其四层电容等效电路模型可以准确到2 GHz.采用等效电路的仿真时间比三维电磁场仿真软件约快60倍.     

硅低温双极晶体管的数值模拟

本文讨论了有关低温双极器件模拟物理参数的低温模型和各种低温物理效应,确立了适用于低温双极器件模拟的数值分析方法,建立了适用于77-300K温度范围内硅双极器件模拟程序,最后模拟分析了一典型结构品体管的常温和低温时的工作特性。     

基于BSIM3的低温MOSFET模型及参数提取

器件模型作为工艺与设计之间的接口,对保证集成电路设计成功具有决定意义.本文介绍了BSIM3模型的原理,并完成了低温下(77K) BSIM3模型的参数提取.同时探讨了使用参数提取软件的具体工作步骤.     

LTCC中埋置电容的参数提取及特性分析

为分析低温共烧陶瓷基板中埋置电容的特性,采用三维电磁场软件HFSS对埋置电容进行了建模和仿真.根据仿真结果,采用一种新方法进行参数提取,并用电路设计软件Ansoft Designer对参数进行优化.特性分析结果表明新的埋置电容结构可以提高电容特性.     

NMOS低温热载流子晶体管的解析研究

利用低温(77-295K)短沟NMOSFET准二维解析模型,研究了77-295K温区NMOSFET衬底电流相关的物理机制。发现沟道电子平均自由程不随温度而改变,其值约为7.6nm;低温下虽然沟道电子在漏端获得较高的能量,但由于碰撞电离减弱,使NMOSFET的衬底电流不随温度降低而显著增长。实验结果证明,提出的衬底电流机制和模型适用于77-295K宽温区范围。     

基于LTCC工艺的低通滤波器设计与实现

为了实现具有高Q值电容电感的小型化滤波器,本文采用低温共烧陶瓷(LTCC)工艺分别构建了垂直螺旋式电感和垂直直插式电容,利用电容电感的参数提取公式并结合HFSS软件进行优化仿真,获得具有高Q值的电容电感模型,并根据此模型来设计一款DC-500MHz小型化低通滤波器。最终经过实际测试结果表明该低通滤波器性能为：在0~500MHz插入损耗优于-0.5dB,回波损耗优于-18dB,带外抑制在1GHz处有-30dB,在1.5GHz处有-50dB。 关键词：低通滤波器;低温共烧陶瓷工艺;高Q值;小型化     

GaAs MIM电容模型

阐述了无源元件在MMIC设计中的重要性及MIM电容模型参数提取的几种方法.以简化的MIM电容等效电路为基础,通过IC-CAP建模软件,建立平板电容的等效模型模拟其电学特性.根据实测数据提取相关模型参数,同时与实际测试的MIM电容值进行对比,对ADS元件库中电容模型的关键参数做了修改和验证.经过在GaAs工艺线实际流片统计、验证,该模型在40 GHz以下实测的S参数与电磁仿真结果基本吻合,平板电容的误差控制在3%以内,可用于40 GHz以下CaAs MMIC的电路设计和仿真.     

一种深低温环境LVDS驱动电路

研究了深低温环境下MOS管与LVDS驱动电路的工作特性。与常温环境相比,LVDS电路在77 K环境下的输出电流更大,导致输出差分信号幅值增大。MOS管在77 K低温环境下的载流子迁移率为常温下的3倍,导致器件电流增大。根据低温条件下器件变化特性的数据分析结果,调节电路结构与器件参数,设置多档可调参考电流,并调节LVDS输出信号于标准范围内。采用标准0.35 μm CMOS工艺进行流片验证。结果表明,LVDS驱动电路在77 K环境下工作时,共模电平为1.2 V,电压摆幅为400 mV。     

35K CMOS器件LDD结构的SPICE宏模型

针对BSIM3v3模型在35K低温下无法模拟LDD(轻掺杂漏区)所引起的串联电阻异常,提出了可以模拟这一异常的SPICE宏模型.通过修改CMOS器件常温BSIM3v3模型中的一些与温度有关的参数值,得到35K BSIM3v3模型.模拟结果表明,根据此模型进行参数提取后的Ⅰ-Ⅴ特性曲线与实测曲线十分吻合.最后,运用此模型对CMOS传输门和两级运算放大器进行仿真,结果表明LDD串联电阻效应对这些电路产生了重要影响,该模型明显提高了低温BSIM3v3的仿真精度.     

平行板式静电微执行器动态Pull-in现象分析

基于求不考虑边缘电容的静电微执行器动态Pull-in参数的能量分析法,并结合边缘电容的模型推导出考虑边缘电容情况下静电微执行器的动态Pull-in参数的计算方法。将不考虑边缘电容条件下的静电微执行器的动态Pull-in参数和考虑边缘电容条件下的静电微执行器的动态Pull-in参数进行比较,得到这两种条件下静电微执行器的动态Pull-in参数的不同以及边缘电容对静电微执行器动态Pull-in参数的影响:考虑边缘电容的Pull-in电压小于不考虑边缘电容的Pull-in电压;在边缘电容模型下,平行板长度的变化对Pull-in电压的影响很大,但是对Pull-in位移却没有影响,平行板宽度的变化对Pull-in电压的影响较小,但是对Pull-in位移的影响很大。     

FDTD法研究散热片与器件间的耦合电容

散热片与器件间的电容耦合是电路产生共模辐射的主要原因之一，其对研究电路的辐射发射特别重要。然而长期以来人们将该电容简化为平板电容，采用静电场推导的电容公式计算。但在高频端，散热片和器件的尺寸与波长相比拟，分布参数影响了该耦合电容的数值。所以本文提出了采用FDTD法计算散热片与器件间的高频耦合电容的构想。数值计算的结果表明：该电容已经不能看作是一简单常数，而是随频率变化的量。频率较低时，耦合电容随频率升高快速减小。且耦合电容具有频率选择性。激励源位于散热片的中心耦合电容小；绝缘层厚度越薄，相对介电常数越大得到的高频耦合电容越大，但不是线性变化。在实际散热片的选择和安装过程前必须对其产生的耦合电容进行预测，以期在最实用的条件下得到最小的耦合电容。     

Design of Class E Amplifier With Nonlinear and Linear Shunt Capacitances for Any Duty Cycle

One of the main advantages of class E amplifiers for RF and microwave applications relies on the inclusion of a shunt capacitance in the tuned output network. At high frequencies, this capacitance is mainly provided by the output parasitic capacitance of the device with perhaps a linear external one for fine adjustments. The device's output capacitance is nonlinear and this influences the design parameters, frequency limit of operation, and performance of the class E amplifier. This paper presents a design method for the class E amplifier with shunt capacitance combining a nonlinear and linear one for any duty cycle, any capacitance's nonlinear dependence parameters, and any loaded quality factor of the tuned network. Nonlinear design with possibly different duty cycles is of relevance to maximize power or, alternatively, frequency utilization of a given device. Experimental, simulated, and compared results are presented to prove this design procedure     

Analysis of Geometry-Dependent Parasitics in Multifin Double-Gate FinFETs

This paper analyzes the geometry-dependent parasitic components in multifin double-gate fin field-effect transistors (FinFETs). Parasitic fringing capacitance and overlap capacitance are physically modeled as functions of gate geometry parameters using a conformal mapping method. Also, a physical gate resistance model is presented, combined with parasitic capacitive couplings between source/drain fins and gates. The effects of geometrical parameters on FinFET design under different device configurations are thoroughly studied     

Capacitance of Parallel Rectangular Plates Separated by a Dielectric Sheet

To determine the capacitance between two rectangular parallel plates separated by a dielectric sheet, the charge distribution on the plates is formulated in terms of a Fredholm integral equation of the first kind. This equation is solved numerically by a projective method using polynomial approximants. The resulting capacitance values are given in normalized graphical form, permitting capacitance determination for any practical values of dielectric constant and geometric parameters to within a few percent.     

串联电容的静电驱动微执行器的动态Pull-in模型

在MEMS执行器的设计中,求出准确的pull-in参数是至关重要的.在过去的研究中,在准静态假设下,电压控制的MEMS微执行器的pull-in模型已经被提出,并且还提出了一些拓宽微执行器稳定行程的方法.在动态条件下,电压控制的MEMS微执行器的pull-in模型也已经被提出.但是,还没有人研究如何提高微执行器动态稳定行...     

Test structure measuring inter- and intralayer coupling capacitance of interconnection with subfemtofarad resolution

We present a new test structure measuring inter- and intralayer coupling capacitance parasitic to the same target interconnection with subfemtofarad resolution. The coupling capacitance as well as fringing capacitance measured by the test structure are demonstrated for two-level copper interconnections used in 90-nm technology node. In addition, we demonstrate that the accuracy of layout parameters extraction is improved by nondestructive inverse modeling of a copper interconnect cross-sectional structure, which reproduces the pitch dependence of the measured inter- and intralayer coupling capacitance within about a 1% error.     

Theoretical modification of the negative Miller capacitance during the switching transients of IGBTs

The insulated gate bipolar transistor (IGBT) has negative Miller capacitance during switching transients. It has conventionally been attributed to the voltage dependency of the Miller capacitance. However this explanation has physical ambiguity, yet, it lacks a discussion of the conditions for the occurrence of negative Miller capacitance as well. We argue that it is the current dependence to the Miller capacitance that results in the negative case. In this paper, we provide a modification to the theoretical analysis of this phenomenon. The occurrence condition for it and the device parameters about it are discussed. It is discovered that the negative Miller capacitance must occur during the turn-off process for any IGBT, while it is relatively difficult during the turn-on process. At the device design level, the current gain of the PNP transistor in the IGBT is an important factor for the negative Miller capacitance.     

Small-signal nonlinear curcuit model of GaAs MESFET

Simple analytical expressions are derived for the drain-to-gate feedback capacitance, for the gate-to-source input capacitance, for the equivalent domain capacitance and the equivalent domain resistance for a GaAs metal-semiconductor field-effect transistor (MESFET). The equivalent circuit parameters are related to the material parameters such as the doping density, the dielectric constant, the low-field mobility, the diffusion coefficient, the built-in voltage and to the design parameters such as the gate length, the gate periphery, the active layer thickness, etc. The results which are in good agreement with the results of Willing et al. [4] may be used for a computer-aided design of GaAs power amplifiers and logic circuits.     

石英音叉陀螺等效参数的测量与分析

分析了石英音叉陀螺连接电路中采样电阻的等效电容(电容特性)对测试的影响,求出了陀螺等效参数,找出了理想工作点.根据陀螺连接电路,针对考虑和不考虑采样电阻的等效电容两种情况进行建模,利用基于初等反射阵(Householder矩阵)变换的最小二乘法求出陀螺两组等效参数,通过仿真对比说明了采样电阻的等效电阻对测试结果有影响,测试中必须考虑.通过求得的参数进行仿真研究,说明了陀螺的真实串联谐振频点为陀螺的理想工作点.