Long term storage reliability of antifuse field programmable gate arrays

Field Programmable Gate Arrays (FPGA) with antifuse elements are preferred in aerospace applications due to their non-volatility and demonstrated radiation hardness. Because aerospace applications typically involve long operating life, there is a requirement to store un-programmed antifuse FPGA parts for long periods and program them when necessary to support the system. No study on the long term reliability of un-programmed antifuse FPGAs in the storage environment is reported in literature. In this paper, antifuse structures, programming process, and failure mechanisms of antifuse FPGAs are discussed. A failure modes, mechanisms and effects (FMMEA) analysis was performed for storage conditions and critical failure mechanisms were identified. High temperature storage tests of a select number of antifuse FPGAs were performed to accelerate the identified failure mechanisms. These parts were subsequently programmed and yield data was analyzed to determine the effects of high temperature storage.     

Antifuse field programmable gate arrays

An antifuse is an electrically programmable two-terminal device with small area and low parasitic resistance and capacitance. Field-programmable gate arrays (FPGAs) using antifuses in a segmented channel routing architecture now offer the digital logic capabilities of an 8000-gate conventional gate array and system speeds of 40-60 MHz. A brief survey of antifuse technologies is provided. the antifuse technology, routing architecture, logic module, design automation, programming, testing and use of ACT antifuse FPGAs are described. Some inherent tradeoffs involving the antifuse characteristics, routing architecture and logic module are illustrated     

基于星地链路的FPGA在轨可重构设计

随着信号处理算法的发展,人们对航天用现场可编程门阵列（Field Programmable Gate Array, FPGA）提出了算法可更新的需求。而传统的固定算法模式已经无法满足要求,所以星上FPGA在轨可重构设计成为了解决这一问题的关键。提出了一种基于星地链路的FPGA在轨可重构设计方案。通过星地链路上载配置数据并将其存入电可擦除只读存储器（Electrically Erasable Programmable Read Only Memory, EEPROM）内,然后利用反熔丝器件对FPGA进行大规模算法重配置操作。这项设计方案已经通过了相关验证,同时也提升了星载FPGA的灵活性。     

DA算法结构改进及其实现

在FPGA的DSP处理中，传统上基于FPGA查找表(LUT)算法在关键通道上存在一个或多个进位传播链，对速度性能形成较大影响。就如何减小或取消FPGA上基于LUT的DA算法关键通道上进位传播作探讨，并提出新的算法，这种方法大大加速了基于DA算法的DSP处理，有较高的性价比。     

A regular fabric design methodology for applications requiring specific layout-level design rules

Regular fabrics have been introduced as an approach to bridge the gap between ASICs and FPGAs in terms of cost and performance. Indeed, compared to an ASIC, by predefining most of the manufacturing masks, they highly reduce time-to-market, non-recoverable engineering costs and lithography hazards. Also, thanks to hardwired configuration and interconnections their performance is closer to those of ASICs than those of FPGAs. They are therefore well suited to many applications requiring low to medium volume applications or higher performance than those provided by FPGAs.In this paper, we evaluate the interest of using a regular fabric to reduce time and design cost significantly in applications involving specific transistor level design (radiative/spacial conditions, side-channel attacks, NMR environment, etc.). With this aim in view, after a broad state of the art overview with an emphasis on architectures and design flows, we develop our approach of a regular fabric designed to limit layout level design, ad-hoc tools and technological migration cost. Then, we evaluate its performance in a 65 nm process versus FPGA and standard cell based ASIC implementations. For sequential designs, our proposed solution is on average 2.5×slower and 2.3×bigger than a standard cell implantation, but also on average 13×faster than a FPGA.     

用于可编程器件的MTM反熔丝特性研究

基于ONO（Oxide-Nitride-Oxide）和MTM（Metal-to—Metal）反熔丝技术的可编程存储及逻辑器件已经广泛应用于空间技术中。MTM反熔丝以其单元面积小、集成度高、反熔丝电容小和编程后电阻小等优势,更加适合深亚微米集成电路。文章通过制备MTM反熔丝单元,对单元的击穿特性和漏电性能展开研究,给出了反熔丝单元漏电流与单元尺寸的关系,对单元的编程电流和编程后的电阻值关系进行了研究,与文献[1]给出的Ron=Vf/Ip的关系基本一致。     

Vertical p-i-n polysilicon diode with antifuse for stackable field-programmable ROM

A field-programmable, stackable memory cell using 0.15-/spl mu/m technology is demonstrated. Vertical polycrystalline silicon diodes are stacked on top of one another, with tungsten (with TiN adhesion film) interconnect wires. An SiO/sub 2/ antifuse film separates the top of each diode from the TiN-W films. The cell is programmed when sufficient biasing voltage is applied to break down the antifuse, connecting the diode to tungsten. The cell is unprogrammed when the antifuse is intact. Cell fabrication and performance are described.     

Path reuse-aware routing for non-volatile memory based FPGAs

Non-volatile memory-based FPGAs (NV-FPGAs) are expected to replace traditional SRAM-based FPGAs to achieve higher scalability and lower power consumption. Yet the slow write performance of NVMs not only challenges FPGA reconfiguration speed and overhead but also constrains the programming cycles of FPGAs. To efficiently configure switch boxes, the majority component of an FPGA, this paper presents a routing path reuse technique. The reconfiguration cost of routing resources is first modeled mathematically and then minimized through a reuse-aware routing algorithm, which is incorporated into the standard VTR CAD tool. Experiments on standard MCNC and Titan benchmarks show that the proposed scheme is able to achieve as much as 58% path reuse rate and reduce as much as 45% configuration cost for routing resources.     

Metro-on-FPGA: A feasible solution to improve the congestion and routing resource management in future FPGAs

Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.     

FPGA-based digit-serial CSD FIR filter for image signal format conversion

This paper proposes the FPGA implementation of the digit-serial Canonical Signed-Digit (CSD) coefficient FIR filters which can be used as format conversion filters in place of the ones employed for the MPEG2 TM 5 (test model 5). Canonical representation of a signed digit (CSD) is a method used to reduce cost by representing a signed number using the least amount of non-zero digits, thereby reducing the number of multiply operations. As Field Programmable Gate Arrays (FPGAs) have grown in capacity, improved in performance, and decreased in cost, they are becoming a viable solution for performing computationally intensive tasks, with the ability to tackle applications formerly reserved for custom chips and programmable digital signal processing (DSP) devices. A digit-serial CSD FIR filter design is realized and practical design guidelines are provided using FPGAs. An analysis of the performance comparison of bit-serial, serial distributed arithmetic, and digit-serial CSD FIR filters on a Xilinx XC4000XL-series FPGA is described. The results show that the proposed digit-serial CSD FIR filter is compact and an efficient implementation of real-time DSP applications on FPGAs.     

High-performance metal/silicide antifuse [for CMOS technology]

A low-programmed-resistance low-thermal-budget, high-performance metal/silicide antifuse is reported. The programmed ON-State resistance of the metal/silicide antifuse is around 60 Ω, which is a factor of 10 less than that of Si-based antifuses (poly/n⁺ and poly/poly). Metal/silicide antifuses also eliminate the nonlinear ON-state resistance seen in Si-based antifuses. Programming of the antifuse can be done in 2 ms at 14 V, which is comparable to Si-based antifuses. Both ON- and OFF-state reliability of the metal/silicide antifuse are shown to be satisfactory     

Scaled dielectric antifuse structure for field-programmable gatearray applications

A scaled antifuse structure consisting of a nitride-oxide (NO) dielectric sandwiched between two polysilicon layers is presented. In addition to reducing the effective thickness of the antifuse dielectric, the current conduction asymmetry of the NO layer is also utilized to lower the breakdown voltage to 10.6 V, and consequently the programming voltage to 13.5 V, which is lower than that of previously reported antifuse structures. Time-dependent dielectric breakdown (TDDB) measurements verify that this scaled antifuse structure exhibits a lifetime exceeding ten years (>1×10¹² s) at 5.5 V in the unprogrammed state. Since a significant fraction of the total measured antifuse resistance is contributed by the sheet resistance of the polysilicon electrodes, this structure also demonstrates the reduction of this resistance component through silicidation of both top and bottom electrodes in the area outside of the antifuse. This poly-poly antifuse structure offers reduction in programmed voltage, reduction in silicon device area, simple peripheral circuitry design, and faster circuit operation due to lower capacitance than previous poly-N⁺ antifuse structures     

反熔丝型FPGA编程方法的研究

在传统的基于反熔丝可编程逻辑阵列结构的基础上,提出一种新颖的寻址编程方法.该方法通过增加额外的编程支路,减小反熔丝单元被编程后的电阻;编程前,对所有布线通道进行预充电,防止反熔丝单元被误编程.仿真和测试结果表明,与传统的编程方式相比,该方法提高了编程的可靠性.     

Write-once diode/antifuse memory element with a sol-gel silica antifuse cured at low temperature

A write-once programmable memory element is based on a spin-coated sol-gel silica antifuse layer cured at 100/spl deg/C. This antifuse is integrated with a thin-film silicon diode deposited at 160/spl deg/C by hot-wire chemical vapor deposition. When a 3 to 5 V electrical pulse is applied across a diode/antifuse element, the silica breaks down suddenly and the current passing through the element increases irreversibly by more than about 10/sup 4/. The on-state exhibits a diode-like current-voltage characteristic with a forward-reverse asymmetry of nearly 100 at 1 V and is stable if there was hexamethyldisilazane treatment of the wet-gel film before curing.     

A sublithographic antifuse structure for field-programmable gatearray applications

The authors demonstrate an antifuse structure with a cell area of 0.2×0.2 μm² which is fabricated by using the vertical sidewall of a polysilicon interconnect layer and two-mask patterning and etching steps. The antifuse is constructed in such a way that its vertical dimension is determined by the thickness of the polysilicon layer, and its horizontal dimension is determined by two-mask patterning and etching steps. For a conventional contact-hole type of structure, a 0.2-μm lithographic capability would be required to achieve the same antifuse cell size. It is also demonstrated that the time-dependent dielectric breakdown (TDDB) reliability of this sidewall antifuse is as good as that of a conventional planar contact-hole antifuse     

Scheduling Hardware-Accelerated Cloud Functions

This paper presents a Function-as-a-Service (FaaS) approach for deploying managed cloud functions onto heterogeneous cloud infrastructures. Current FaaS systems, such as AWS Lambda, allow domain-specific functionality, such as AI, HPC and image processing, to be deployed in the cloud while abstracting users from infrastructure and platform concerns. Existing approaches, however, use a single type of resource configuration to execute all function requests. In this paper, we present a novel FaaS approach that allows cloud functions to be effectively executed across heterogeneous compute resources, including hardware accelerators such as GPUs and FPGAs. We implement heterogeneous scheduling to tailor resource selection to each request, taking into account performance and cost concerns. In this way, our approach makes use of different processor types and quantities (e.g. 2 CPU cores), uniquely suited to handle different types of workload, potentially providing improved performance at a reduced cost. We validate our approach in three application domains: machine learning, bio-informatics, and physics, and target a hardware platform with a combined computational capacity of 24 FPGAs and 12 CPU cores. Compared to traditional FaaS, our approach achieves a cost improvement for non-uniform traffic of up to 8.9 times, while maintaining performance objectives.

     

A probe-based SEU detection method for SRAM-based FPGAs

SRAM-based FPGAs are becoming increasingly suitable for avionic and space applications due to their flexibility, reconfigurability and capacity as well as their signal processing capabilities. Unfortunately, commercial-of-the-shelf (COTS) SRAM-based FPGAs are highly sensitive to ionizing radiation environment such as space or avionic, making them extremely sensitive to radiation-induced Single Event Upsets (SEUs). In this paper, we propose a detection solution able to detect SEU-effects before they affect the circuit functionalities. The developed solution overcome state-of-the-art techniques since it is able to anticipate the detection of SEU-effects with an improvement of the latency of more than 70% than traditional redundancy based mitigation techniques. Besides, the proposed solution has a negligible impact on the circuit timing, since it does not introduce any performance degradation and it has a limited cost in terms of area usage. Experimental results performed on three benchmark circuits with traditional Duplication with Comparison (DEC) error detection technique demonstrate the feasibility of the proposed method showing an improvement of the detection capability of around 98% on the average.     

Design and implementation of a high level programming environmentfor FPGA-based image processing

Reconfigurable hardware in the form of field programmable gate arrays (FPGAs) has been proposed as a way of obtaining high performance for computationally intensive DSP applications such as image processing (IP), even under real time requirements. The inherent reprogrammability of FPGAs gives them some of the flexibility of software while keeping the performance advantages of an application specific solution. However, a major disadvantage of FPGAs is their low level programming model. To bridge the gap between these two levels, the authors present a high level software environment for FPGA-based image processing, which aims to hide hardware details as much as possible from the user. Their approach is to provide a very high level image processing coprocessor (IPC) with a core instruction set based on the operations of image algebra. The environment includes a generator which generates optimised architectures for specific user-defined operations     

FPGA Implementation and Energy Cost Analysis of Two Light-Weight Involutional Block Ciphers Targeted to Wireless Sensor Networks

In this paper, we investigate the energy cost of the FPGA implementation of two cryptographic algorithms targeted to wireless sensor networks (WSNs). Recent trends have seen the emergence of WSNs using sensor nodes based on reconfigurable hardware, such as a field-programmable gate arrays (FPGAs), thereby providing flexible functionality with higher performance than classical microcontroller based sensor nodes. In our study, we investigate the hardware implementation of involutional block ciphers since the characteristics of involution enables performing encryption and decryption using the same circuit. This characteristic is particularly appropriate for a wireless sensor node which requires the function of both encryption and decryption. Further, in order to consider the suitability of a cipher for application to a wireless sensor node, which is an energy constrained device, it is most critical to consider the cost of encryption in terms of energy consumption. Hence, we choose two involutional block ciphers, KHAZAD and BSPN, and analyze their energy efficiency for FPGA implementation.     

A comparative study of the on-off switching behavior ofmetal-insulator-metal antifuses

The on-state reliability of metal-insulator-metal antifuses based on aluminum nitride, silicon nitride, amorphous silicon, and tetrahedral amorphous carbon were investigated and compared. Among them, only the tetrahedral amorphous carbon antifuses show no spontaneous switching from the on-state to the off-state during operation. The unwanted switching was found to be associated with the presence of pinholes in the upper metal electrode of the antifuse. The percentages of silicon nitride and amorphous silicon antifuses with on-off switching were found to he greatly reduced after thermal annealing of the insulators. A failure mechanism of an antifuse resulting from thermal oxidation of its conductive link is proposed