Advances in magneto optical static event detector technology

Magneto-optical static event detectors, introduced at the 1998 EOS/ESD Symposium, have been demonstrated as a useful tool to detect low-level transients that damage magnetoresistive (MR) and giant magnetoresistive (GMR) recording heads. Improvements in magneto-optic film characteristics, device design, and wafer fabrication methods will result in enhanced sensitivity to those transients. Improvements in packaging and performance repeatability are described     

An Optimization-Based Algorithm for Shunt Active Filter Under Distorted Supply Voltages

In this paper, an optimization-based control algorithm for the compensation of steady-state load under distorted supply voltages is presented. For balanced and sinusoidal supply voltages, load compensation using shunt active filter produces perfect harmonic cancellation (PHC) and unity power factor (UPF) source currents. However, when the supply voltages are distorted, compensation for PHC will not provide UPF, as the harmonics in the supply voltages are not utilized for delivering the average power. In the same way, to achieve UPF source currents, the compensated source currents should have the same harmonics, unbalance, shape, and be in phase with the respective supply voltages, thereby violating the perfect harmonic cancellation objective. Hence, there should be an optimal operation between these two important compensation characteristics. The optimization-based control algorithm presented in this paper gives the best power factor while satisfying the constraints such as total harmonic distortion limits and average power balance of source currents. It is also flexible to adopt different compensation characteristics based upon the supply voltage conditions. Matlab and its optimization toolbox are used for simulation studies and solving the nonlinear optimization problem, respectively. The algorithm is validated by using a prototype of digital signal processor (TMS320F2812PGFA)-based shunt active power filter. Detailed experimental results are presented.     

Punchthrough currents in short-channel m.o.s.t. devices

Measurements have been performed on the source-leakage currents associated with short-channel m.o.s.t. devices. Both space-charge-limited and non-space-charge-limited punchthrough currents have been observed as a function of gate and drain voltages, and physical mechanisms describing these currents are briefly discussed.     

CMOS on buried nitride—A VLSI SOI technology

A CMOS technology in silicon on insulator (SOI) for VLSI applications is presented. The insulator is a buried silicon nitride formed by nitrogen implantation and annealing. The CMOS devices are fabricated in the superficial monocrystalline silicon layer without an epitaxial process, 1-µm PMOS and 2-µm NMOS transistors have been realized, which have been used to built inverters, ring Oscillators, and other circuits. With 40-nm gate oxide the transistors withstand gate and drain voltages of 10 V. Mobilities, subthreshold behavior, and leakage currents are nearly the same as in bulk-CMOS devices. Ring-oscillator measurements yield inverter delay times of 230 ps and power delay products of 14 fJ.     

Hyperreal Operating Points in Transfinite Resistive Networks

Transfinite resistive electrical networks may (or may not) have operating points, and, even when voltages and currents do exist within them, Kirchoff’s laws may not be satisfied everywhere. Moreover, rather severe restrictions have to be placed on those networks in order to obtain such results. However, by borrowing some techniques of nonstandard analysis, we can replace the real-valued voltages and currents by hyperreal-valued voltages and currents. As a result, Kirchhoff’s laws are always satisfied so long as the transfinite network is "restorable" in the sense that the transfinite network is the end result of an expanding sequence of finite networks. No other restrictions on the transfinite network are needed. Several transfinite networks are then examined under nonstandard analysis, and explicit hyperreal currents and voltages are established for them.     

PWM-switch modeling of DC-DC converters

The introduced PWM-switch modeling method is a simple method for modeling pulse-width-modulated (PWM) DC-DC converters operating in the continuous conduction mode. The main advantage of this method is its versatility and simple implementation compared to other methods. The basic idea is the replacement of the switches in the converter by their time-averaged models. These switch models have been developed in such a way that the converter model provides the same results as the state-space-averaging technique but not including nonlinear effects. Simple rules for determination of the switch models are obtained. The resulting model is a time-averaged equivalent circuit model where all branch currents and node voltages correspond to their averaged values of the corresponding original currents and voltages. The model also includes parasitics, second-order effects and nonlinearities, and can be implemented in any circuit-oriented simulation tool. The same model is used for the simulation of the steady-state and the transient behavior     

Response of a planar microstrip line excited by an externalelectromagnetic field

The voltages and currents induced by external electromagnetic fields on a planar microstrip line have been studied with the use of a distributed-source transmission-line model. The frequency response of the microstrip line has been analyzed by simulating the illuminating field with a plane wave arbitrarily incident on the line. The influence of the microstrip geometrical and electrical characteristics on the voltages and currents induced on the line has been examined, and indications for reducing the circuit susceptibility have been obtained. The model adopted can be used for studying the response of the line to any type of external field arbitrarily varying in space time. Numerical results show that for lines loaded with the characteristic impedance at both terminals, voltage amplitudes on the order of some millivolts and currents of some hundreds of microamperes can be induced at f=3 GHz by an incident plane wave with an electric-field intensity of 1 V/m and for various angles of incidence. The voltages and currents induced on a microstrip circuit can be reduced by using substrates of sufficiently high permittivity     

Application of field-based circuits to the modeling of magneticcomponents with hysteresis

A magnetic component with hysteresis is modeled as a network of field-based elemental subcircuits, whose currents and voltages are related to the dynamic electromagnetic fields in the component and an interface network, which couples the terminal voltages and currents to the field-based network. Such a model captures rate-dependent hysteresis, geometry, frequency and waveshape effects. Coupled transient simulation of the electromagnetic fields inside the core and circuit phenomena has been demonstrated using the Saber circuit simulator. The low-frequency inductances and hysteresis-related waveforms predicted by the model have been verified experimentally     

Lateral field emission diodes using SIMOX wafer

Lateral field emission diodes were fabricated by using separation by implantation of oxygen (SIMOX) wafer and their current-voltage characteristics (I-V) were analyzed. Applying conventional photolithography and local oxidation of silicon (LOGOS) process, we fabricated single-crystalline lateral silicon field emitters with very sharp cathode and anode tips and very short cathode to anode spacing ranging from 0.3 to 0.8 μm as well. Two different types of tips, tapered and wedge-shaped emitters, were typically formed according to oxidation time. The turn-on voltages for both types of diodes were as low as 22~25 V and the emission currents were as high as 6 μA/tip at voltages of 35~38 V. From the Fowler-Nordheim (FN) equation, field emitting area (A) and field enhancement factor (β) for both types of diodes were estimated to explain the low turn-on voltages and the high emission currents     

Schottky rectifiers on silicon using high barriers

Schottky diodes are presently used for power rectification because of their low forward voltage drop. However, they have only been fabricated on relatively low resistivity and thin semiconductor layers. Hence the reverse breakdown voltages are low. To make diodes that stand higher reverse voltages, low doped material of sufficient thickness is necessary. Ordinary Schottky barriers do not inject minority carriers and the resistive voltage drop at high forward currents will be large, However, for high Schottky barriers ～ 0.9eV, minority carriers are injected and the series resistance is decreased.In this paper we report results from one-dimensional numerical calculations as well as experimental results of high barrier Schottky diodes. We discuss the voltage drop at high forward currents for different substrate resistivity and thickness, as well as values of the high barrier.     

栅压对LDMOS在瞬态大电流下工作的温度影响

研究 LDMOS在一次雪崩击穿后的大电流区,栅压对器件内部温度的影响.结果表明:温度随正栅压升高而升高,随负栅压升高而降低,并分析了有源区内电场强度、电流密度和功率密度随栅压的变化规律.从而证明,与LDMOS栅接地时相比,正栅压降低了器件的静电放电能力,而负栅压则提高了器件的静电放电能力.     

The current-mode muddle

With the arrival of monolithic processes for the fabrication of bipolar transistors during the mid-1960s, it seemed like a good time to examine new paradigms for design. Current-mode (CM) was attractive because it suggested that small voltages swings could be used to process analog signals represented as currents; whatever voltages that did arise were treated as incidental. These were good ideas at the time. Are they still true today? It is important to know when CM offers a real advantage, to know when it is truly valuable, and to know when it is of only passing and academic interest.     

Voltage oscillations during surge pulses induced by self-extinguishing non-destructive second breakdown in pn-junction diodes

PN-junction diodes with different breakdown voltages have been subjected to surge pulses per the standard IEC 61000-4-5 and their transient behaviour has been studied. For medium breakdown voltages (20–40 V) at high surge currents large transient oscillations in the voltage drop across the diodes are observed. After such an event, the devices are still operational. 3D electro-thermal TCAD simulations have been done to understand the phenomenon. A comparison between measurement and simulation reveals that the periodic voltage drop is caused by non-destructive second breakdown.     

The theory of endfire arrays

The general King-Sandler array theory has been examined in detail for the case of endfire arrays. Since it is not necessary to assume identical current distributions, a distinction is made between specification of the base voltages and currents. The driving-point impedances for specified base voltages and currents are presented for arrays of up to 25 elements. The effect of interaction between the element currents in distorting the radiation pattern is shown for the 15-element endfire array. The results indicate that the unequal current distributions have a pronounced effect in determining the driving-point impedances, sidelobe levels and back-to-front ratios of endfire arrays.     

A grid-interfacing power quality compensator for three-phase three-wire microgrid applications

This paper proposes a grid-interfacing power quality compensator for three-phase three-wire microgrid applications with consideration of both the power quality of the microgrid and the quality of currents flowing between the microgrid and utility system. It is proposed that two inverters connected in shunt and series are used for each distributed generation (DG) system in the microgrid. In each inverter, both positive- and negative-sequence components are controlled to compensate for the effects caused by the unbalanced utility grid voltages. Specifically, the shunt inverter is controlled to ensure balanced voltages within the microgrid and to regulate power dispatches among parallel-connected DG systems, while the series inverter balances the line currents by injecting appropriate voltage components. A current-limiting algorithm is also proposed and integrated within the inverter control schemes to protect the microgrid from large fault currents during utility voltage sags. The proposed compensator has been tested in simulations and experimentally using a laboratory hardware prototype.     

Transients on lossy transmission lines with arbitrary boundary conditions

In this work the problem of transients on a lossy transmission line terminated by an arbitrary, including nonlinear, load is formulated. The tranmission line parameters are the constantsR, L, G, andC. The exact relation between the input and output voltages and currents in the form of two coupled integral equations is derived by the Laplace transform method. It is shown that the kernels of the integral equations may be represented in terms of either Lommel functions or integrals involving zeroth order modified Bessel functions. Simultaneous (numerical) solutions of these integral equations fulfilling the boundary conditions at the input and output of the line yields the input and output voltages and currents on the line. Finally the exact analytical relations in time domain of the voltage and current at an arbitrary point on the line (and the voltages and currents at the input and output terminals) are derived. In all parts, the problem has been formulated in such a way as to impose the causality condition explicitly.     

Thin-film transistors incorporating a thin, high-quality PECVD SiO2 gate dielectric

Thin-film transistors (TFTs) have been made that incorporate a thin (~380 Å), high-quality plasma-enhanced chemical vapor deposition (PECVD) SiO₂ film as the gate dielectric in a staggered-inverted structure. Threshold voltages and mobilities have been found to be in the range of 1.6-2.4 V and 0.20-0.25 cm² V^-1 s^-1, respectively, where the exact values are dependent on the measurement technique used. Very low gate leakage currents (<10^-11 A) were recorded when measured using a ramped I-V technique, even for electric fields as high as 5×10⁶ V/cm     

Quantum Transport Simulation of Experimentally Fabricated Nano-FinFET

We have utilized the contact-block-reduction (CBR) method, which we extended to allow a charge self-consistent scheme, to simulate experimentally fabricated 10-nm-FinFET device. The self-consistent CBR simulator has been modified to simulate devices with channels along arbitrary crystallographic orientation. A series of fully quantum-mechanical transport simulations has been performed. First, the fin extension length and doping profile have been calibrated to match the experimental data. The process control window for the threshold voltage as a function of fin extension has been extracted for the considered device. Then, a set of transfer characteristics and gate leakage currents have been calculated for different drain voltages. The simulation results have been found to be in good agreement with the experimental data in the subthreshold regime. The device turn-off and turn-on behavior has been examined for different fin widths: 12 (experimental), 10, 8, and 6 nm. Finally, the subthreshold slope degradation at high temperatures has been studied     

ESD phenomena in GMR heads in the manufacturing process of HDD and GMR heads

It is well known that giant magnetoresistive (GMR) heads used for hard disk drives (HDD) are very sensitive to electrostatic discharge (ESD). In this paper, we describe a method of categorizing ESD damage modes from a standpoint of magnetic influences on the heads as observed by quasi-static test (QST) characteristics as well as electromagnetic characteristics like off-track profiles. In addition, we report an example of GMR stack interlayer diffusion which is one type of hard ESD damage. We also present an example of ESD damage that happened in an actual production process and its preventive measures as guidelines.     

Calculation Model for Current-voltage Relation of Silicon Quantum-dots-based Nano-memory

Based on the capacitive coupling formalism, an analytic model for calculating the drain currents of the quantum-dots floating-gate memory cell is proposed. Using this model, one can calculate numerically the drain currents of linear, saturation and subthreshold regions of the device with/without charges stored on the floating dots. The read operation process of an n-channel Si quantum-dots floating-gate nano-memory cell is discussed after calculating the drain currents versus the drain to source voltages and control gate voltages in both high and low threshold states respectively.