Reliability improvement of EEPROM by using WSi2 polycide gate

Recent technology fabrication of EEPROM developed by STMicroelectronics involves tungsten-based polycide for the gate of the transistors. The EEPROM design is based on one floating gate. The main objective was to increase the data retention capability on product using this polycide, and this after cycling. Thus, we have set up a new process called integrated process involving a cluster tool which avoids any contamination during the manufacturing of the polycide stacked layers in comparison with the standard process. In addition, the tungsten chemistry induces an insertion of fluorine in the tunnel oxide. The presence of the fluorine is verified and can explain the modification of the threshold voltages and the evolution of the programming window. Analyses of test cells and product vehicles were made. This new process improves the data retention capability of the EEPROM after one million cycles, and also decreases the cumulative percentage of defects; these results were good enough to insert this process in the production line.     

Novel Single Polysilicon EEPROM Cell With Dual Work Function Floating Gate

A novel single polysilicon electrically erasable programmable read-only memory cell with dual work function floating-gate (DWFG) structure is presented in this letter. The floating gate of the proposed DWFG cell is doped with p+ on the source side and n+ on the drain side. For DWFG devices, the floating gate on the source side has a higher work function than that on the drain side. The work function difference and the intrinsic doped region at the middle of the floating-gate affect the channel potential distribution and generate a peak lateral electric field inside the channel, improving the channel's hot electron programming characteristics. The experimental results show that the proposed DWFG cell gives faster programming speeds and program operation at lower voltage than conventional cells     

Stacked gate mid-channel injection flash EEPROM cell-Part II:analysis of gate current and modeling of programmingcharacteristics

The programming characteristics of the stacked gate mid-channel injection (SMCI) flash memory cell is quantitatively analyzed vis a vis the stacked gate device. In the present model, the hot electrons in the high field channel region are described by the elevated temperature model. The programming speed and efficiency depend, among other factors, on the carrier lifetime, which is limited by both the recombination process and the carrier dwell time in the channel. The gate currents from the reference devices are quantitatively analyzed and specified empirically via the applied voltages and the device parameters. These results are applied to modeling the shift in time of the threshold voltage and the simulated values are shown to fit the data with a fair degree of accuracy     

An analytical programming model for the drain-coupling source-side injection split gate flash EEPROM

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted.     

Effects of flash EEPROM floating gate morphology on electricalbehavior of fast programming bits

The effects of Flash EEPROM Floating Gate morphology on the generation and density of fast programming bits on a 2-MBit Flash EEPROM array has been characterized. These fast programming bits exhibit identical subthreshold characteristics similar to that of a normal bit after UV-erase, thus establishing that the initial charge stored on the floating gate of both fast and normal bit is the same. This clearly indicates that the fast programming phenomena result from an interaction of the programming process and the floating gate. An in depth experimentation reveals that the floating gate poly deposition and doping process are crucial for controlling the desired Fowler-Nordheim (FN) tunneling. A correlation is established between the fast bit density observed in the 2-MBit array, the FN tunneling currents, the floating gate deposition and doping processes. The fast programming bit threshold voltage distribution and density can be modulated with the floating gate deposition and doping processes     

Modelling of write/erase and charge retention characteristics of floating gate EEPROM devices

A theoretical model is developed to characterise the write, erase and charge retention mechanisms of floating gate EEPROM devices. The model depicts the effect of the properties of thin tunnel oxide, interpoly oxide, injector area, and programming voltage on the device performance. The effect of trapping of electrons in the thin oxide during repeated write/erase cycles is also described.     

Effects of active area and gate doping method on program threshold voltage in an EEPROM cell

In this paper, we investigate dependency of program threshold voltage (V_T) in EEPROM cell on active area and doping method of floating gate. With in situ doped floating gate, it is found that there is a sharp drop of program V_T from 4 to 2.25 V when the channel width is reduced from 0.30 to 0.22 μm, while doping by ion implantation results in slight reduction of program V_T from 3.95 to 3.69 V. It also appears that channel length is another critical factor to affect on reduction of program V_T. In case of in situ doped floating gate, the program V_T is reduced from 3.9 to 2.7 V when the channel length is reduced from 0.20 to 0.18 μm. TEM analysis reveals that thermal oxidation in tunnel oxide region occurs during subsequent high temperature oxidation due to oxidant penetration via interface of silicon surface and sidewall silicon nitride.     

Simplified 0.35-μm flash EEPROM process using high-temperatureoxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheraltransistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O₂ anneal at 850°C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs     

Stacked gate mid-channel injection flash EEPROM cell. I.Programming speed and efficiency versus device structure

Presents a new flash EEPROM cell which has been fabricated to achieve fast programming with low power. This memory cell attains speed and efficiency, comparable to the split-gate device, while preserving a simple stacked gate structure. The device programs faster than the stacked gate cell by a factor of about ten. Also, the threshold voltage shift of 5 V can be accomplished with the drain voltage of 3 V in about 50 μs. The proposed memory cell is strongly resistant against the punchthrough effect and is capable of erasure in byte unit at the drain side. Factors pertinent to programming are discussed, theoretically and experimentally, in correlation with device structures. The hot electron dwell time in the channel is shown to be an important parameter, affecting the programming speed and efficiency     

Modeling of gate underlap junctionless double gate MOSFET as bio-sensor

In this work, the sensitivity of two types gate underlap Junctionless Double Gate Metal-Oxide-Semiconductor Field-Effect Transistor (JL DG MOSFET) has been compared when the analytes bind in the underlap region. Gate underlap region considered at source end and drain end once at a time in the channel of JL DG MOSFET. Separate models have been derived for both types of gate underlap JL DG MOSFETs and verified through device simulation TCAD tool sprocess and sdevice. To detect the bio-molecules, Dielectric Modulation technique has been used. The shift in the threshold voltage has been pondered as the sensing parameter to detect the presence of biomolecules when they are bound in gate underlap channel region of the devices.     

A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories

The aim of this study is to obtain from experimental data a reliable approach for predicting the impact of temperature on data retention in EEPROM memories. Using a floating gate dedicated structure, we present stress induced leakage current results and characterization in terms of AC generation, annealing kinetics and temperature activation in 6.8 nm SiO₂ tunneling oxide used in standard EEPROM products. We propose a simple way to deal with these three aspects in order to describe SILC evolution during retention phases corresponding to an oxide floating gate potential lower than 2 V.     

EEPROM as an analog storage device, with particular applications inneutral networks

The use of EEPROM as a compact, high-precision, nonvolatile, and reconfigurable analog storage element is investigated, with particular consideration given to the modifiable weight storage and analog multiplication problems in the hardware implementation of a neural network. Industry-standard digital EEPROM cells can be programmed to any analog value of threshold voltage, but programming characteristics of different devices on the same chip vary. The programming window of a single device also narrows with cycling. These phenomena necessitate the use of a feedback-based programming scheme. Stressing at high temperature suggests that charge retention is good even at 175°C. The linear variation of threshold voltage with temperature implies that temperature compensation of EEPROM is no more complicated than its conventional MOSFET counterpart. The drain current in the saturation region is found to be a quadratic function of drain voltage when the floating-gate-to-drain overlap capacitance is adequately large. A differential circuit that uses this property to generate the multiplication function required of neural net synapses is proposed     

以BCB为介质层的圆片级三维多芯片封装结构研究

研究了一种新型的圆片级三维多芯片封装结构,该结构以BCB为介质层,体硅工艺加工的硅片为基板,适合于毫米波射频元器件的封装与应用。结构中包含多层BCB介质层和金属布线,同时可以集成射频芯片,薄膜电阻,可变电容等有源和无源元件。封装过程中,射频芯片埋置在接地金属化的硅腔体中,利用热压焊凸点技术和化学机械抛光（CMP）实现多成金属布线间的层间互连。BCB介质层的涂覆、固化和抛磨对封装结构的性能影响较大,为了在进行CMP工艺和多层布线工艺之前得到高质量的BCB介质层,对BCB的固化曲线进行了优化,改进后的BCB介质层在经过CMP工艺后,能够得到光滑可靠的抛磨表面,不易产生质量缺陷,表粗糙度能够控制在10nm以内,利于BCB表面的金属布线工艺。同时,对加工完成的封装结构的力学、热学和射频传输性能进行了测试,结果显示：互连金凸点的剪切力达到70 N/mm2,优化后封装结构的热阻可以控制在2℃/W以内,在工作频段内,测试用低噪放大器的S参数变化很小,插入损耗的变化小于1db,回波损耗在10~15GHz的范围内,低于-8db,满足设计要求。     

A wafer-level 3D packaging structure with Benzocyclobutene as a dielectric for multichip module fabrication

A new wafer-level 3D packaging structure with Benzocyclobutene (BCB) as interlayer dielectrics (ELDs) for multichip module fabrication is proposed for application in the Ku-band wave. The packaging structure consists of two layers of BCB films and three layers of metallized films, in which the monolithic microwave IC (MMIC), thin film resistors, striplines and microstrip lines are integrated. Wet etched cavities fabricated on the silicon substrate are used for mounting active and passive components. BCB layers cover the components and serve as ILDs for interconnections. Gold bumps are used as electric interconnections between different layers, which eliminates the need to prepare vias by costly dry etching and deposition processes. In order to get high-quality BCB films for the subsequent chemical mechanical planarization (CMP) and multilayer metallization processes, the BCB curing profile is optimized and the roughness of the BCB film after the CMP process is kept lower than 10 nm. The thermal, mechanical and electrical properties of the packaging structure are investigated. The thermal resistance can be controlled below 2 ℃/W. The average shear strength of the gold bumps on the BCB surface is around 70 N/mm~2. The performances of MMIC and interconnection structure at high frequencies are optimized and tested. The 5 -parameters curves of the packaged MMIC shift slightly showing perfect transmission character. The insertion loss change after the packaging process is less than 1 dB range at the operating frequency and the return loss is less than -8 dB from 10 to 15 GHz.     

Semiconductor laser amplifier as optical switching gate

The properties of a semiconductor laser amplifier as optical switching gate are investigated. Particular attention is paid to gain, contrast ratio, and switching time of the device. These properties are studied experimentally and theoretically with respect to the injection current, optical input power, and cavity resonances. The experimental arrangements and the theoretical method are described. As an example of the various applications of semiconductor laser amplifier gates, packet switching experiments with self-routing, employing cascaded switching gates, are reported. In a theoretical analysis the restrictions that the properties of semiconductor laser amplifier gates impose on a larger switching system consisting of many such gates are investigated     

Thin-oxide damage from gate charging during plasma processing

The plasma-induced charge damage to small gate gate MOS capacitors is investigated by using `antenna' structures. After an O₂ plasma step the interface state density increases with increasing antenna area and varies by two orders of magnitude. A hole trapping-induced breakdown mechanism during plasma charging is supported by experimental evidence which includes annealing and polarity effects for charge to breakdown and tunneling currents. In addition, oxide susceptibility is shown to depend on oxide growth conditions and is predictable by negative bias-temperature aging     

Resist-related damage on ultrathin gate oxide during plasma ashing

This paper presents an important observation of plasma-induced damage on ultrathin oxides during O₂ plasma ashing by metal “antenna” structures with photoresist on top of the electrodes. It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10⁴. In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging. This phenomenon is contrary to most previous reports. It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides     

An anti-snapback circuit technique for inhibiting parasitic bipolar conduction during EOS/ESD events

In this work, an anti-snapback circuit technique called source injection (SI) is presented for the first time ever, which is shown to inhibit parasitic bipolar conduction during EOS/ESD events. The design is presented for a fully salicided, 0.25 μm, 35 Å /70 Å dual gate oxide, thin-epi, retrograde n-well, bulk CMOS technology. The technique is shown to greatly extend the snapback voltage of NMOS devices in this technology, which are usually destroyed instantaneously once snapback occurs. The design also has the benefit of controlling output buffer impedances for impedance matching to transmission-line loads. The design is fully compatible with the baseline process and has been shown to increase ESD robustness for positive discharge stress modes, which are the most difficult to protect for in epi processes. An increase of >1.5 kV is demonstrated for HBM, an increase of 550 V is shown for MM, and an increase of >550 V is exhibited for CDM, over non-SI and SI iopad designs, respectively.     

Off-state gate current with quasi-zero temperature coefficient in n-MOSFETs with reoxidized nitrided oxide as gate dielectric

Temperature stability of off-state gate current (I_g) for n-MOSFET's with reoxidized nitrided oxide (RNO) as gate dielectrics prepared by rapid thermal processing is investigated. A significant phenomeon that I_g remains almost unchanged at elevated temperature is observed. This could be attributed to the fact that reoxidation recovers part of the nitridation-induced lowering of barrier height for hole emission at the RNO/Si interface, resulting in the increases of the hot-hole injection which nearly compensate the decrease of hole generation at elevated temperature in the avalanche regime. The finding reveals a useful behavior with temperature-insensitive off-state gate current for RNO devices requiring a thermally stable operation.