共查询到19条相似文献,搜索用时 31 毫秒
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时序调整是由Leiserson和Saxe提出的一种同步电路优化技术。然而时序调整概念被提出来以后,这种技术并没有得到广泛的应用和进一步的发展。由下面的情况可以很清楚地看出来,功能强大的时序调整算法直到最近才在逻辑综合工具中得到最广泛的应用:* 时序调整技术的应用会直接导致面积的增加,这在早期的ASIC和可编程逻辑设计中将导致成本的迅速增加。* 典型设计实施过程中带宽并不总是最迫切的需求。* 多种不同类型寄存器的存在以及复杂的寄存器控制信号都限制了时序调整算法的应用。最近几年的设计实践表明,设计工程师对速度和带宽的要求越… 相似文献
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基于FPGA的相机特殊时序调整系统设计 总被引:1,自引:1,他引:0
针对某型特殊时序的红外相机图像需要通过CameraLink图像采集卡进行采集并显示的工程需要,设计了基于FPGA的特殊时序调整及接口适配板卡。采用SignaTap测量红外相机的具体时序,在此基础上根据图像采集卡可以识别的时序对相机输出信号的时序进行调整。采用FPGA内部集成的FIFO模块实现像素时钟的改变和图像数据的存取。采用Verilog语音编程实现有效信号的提取和无效信号的屏蔽以及行、场同步信号的调整等,将特殊时序的相机信号调整为通用CameraLink图像采集卡可以识别的信号时序。试验结果证明,经过处理的图像信号可以由CameraLink采集卡正确采集并显示,显示图像正确、稳定。 相似文献
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文章介绍了诱饵时序控制的重要性,给出了利用Altera公司可编程逻辑器件实现诱饵时序控制的工作原理、设计思路、电路结构和仿真结果。结果表明,基于FPGA的电路设计实际可行。 相似文献
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静态时序分析是FPGA系统设计中最常用的分析、调试时序性能的方法和工具,TimeQuest(TQ)时序分析器作为Altera公司的第二代静态时序分析器,得到了业界广泛的应用和关注。本文在解释了何为静态时序分析的基础上,介绍了基于TQ的时序分析和约束。 相似文献
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在数字系统的同步接口设计中,可编程逻辑器件的输入输出往往需要和周围新片对接,些时I/O接口的时序问题显得尤为重要。介绍了几种FPGA中的I/O时序优化设计的方案,切实有效的解决了I/O接口中的时序同步问题。 相似文献
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采用FPGA对电视同步信号时序进行监测,采用数字图像分析技术对电视图像内容进行监测,可以发现同步时序异常变化并进行自动信号切换;同时应用FPGA设计实现对电视同步信号的实时检测,并给出检测程序;使用图像分割方法建立电视信号初始模板,研究了建立精确图像模板的动态更新方法。 相似文献
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提出了由于FPGA容量的攀升和配置时间的加长,采用常规设计会导致系统功能失效的观点.通过详细描述Xilinx FPGA各种配置方式及其在电路设计中的优缺点,深入分析了FPGA上电时的配置步骤和工作时序以及各阶段I/O管脚状态,说明了FPGA上电配置对电路功能的严重影响,最后针对不同功能需求的FPGA外围电路提出了有效的设计建议. 相似文献
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This paper addresses timing acquisition aspects in direct-sequence code division multiple access (DS-CDMA) systems. Various chip waveform shaping schemes are considered, including both one-chip long full-response pulses, and partial-response ones occupying several chip periods. Different figures of merits are considered in a comparative analysis that seeks to establish performance limits in terms of correct timing detection capability, false alarm rate, bandwidth occupancy, multiple-access interference (MAI), and inter-chip interference (ICI). A waveform design algorithm is formulated to optimize system performance in terms of signal-to-interference-ratio (SIR) subject to other signalling constraints, and a solution based on the use of prolate spheroidal wave functions (PSWF) is derived. Numerous waveform design examples are then constructed to illustrate acquisition detection capability versus system load for both faded and unfaded cases. A comparative assessment of the performance of conventional signalling waveforms against the optimized ones is also presented. In particular, the numerical results show that the half-sine pulse used in minimum shift keying (MSK) is quasi-optimal within the full-response category, while root-raised cosine (RRC) Nyquist filtering with 22% rolloff (used in third generation CDMA standards) is also close to optimal when considering many-chip-long pulses. 相似文献
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Stefaan Vanheesbeke 《电子设计技术》2007,14(12):124-124
当你需要一些模拟输出,并且系统中有一片FPGA时,你可能选择采用一个PWM模块和一个简单的低通滤波器,如图1所示.FPGA的输出通常是一种固定频率、可变占空比的波形,由一个计数器和一个数字比较器生成(表1). 相似文献
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当前,时钟产品的推出速度越来越快,时钟需要满足的标准也在不断发展,时钟需要更高的性能、更高的精度,系统尺寸也需要越来越小,在存储、通信与网络、上网本、开关稳压器的相位同步、FPGA等方面的应用成为热门. 相似文献
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We propose an algorithm for assessing probabilistic timing constraints for systems including components with uncertain delays. We make a case for designing systems based on a probabilistic relaxation of such constraints, as this has the potential for resulting in lower silicon area and/or power consumption. We consider a concrete example, an MPEG decoder, for which we discuss modeling and assessment of probabilistic throughput constraints. 相似文献
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V-FPGAs: Increasing Performance with Manual Placement,Timing Extraction and Extended Timing Modeling
Pfau Johannes Zaki Peter Wagih Becker Jürgen 《Journal of Signal Processing Systems》2022,94(9):865-882
Journal of Signal Processing Systems - Virtual FPGAs (V-FPGAs) are used as vendor-independent virtualization layers, to retrofit features which are not available on the host FPGA and to prototype... 相似文献
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简要概述了弹性分组传送技术的特性和优点,阐述了弹性分组传送的定时机制和业务等级,并对弹性分组传送环的时钟等级分布、时延和抖动、错误容限和保护管理等内容及与之息息相关的TDM业务性能进行分析,同时就RPT的有关性能和以太网进行了比较。 相似文献
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Tom Kinsley 《电子产品世界》2004,(6):45-47
在前面的两篇文章中,讨论的重点是DDRSDRAM存储器的工作方式和一般布局指导.本文主要讨论如何增加读取操作时的时序裕量,如何优化设计获得更好的功率性能. 相似文献
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Abbaspour S. Pedram M. Ajami A. Kashyap C. 《Very Large Scale Integration (VLSI) Systems, IEEE Transactions on》2006,14(12):1383-1388
Static timing analysis is a key step in the physical design optimization of VLSI designs. The lumped capacitance model for gate delay and the Elmore model for wire delay have been shown to be inadequate for wire-dominated designs. Using the effective capacitance model for the gate delay calculation and model-order reduction techniques for wire delay calculation is prohibitively expensive. In this paper, we present sufficiently accurate and highly efficient filtering algorithms for interconnect timing as well as gate timing analysis. The key idea is to partition the circuit into low and high complexity circuits, whereby low complexity circuits are handled with efficient algorithms such as total capacitance algorithm for gate delay and the Elmore metric for wire delay and high complexity circuits are handled with sign-off algorithms. Experimental results on microprocessor designs show accuracies that are quite comparable with sign-off delay calculators with more than of 65% reduction in the computation times 相似文献