Design of 100‐V Super‐Junction Trench Power MOSFET with Low On‐Resistance

Power metal‐oxide semiconductor field‐effect transistor (MOSFET) devices are widely used in power electronics applications, such as brushless direct current motors and power modules. For a conventional power MOSFET device such as trench double‐diffused MOSFET (TDMOS), there is a tradeoff relationship between specific on‐state resistance and breakdown voltage. To overcome the tradeoff relationship, a super‐junction (SJ) trench MOSFET (TMOSFET) structure is studied and designed in this letter. The processing conditions are proposed, and studies on the unit cell are performed for optimal design. The structure modeling and the characteristic analyses for doping density, potential distribution, electric field, width, and depth of trench in an SJ TMOSFET are performed and simulated by using of the SILVACO TCAD 2D device simulator, Atlas. As a result, the specific on‐state resistance of 1.2 mΩ‐cm² at the class of 100 V and 100 A is successfully optimized in the SJ TMOSFET, which has the better performance than TDMOS in design parameters.     

槽栅型SiC MOSFET器件单粒子响应特性研究

利用TCAD Sentaurus模拟仿真软件,研究分析了三种不同结构的槽栅型1 200 V SiC MOSFET单粒子响应特性,器件包括传统单沟槽MOSFET、双沟槽MOSFET和非对称沟槽MOSFET结构。仿真结果表明,双沟槽MOSFET的抗单粒子特性优于其它两种结构器件。通过分析可知,双沟槽MOSFET结构的优越性在于有较深的源极深槽结构,有助于快速收集单粒子碰撞过程产生的载流子,从而缓解大量载流子聚集带来的内部电热集中,相比其它两种结构能有效抑制引起单粒子烧毁的反馈机制。     

Investigation of power Trench MOSFETs with retrograde body profile

We present here a power Trench MOSFET (T-MOS) with retrograde body doping profile. The channel length and trench depth are both shortened compared with conventional T-MOS. High energy implantation is used to form retrograde body profile. Electronic parameters of the new structure have been obtained by process and device simulation. The results show that the new structure has much lower specific on-resistance (R_ds,on) because of its shorter channel when compared with conventional T-MOS. As the trench depth is shallowed, the gate charge density Q_g is also reduced.     

沟槽负斜角终端结构的耐压机理与击穿特性分析

对常用的场限环(FLR)和正、负斜角终端结构的耐压机理进行了简要分析,讨论了其结构参数的优化方法.基于GTR台面终端结构,在功率MOSFET中引入了一种类似的沟槽负斜角终端结构.利用1SE软件对其耐压机理和击穿特性进行了模拟与分析.结果表明,采用沟槽负斜角终端结构会使功率MOSFET的耐压达到其平行平面结击穿电压的92...     

Simulation and Fabrication Studies of Semi‐superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi‐superjunction (semi‐SJ) trench double‐diffused MOSFET (TDMOS). In this new process, the thick single insulation layer (SiO₂) of a conventional device is replaced by a multilayered insulator (SiO₂/SiN_x/TEOS) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on‐resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on‐resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on‐resistance are 108 V and 1.1 mΩcm², respectively.     

DC-DC转换器中功率沟槽MOSFET的优化设计

利用工艺和器件模拟软件TSUPREM-4和MEDICI,研究了工艺参数对DC-DC转换器中的功率沟槽MOSFET的通态电阻Ron、栅-漏电容Cgd的影响以及栅-漏电荷Qgd在开关过程中的变化,指出了在设计和工艺上减小通态电阻Ron和栅-漏电容Cgd,提高器件综合性能的途径。     

具有栅介质电场屏蔽作用的新型GaN纵向槽栅MOSFET器件设计

基于氮化镓(GaN)等宽禁带(WBG)半导体的金氧半场效应晶体管(MOSFET)器件在关态耐压下,栅介质中存在与宽禁带半导体临界击穿电场相当的大电场,致使栅介质在长期可靠性方面受到挑战。为了避免在GaN器件中使用尚不成熟的p型离子注入技术,提出了一种基于选择区域外延技术制备的新型GaN纵向槽栅MOSFET,可通过降低关态栅介质电场来提高栅介质可靠性。提出了关态下的耗尽区结电容空间电荷竞争模型,定性解释了栅介质电场p型屏蔽结构的结构参数对栅介质电场的影响规律及机理,并通过权衡器件性能与可靠性的关系,得到击穿电压为1 200 V、栅介质电场仅0.8 MV/cm的具有栅介质长期可靠性的新型GaN纵向槽栅MOSFET。     

一种基于VDMOS技术的浅沟槽平面栅MOSFET新结构

本文基于VDMOS技术提出了一种浅沟槽平面栅MOSFET（TPMOS）新结构,其中浅沟槽位于VDMOS多晶硅平面栅下方n-漂移区的两元胞中央。与传统的VDMOS结构相比,新结构不仅可以显著改善器件的导通电阻(RON)和击穿电压(VBR),减小它们对栅极长度的依赖,而且除浅沟槽外,制作工艺与VDMOS完全兼容。采用TPMOS结构可为器件设计和制造提供更大的自由度。     

Extended Trench Gate Superjunction Lateral Power MOSFET for Ultra‐Low Specific on‐Resistance and High Breakdown Voltage

In this paper, a lateral power metal–oxide–semiconductor field‐effect transistor with ultra‐low specific on‐resistance is proposed to be applied to a high‐voltage (up to 200 V) integrated chip. The proposed structure has two characteristics. Firstly, a high level of drift doping concentration can be kept because a tilt‐implanted p‐drift layer assists in the full depletion of the n‐drift region. Secondly, charge imbalance is avoided by an extended trench gate, which suppresses the trench corner effect occurring in the n‐drift region and helps achieve a high breakdown voltage (BV). Compared to a conventional trench gate, the simulation result shows a 37.5% decrease in R_on.sp and a 16% improvement in BV.     

Dual-Material-Gate Technique for Enhanced Transconductance and Breakdown Voltage of Trench Power MOSFETs

In this brief, we propose a new dual-material-gate-trench power MOSFET that exhibits a significant improvement in its transconductance and breakdown voltage without any degradation in on-resistance. In the proposed structure, we have split the gate of a conventional trench MOSFET structure into two parts for work-function engineering. The two gates share the control of the inversion charge in the channel. By using 2-D numerical simulation, we have shown that by adjusting the lengths of the two gates to allow equal share of the inversion charge by them, we get the optimum device performance. By using $hbox{N}^{+}$ poly-Si as a lower gate material and $hbox{P}^{+}$ poly-Si as an upper gate material, approximately 44% improvement in peak transconductance and 20% improvement in breakdown voltage may be achieved in the new device compared to the conventional trench MOSFET.      

Trench superjunction VDMOS with charge imbalance cells

The breakdown capability of the trench superjunction (SJ) VDMOS with strip gate and rounded corner layout pattern is experimentally investigated. The investigation shows that the local charge imbalance of device’s corner is the reason for breakdown voltage degradation. In order to improve the breakdown capability and reliability of the device, an analytical model which is verified by the simulation using Sentaurus TCAD and experiment results is proposed to optimize the doping of p-pillar with respect to different cell pitches and corner radiuses. Finally, two robust 600 V trench SJ-VDMOS structures with different curvatures of the corner are proposed and fabricated.     

深硅槽开挖工艺

本文介绍了硅槽应用,即硅槽隔离和硅槽电容,对器件性能的改善。并介绍了硅槽隔离和硅槽电容的形成步骤及硅槽刻蚀剖面的形貌控制,CBrF_3刻蚀硅槽侧壁保护层的形成等等。     

A new shallow trench and planar gate MOSFET structure based on VDMOS technology

This paper proposes a new shallow trench and planar gate MOSFET(TPMOS) structure based on VDMOS technology,in which the shallow trench is located at the center of the n~- drift region between the cells under a planar polysilicon gate.Compared with the conventional VDMOS,the proposed TPMOS device not only improves obviously the trade-off relation between on-resistance and breakdown voltage,and reduces the dependence of on-resistance and breakdown voltage on gate length,but also the manufacture process is compatible with that of the VDMOS without a shallow trench,thus the proposed TPMOS can offer more freedom in device design and fabrication.     

深槽TVS研究

以静电放电（ESD）以及其他一些电压浪涌形式随机出现的瞬态电压,通常存在于各种电子器件中。随着半导体器件日益趋向小型化、高密度和多功能。电子器件越来越容易受到电压浪涌的影响,甚至导致致命的伤害。从静电放电到闪电等各种电压浪涌都能诱导瞬态电流尖峰,瞬态电压抑制器（TVS）通常用来保护敏感电路受到浪涌的冲击。基于不同的应用。瞬态电压抑制器可以通过改变浪涌放电通路和自身的箝位电压来起到电路保护作用。为了节省芯片面积,并且获得更高的抗浪涌能力,深槽TVS的概念已经被提出和研究。深槽TVS的结面形成于纵向的深槽的侧壁,这样,在相同的芯片面积下,它有更多的有效结面积,即更强的放电能力。我们也可以预见,深槽TVS的小封装尺寸对应用于保护高端IC非常关键。     

高频控制开关用沟槽MOSFET的研究

高频控制开关用功率器件要同时具备极低的导通电阻和栅漏电荷值,从而降低导通损耗和开关损耗.基于器件与工艺模拟软件TsupremⅣ和Medici,研究了工艺参数和设计参数对沟槽MOSFET器件击穿电压、比导通电阻和栅漏电荷的影响,优化设计了耐压30 V的开关用沟槽MOSFET器件.对栅极充电曲线中平台段变倾斜的现象,运用沟道长度调制效应给出了解释.     

Electrothermal Analysis for Super‐Junction TMOSFET with Temperature Sensor

For a conventional power metal–oxide–semiconductor field‐effect transistor (MOSFET), there is a trade‐off between specific on‐state resistance and breakdown voltage. To overcome this trade‐off, a super‐junction trench MOSFET (TMOSFET) structure is suggested; within this structure, the ability to sense the temperature distribution of the TMOSFET is very important since heat is generated in the junction area, thus affecting its reliability. Generally, there are two types of temperature‐sensing structures — diode and resistive. In this paper, a diode‐type temperature‐sensing structure for a TMOSFET is designed for a brushless direct current motor with on‐resistance of 96 mΩ·mm². The temperature distribution for an ultra‐low on‐resistance power MOSFET has been analyzed for various bonding schemes. The multi‐bonding and stripe bonding cases show a maximum temperature that is lower than that for the single‐bonding case. It is shown that the metal resistance at the source area is non‐negligible and should therefore be considered depending on the application for current driving capability.     

Trench capacitor leakage in high-density DRAM's

The leakage current between trench capacitors for megabit dynamic MOS memories has been modeled and studied through simulations. The minimum substrate doping density, to limit the leakage current to 1 pA/µm, has been determined as a function of trench-trench spacing. The effect of all other relevant parameters on the required substrate doping density has also been investigated. Furthermore, the substrate doping density at which impact ionization causes avalanche breakdown at the trench capacitor junction has been estimated. It is found that, for trench spacing of 0.75 µm or more, one can always find an intermediate range of substrate doping concentrations for which both the trench-trench leakage and the junction breakdown can be avoided.     

射频功率Trench MOSFET研制

在国内首次研制出了一种采用条状元胞结构、特殊的栅槽刻蚀条件、特殊的栅介质生长前处理工艺及多晶硅栅的射频功率Trench MOSFET器件。该器件漏源击穿电压大于62V、漏极电流大于3.0A、跨导大于0.8S、阈值电压2~3V、导通电阻比同样条件的VDMOS降低了19%~43%,在175MHz、VDS=12V下输出功率PO为7W、漏极效率ηD为44%、功率增益GP为10dB。     

高压Trench IGBT的研制

介绍了当前绝缘栅双极晶体管(IGBT)的几种结构及沟槽型IGBT的发展现况,分析了高电压沟槽型非穿通(NPT)IGBT的结构及工艺特点。通过理论分析计算出初步器件的相关参数,再利用ISE仿真软件模拟器件的结构及击穿和导通特性,结合现有沟槽型DMOS工艺流程,确定了器件采用多分压环加多晶场板的复合终端、条状元胞、6μm深度左右沟槽、低浓度背面掺杂分布与小于180μm厚度的器件结构,可以很好地平衡击穿特性与导通特性对器件结构的要求。成功研制出1 200 V沟槽型NPT系列产品,并通过可靠性考核,经过电磁炉应用电路实验,结果表明IGBT器件可稳定工作,满足应用要求。该设计可适合国内半导体生产线商业化生产。     

深亚微米隔离技术--浅沟槽隔离工艺

研究了浅沟槽隔离(STI)工艺的各主要工艺步骤:沟槽的形成、沟槽顶角的圆滑、沟槽填充以及化学机械抛光平坦化.使用器件模拟软件Medici和Davinci分析了STI结构的隔离性能以及沟槽隔离MOSFET的Kink效应和反窄宽度效应.