Hydrogenated amorphous silicon thin film transistor fabricated onplasma treated silicon nitride

We have demonstrated that the performance of the inverted staggered, hydrogenated amorphous silicon thin film transistor (a-Si:H TFT) is improved by a He, H₂, NH₃ or N₂ plasma treatment for a short time on the surface of silicon nitride (SiN _x) before a-Si:H deposition. With increasing plasma exposure time, the field-effect mobility increase at first and then decrease, but the threshold voltage changes little. The a-Si:H TFT with a 6-min N₂ plasma treatment on SiN_x exhibited a field effect mobility of 1.37 cm²/Vs, a threshold voltage of 4.2 V and a subthreshold slope of 0.34 V/dec. It is found that surface roughness of SiN_x is decreased and N concentration in the SiN _x at the surface region decreases using the plasma treatment     

Dependence of thin film transistor characteristics on thedeposition conditions of silicon nitride and amorphous silicon

The systematic relation between thin film transistors' (TFT's) characteristics and the deposition conditions of amorphous silicon nitride (a-SiN) films and hydrogenated amorphous silicon (a-Si:H) films is investigated. It is observed that field effect mobility μ_FE and threshold voltage V_th of the TFT's strongly depend on the deposition conditions of these films. The maximum μ_FE of 0.88 cm²/V·s is obtained for the TFT of which a-SiN film is deposited at a pressure of 85 Pa. This phenomenon is due to the variation of the interface states density between a-Si:H film and a-SiN film     

High-voltage silicon thin film transistor on quartz

A high voltage enhancement-type thin film transistor (TFT) has been fabricated on quartz in layers of laser-recrystallized polysilicon. The fabrication details and TFT characteristics are described.     

Solid phase crystallization of amorphous silicon on glass by thin film heater for thin film transistor (TFT) application

A new process for solid phase crystallization (SPC) of amorphous silicon (a-Si) using thin film heater is reported. With this localized Ti silicide thin film heater, we successfully crystallized 500 Å-thick a-Si in a few minutes without any thermal deformation of glass substrate. The size of crystallized silicon grain was abnormally big (30-40 μm). Polycrystalline thin film transistors (TFT) fabricated using this unique thin film heater showed better mobility than those of conventional ones by furnace annealing.     

Low pinch-off voltage amorphous silicon junction field-effect transistor: experiment and simulation

In this work, a junction field effect transistor (JFET) based on a-Si:H is presented. The drain-source contacts are made on top of the n-layer of a glass/metal/p/sup +/-i-n structure. The channel conductivity can be modulated by a reverse bias applied to the p/sup +/-i-n junction, which varies the depth or the length of the depletion region. In amorphous silicon, the depletion of doped layers is limited by the high defect density induced by the doping process. Here, the electron concentration of the n-doped layer (the device channel) in a p-i-n amorphous silicon junction is studied by using a one-dimensional finite-difference simulator. The n-channel conductivity is then obtained by integrating the free electron concentration along the drain-source direction. Pinch-off regime is achieved when the n-layer is fully depleted. A JFET with W/L = 400 /spl mu/m/40 /spl mu/m was fabricated. Transistors with pinch-off voltages around -3.6 V and transconductance values of the order of 10/sup -7/ A/V were obtained. Comparison between experimental and modeled output characteristics suggests the presence of a defect-rich layer at the channel-air interface. This is related to the damage induced by the process steps during the device fabrication. The achieved experimental results make the device suitable for applications in linear circuits. In particular, unlike thin film transistors (TFTs), JFETs do not require high-temperature, high-quality dielectric layers, and appear particularly attractive for process on plastic substrates.     

A self-alignment process for amorphous silicon thin film transistors

A new method of fabricating amorphous Si thin film transistors (a-Si TFT's) has been developed. This method uses the self-alignment process, which also includes the successive deposition of gate insulator and active amorphous Si layers in one-pumpdown time in an RF glow discharge apparatus. This method greatly simplifies the fabrication process and results in stable device performance. The practicability of this method was confirmed by experimentally fabricated devices.     

非晶硅薄膜太阳能电池应用开发新进展

非晶硅（ａ－Ｓｉ）薄膜太阳能电池是取之不尽的洁净能源－太阳能的光电元（组）件。文章详述了ａ－Ｓｉ薄膜太阳能电池的工艺优势，市场开发状况，可能应用领域，存在问题和展望。     

Low temperature polycrystalline silicon thin film transistor withsilicon nitride ion stopper

The authors have fabricated a new low temperature polycrystalline silicon (poly-Si) thin film transistor (TFT) with silicon nitride (SiN _x) ion-stopper and laser annealed poly-Si. The fabricated poly-Si TFT using SiN_x as the ion-stopper as well as the gate insulator exhibited a field effect mobility of 110 cm²/Vs, subthreshold voltage of 5.5 V, subthreshold slope of 0.48 V/dec., and on/off current ratio of ~10⁶. Low off-state leakage current of 2.4×10^-2 A/μm at the drain voltage of 5 V and the gate voltage of -5 V was achieved     

Dependence of annealing on stability of transparent amorphous InGaZnO thin film transistor

Bottom-gate transparent IGZO–TFT had been successfully fabricated at relatively low temperature (200 °C). The devices annealing for 4 h at 200 °C exhibit good electrical properties with saturation mobility of 8.2 cm²V^?1s^?1, subthreshold swing of 1.0 V/dec and on/off current ratio of 5×10⁶. The results revealed that the stability of TFT devices can be improved remarkably by post-annealing treatment. After applying positive gate bias stress of 20 V for 5000 s, the device annealing for 1 h shows a larger positive V_th shift of 4.7 V. However, the device annealing for 4 h exhibits a much smaller V_th shift of 0.04 V and more stable.     

An amorphous silicon thin-film transistor with fully self-alignedtop gate structure

We have developed a novel fully self-aligned top gate amorphous silicon thin-film transistor, which shows excellent transistor characteristics. Self-alignment is achieved by patterning the gate electrode and then etching the silicon nitride gate insulator, followed by silicidation and ion implantation of the exposed a-Si in the contact regions. We obtain a long channel saturated mobility of 0.9 cm² V^-1 s^-1, while for channel lengths of 6 μm, we obtain an effective mobility of 0.6 cm² V^-1 s^-1, in the saturated region and 0.5 cm² V ^-1 s^-1, in the linear region. This high level of performance, together with the negligible parasitic capacitance of the self-aligned structure, makes this transistor suitable for new demanding applications in active matrix liquid crystal displays and large area X-ray image sensors     

Analogue circuit building blocks with amorphous silicon thin film transistors

Useful building blocks such as the analogue subtractor, adder, and current source, with amorphous silicon (a-Si:H) thin film transistors (TFTs) are presented. The circuits built with only n-channel devices tackle the problem of threshold voltage instability in the TFT to provide stable transfer characteristics.     

柔性衬底硅薄膜太阳电池中ZGO薄膜的应用

在室温下,采用孪生对靶直流磁控溅射工艺,在玻璃衬底上制备出高质量的Ga掺杂ZnO(ZnO:Ga)透明导电膜。研究了薄膜厚度对薄膜的结构、光学及电学特性的影响。制备的ZnO:Ga是具有六角纤锌矿结构的多晶薄膜,最佳择优取向为(002)方向。随着薄膜厚度的增加,衍射峰明显增强,晶粒增大。优化反应条件,薄膜的电阻率达到4.69×10-4Ω.cm,在可见光范围内平均透过率达到了85%以上。将不同厚度的ZnO:Ga薄膜(350～820 nm)在柔性聚酰亚胺衬底nip非晶硅(a-Si)薄膜太阳电池中,随厚度的增加,电池的填充因子和效率都得到了提高,得到聚酰亚胺衬底效率7.09%的a-Si薄膜太阳电池。     

Planarization of amorphous silicon thin film transistors by liquidphase deposition of silicon dioxide

A planarized device structure was developed for amorphous silicon thin film transistors to overcome the gate leakage problem. Utilizing the liquid phase deposition technique, a silicon oxide film with thickness exactly equal to the gate height was grown around the gate to planarize the surface for the fabrication of inverted staggered thin film transistors. The planarized thin film transistor has smaller leakage current and better performance, i.e., field effect mobility, subthreshold swing, etc. This novel process has a potential to improve the yield of large area liquid crystal display     

An experimental and theoretical study of polycrystalline thin film transistor

This paper describes work undertaken to develop the Wiemer theory of thin film transistors [1] to be valid for polycrystalline semiconductors (s.c.) as well as monocrystalline s.c. A simple representation of the grain boundaries of polycrystalline s.c. as a series resistance has been proposed. A comparison of experimental and theoretical results shows good agreement between the calculated and measured values of the transistor parameters. Finally, an application of the theory has been extended to evaluate the average resistivity of the grain boundaries of polycrystalline s.c. such as InSb.     

Amorphous silicon detector and thin film transistor technology for large-area imaging of X-rays

This paper reviews amorphous silicon imaging technology in terms of the detector operating principles, electrical and optoelectronic characteristics, and stability. Also, issues pertinent to thin film transistor stability are presented along with optimization of materials and processing conditions for reduced V_T-shift and leakage current. Selected results are shown for X-ray and optical detectors, thin film transistors, and integrated X-ray pixel structures. Extension of the current fabrication processes to low (120°C) temperature, enabling fabrication of thin film electronics on flexible (polymer) substrates, are also discussed along with preliminary results.     

Achieving time-of-flight mobilities for amorphous organic semiconductors in a thin film transistor configuration

We observe bulk-like hole transport in amorphous organic semiconductors in a thin film transistor (TFT) configuration. Five different organic hole transporters (HTs) commonly used in organic light-emitting diodes are investigated. When these HTs are deposited on SiO₂ gate dielectric layer, the TFT mobilities are 1–2 orders of magnitude smaller than those obtained from bulk films (3–8 μm) using time-of-flight (TOF) technique. The reduction of hole mobilities can be attributed to the interactions between the organic HTs and the polar SiO bonds on the gate dielectric layer. Detailed temperature dependence studies, employing the Gaussian disorder model, indicate that the SiO₂ gate dielectric contributes between 60 and 90 meV of energetic disorder in the charge hopping manifold. Besides SiO₂ gate dielectric, similar effects can also be observed for other polar insulators including polymeric PMMA and BCB, or HMDS-modified SiO₂. However, when a common non-polar polymer, polystyrene (PS), is employed as the dielectric layer, the dipolar energetic disorder becomes negligible. Holes effectively experience bulk-like transport on the PS gate dielectric surface. TFT mobilities extracted from all five organic HTs are in excellent agreements with TOF mobilities. The present study should have broad applications in the transport characterization of amorphous organic semiconductors.     

A novel depletion-gate amorphous silicon thin-film transistor

A novel type of amorphous silicon (a-Si) thin-film transistor (TFT) in which a depletion gate is added to the top of the second nitride layer of a conventional a-Si TFT has been fabricated. In this transistor, switching is done by the depletion gate instead of the accumulation gate as in conventional a-Si TFTs. The pinch-off voltage and ON-OFF current ratio of the transistor can be changed by the accumulation gate bias. The transistor exhibits high ON-OFF current ratio, low contact resistance, and low gate-source capacitance     

An experimental study of the indium antimonide thin film transistor

In this paper a survey is given of our experimental investigations on the InSb thin film transistor (TFT). The best characteristics were obtained on a two-sided thin film transistor, made by flash evaporations of InSb on a heated substrate of 250°C, followed by an annealing at 350°C for 30 minutes. Furthermore it was found that the presence of minority carriers obstruct the saturation of the transistor characteristics at room temperature. This negative influence of the minority carriers is weakened at lower temperatures, which makes the InSb TFT more attractive for operations in a cryogenic environment.     

Impact of light soaking and thermal annealing on amorphous silicon thin film performance

Nowadays, there is a wide debate in literature related to the silicon thin films seasonal performance. Amorphous modules seem to react positively to the temperature, while the temperature parameters indicate a negative thermal response. Periodic fluctuations of nominal power due to light soaking and thermal annealing effects are observed. On the other hand, the module temperature reached in some open rack plants seems too low to activate annealing power regeneration process so that the seasonal performance trend may depend mainly on other effects such as spectral or irradiance. In the following paper, a model that allows to calculate the impact of all the phenomena that affect the photovoltaic performance is used. The light soaking and thermal annealing contributions are measured from outdoor data using two different methods. Both methods lead to similar results, and the model is able to reproduce the seasonal performance with an acceptable level of reliability on the day, hour, minute time scale. An analysis of each effect contribution to the seasonal performance is also provided. Thus, main open questions related to a‐Si thin films performance such as positive reaction to temperature and seasonal fluctuations are discussed. Copyright © 2015 John Wiley & Sons, Ltd.     

A low-leakage-current CdSe thin film transistor

This paper reports the design, fabrication, and performance of a very low-leakage-current thin film transistor (TFT). The TFT had a double-gate structure and used a 80–100 Å thick CdSe thin film as the semiconductor. The free charge carrier concentration in the semiconductor film was calculated to be 5×10¹⁴/cm³. These factors contributed to achieving a zero-gate-bias current less than 10^?10 A in the TFT. The ON/OFF current ratio of the TFT was measured to be greater than 10⁶. The TFT had acceptable stability in the ON condition and excellent stability in the OFF condition. A life test was performed on a TFT under a zero-gate-bias condition. After 1100 hr of testing, the zero-gate-bias current of the TFT increased from 5.8×10^?10 A to 9×10^?10 A. With extrapolation, the TFT had more than 10,000 hr lifetime.