A vertical resonant tunneling transistor for application in digitallogic circuits

A vertical resonant tunneling transistor (VRTT) has been developed, its properties and its application in digital logic circuits based on the monostable-bistable transition logic element (MOBILE) principle are described. The device consists of a small mesa resonant tunneling diode (RTD) in the GaAs/AlAs material system surrounded by a Schottky gate. We obtain low peak voltages using InGaAs in the quantum well and the devices show an excellent peak current control by means of an applied gate voltage. A self latching inverter circuit has been fabricated using two VRTTs and the switching functionality was demonstrated at low frequencies     

Continuous active T-gate travelling-wave transistor

In the letter experimental results are presented which show that a continuous active gate travelling-wave transistor (TWT) can be used for medium power applications in a wide bandwidth. To reduce the gate resistance, a T-gate configuration has been chosen. This allows one to extend the frequency bandwidth of such a device. Simulations have been performed using small- and large-signal models taking in addition the parasitic capacitances into account. A distributed Schottky diode has been used to adjust the phase synchronisation and therefore to achieve flat gain.<>     

Schottky-clamped NMOS transistors implemented in a conventional0.8-μm CMOS process

An 0.8-μm n-channel MOSFET with a TiSi₂-Si Schottky clamped drain-to-body junction (SCDR) and an n⁺ implanted standard source structure have been fabricated in a conventional 0.8-μm salicide CMOS process without any process modifications. The SCDR should be useful for reducing susceptibility for latch-up in integrated CMOS RF power amplifiers and switches where drain to p-substrate junctions can be forward biased during normal operations. Output I-V characteristics of the devices are the same as those of conventional MOSFETs, while parasitic lateral n⁺-drain/p-substrate/n⁺-source bipolar transistor measurements showed significantly reduced current gains because the Schottky barrier diode which does not inject minority carriers (electrons) to the p-substrate base clamps the n⁺ drain-to-p-substrate guard-ring diode connected in parallel     

A novel silicon Schottky diode for NLTL applications

The design and simulation of a novel silicon Schottky diode for nonlinear transmission line (NLTL) applications is discussed in this paper. The Schottky diode was fabricated on a novel silicon-on-silicide-on-insulator (SSOI) substrate for minimized series resistance. Ion implantation technology was used as a low-cost alternative to molecular beam epitaxy to approximate the delta (/spl delta/) doping profile, which results in strong nonlinear CV characteristics. The equivalent circuit model of the Schottky diode under reverse bias conditions was extracted from the S-parameter measurement performed on the diode. The measured CV characteristics show strong nonlinearity, the junction capacitance varies from 182 to 47.5 fF as the reverse bias voltage is varied from 0 to -5 V. A parasitic inductance of 40 pH was measured for the silicon Schottky diode, which is much smaller than a comparable sized GaAs Schottky diode. This small inductance is an advantage for the silicon Schottky diode offering improvement in the silicon NLTL performance.     

Latchup-free ESD protection design with complementary substrate-triggered SCR devices

The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits, which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V/sub SS/ and pad-to-V/sub DD/ ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-/spl mu/m salicided CMOS process with the human body model (machine model) ESD level of /spl sim/7.25 kV (500 V) in a small layout area.     

基于UTB-SOI技术的双辅助触发SCR ESD防护器件研究

为了提高FDSOI ESD防护器件的二次击穿电流,基于UTB-SOI技术,提出了一种SOI gg-NMOS和寄生体硅PNP晶体管双辅助触发SCR器件。通过gg-NMOS源区的电子注入和寄生PNP晶体管的开启,共同辅助触发主泄放路径SCR,快速泄放ESD电流。TCAD仿真结果表明,新结构能够泄放较高的二次击穿电流,具有可调节的触发电压。     

Hybrid Schottky injection MOS-gated power transistor

A modified Schottky injection field effect transistor (SINFET) which offers lower on-resistance and a switching speed comparable to conventional n-channel LDMOSTs is described. The fabrication process is similar to that of an LDMOS transistor but with the high-low (n+n-) `ohmic? contact at the drain replaced by a parallel combination of a Schottky barrier and a pn junction diode. This hybrid anode injects minority carriers into the n- drift region, which in turn provides conductivity modulation. A current handling capability 3.5 times larger than that of the LDMOST is achieved. With the minority carrier injection level limited by the Schottky barrier, the total amount of minority carriers injected by the hybrid anode is much lower than that injected by the pn junction diode alone. Thus, the device speed is comparable to the conventional n-channel LDMOST. By minimising the shunting resistance in the p-channel region, devices with a latch-up current density of 400 A/cm2 are obtained.     

Photon emission as a characterization tool for bipolar parasitics in FinFET technology

Parasitic bipolar effects are a well-known failure mechanism in integrated circuits. They trigger latching phenomena and are of particular interest for higher current applications and under leaky conditions. Photon emission microscopy (PEM) has proven to be a suitable tool to detect the occurrence of parasitic bipolar elements in MOSFETs, such as the parasitic bipolar junction transistor (BJT). Spectral PEM even allows for a more detailed characterization of the respective parasitic bipolar operation modes. In this work, we show that spectral PEM can also be used to characterize bipolar parasitics in modern p-type and n-type FinFETs. Additionally, this characterization method allows us to determine whether germanium enriched silicon was used to optimize device performance. We conclude by demonstrating that the FinFET devices under test show a very good suppression of parasitic bipolar effects.     

SCR operation mode of diode strings for ESD protection

Diodes and diode strings in 90 nm and beyond technologies are investigated by measurement and device simulation. After a thorough calibration, the device simulator is utilised to achieve a better understanding and an enhanced device performance of diode strings under static and transient ESD conditions. Thereto, parasitic transistors and a so far neglected parasitic thyristor (SCR) in the diode string are regarded, exploited and optimised.     

基于平面肖特基二极管的平衡式亚毫米波倍频器芯片

基于标准的平面肖特基二极管单片工艺设计了一款平衡式亚毫米波倍频单片集成电路.依据二极管实际结构进行电磁建模,提取了器件寄生参数,并与实测的器件本征参数相结合获得了二极管非线性模型;依据该模型,采用平衡式拓扑结构以实现良好的基波抑制,设计了三线耦合巴伦电桥,并与肖特基二极管集成在同一芯片上,实现了单片集成,提高了设计准确...     

CMOS on-chip electrostatic discharge protection circuit using four-SCR structures with low ESD-trigger voltage

A robust CMOS on-chip ESD protection circuit is proposed, which consists of four parasitic lateral SCR devices with low ESD trigger voltages to protect NMOS and PMOS devices of the internal circuits against the ESD pulses with both positive and negative polarities with respect to either VDD or VSS(GND) nodes. For each ESD stress with positive or negative polarity, there is an efficient and direct shunt path generated by the SCR low-impedance latching state to quickly bypass the ESD current. Thus, this four-SCR ESD protection circuit can perform very efficient protection in a small layout area. Since there is no diffusion or polysilicon resistor in the proposed ESD protection circuit, the RC delay between each I/O pad and its internal circuits is very low and high-speed applications are feasible. The experimental results show that this four-SCR protection circuit can successfully perform very effective protection against ESD damage. Moreover, the proposed ESD protection circuit is fully process-compatible with n-well or p-well CMOS and BiCMOS technologies.     

Conversion Losses in Schottky-Barrier Diode Mixers in the Submillimeter Region

Conversion Iosses, both intrinsic and parasitic, are calculated for Schottky diode mixers in the submillimeter region, and optimum mixer performance is shown to depend strongly upon operating frequency and upon diode diameter. The implications for high-frequency diode fabrication are discussed, and a comparison is made of the expected performance of GaAs, Si, and InSb Schottky diodes at frequencies up to 5 THz.     

DC and transient characterization of a compact Schottky bodycontact technology for SOI transistors

A self-aligned Schottky diode method for body contacting partially depleted silicon-on-insulator (SOI) transistors applicable to technologies that incorporate silicide cladded junctions is presented. The Schottky body contacted transistor requires no extra manufacturing steps, uses the same or less area than a transistor using other body contacting schemes and allows bi-directional operation. Extensive dc and transient characterization of the Schottky body contact illustrates its utility     

Characteristics of a p-n-p-n switch with an aluminum—Silicon Schottky diode clamp

An Al-Si Schottky diode has been incorporated in a p-n-p-n switch using a lateral p-n-p transistor and a vertical n-p-n transistor as a clamp. The switching characteristics are improved (speeded up). The dc characteristics display a negative resistance in the on region, and the on voltage at moderate currents is approximately the same as an unclamped p-n-p-n switch.     

基于平面肖特基二极管的W波段检波器

肖特基二极管技术为常温下毫米波信号的检测提供了有效的解决方案。它具有极低的寄生电容和级联电阻,可用于该频段的倍频器、混频器和检波器当中。相比于Galey Cell和热辐射测定器(Bolometer),基于肖特基二极管的直接检波技术具有低噪声、高反应率和常温使用的特点。本文介绍了一种基于波导结构的零偏置肖特基二极管检波器,采用E面探针传输波导基模电磁波,通过阻抗匹配实现微带线到二极管的耦合。测试结果表明,在-30 dBm输入功率下：电压反应率的峰值可达8 900 V/W;在75 GHz~105 GHz的频率范围内,电压反应率在1 000 V/W以上。     

Transistor Schottky-barrier-diode integrated logic circuit

A new high-speed low-power logic circuit using Schottky barrier diodes to avoid saturation of bipolar transistors is described. An experiment using discrete devices and a theoretical calculation show the possibility of subnanosecond logic using a saturated-type transistor logic circuit. A theoretical comparison with CML shows a 2:1 advantage in the speed-power product. The compatibility of Schottky barrier diode with monolithic silicon integrated circuit processing is shown. A prototype TTL circuit is described. Experimental results are given.     

Characteristics of low-leakage deep-trench diode for ESD protection design in 0.18-/spl mu/m SiGe BiCMOS process

This paper proposes a novel low-leakage BiCMOS deep-trench (DT) diode in a 0.18-/spl mu/m silicon germanium (SiGe) BiCMOS process. By means of the DT and an n/sup +/ buried layer in the SiGe BiCMOS process, a parasitic vertical p-n-p bipolar transistor with an open-base configuration is formed in the BiCMOS DT diode. Based on the two-dimensional (2-D) simulation and measured results, the BiCMOS DT diode indeed has the lowest substrate leakage current as compared to the conventional p/sup +//n-well diode even at high temperature conditions, which mainly results from the existence of the parasitic open-base bipolar transistor. Considering the applications of the diode string in electrostatic discharge (ESD) protection circuit designs, the BiCMOS DT diode string also provides a good ESD performance. Owing to the characteristics of the low leakage current and high ESD robustness, it is very convenient for circuit designers to use the BiCMOS DT diode string in their IC designs.     

Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology

Latchup failure which occurred at only one output pin of a power controller IC product is investigated in this work. The special design requirement of the internal circuits causes the parasitic diode that is inherent between the n-well and p-substrate to be a triggering source of the latchup occurrence in this IC. The parasitic diode of the internal PMOS was easily turned on by an anomalous external signal to trigger the neighbor parasitic Silicon Controlled Rectifier (SCR) path which causes latchup event in the CMOS IC product. Some solutions to overcome this latchup failure have been also proposed in this paper.     

Noise behavior of Schottky barrier gate field-effect transistors at microwave frequencies

The noise behavior of a Schottky barrier gate field-effect transistor is investigated by the use of the noise equivalent circuit. The influence of the carrier velocity saturation is estimated. The noise parameters are calculated by taking into account the influence of parasitic resistances. Measured and calculated noise parameters show good agreement in the frequency range 2-8 GHz.     

Organic strain sensor comprised of heptazole-based thin film transistor and Schottky diode

A strain sensor presenting a voltage signal has been studied, as comprised of an organic thin-film transistor (OTFT) and an organic Schottky diode which are connected in series to sensitively measure elastic tensile strain (up to ∼0.64%, bending radius of ∼4 mm). We chose organic heptazole TFT as a sensor component and large area heptazole Schottky diode as a strain-insensitive load incorporated into this strain sensor gauge circuit, because our heptazole TFTs have shown anisotropic response to the elastic tensile strain. Our organic strain sensor exhibits a decent amount of gauge factor (GF > 1.51) performance in both static and dynamic ways.