A Compact C‐Band 50 W AlGaN/GaN High‐Power MMIC Amplifier for Radar Applications

A C‐band 50 W high‐power microwave monolithic integrated circuit amplifier for use in a phased‐array radar system was designed and fabricated using commercial 0.25 μm AlGaN/GaN technology. This two‐stage amplifier can achieve a saturated output power of 50 W with higher than 35% power‐added efficiency and 22 dB small‐signal gain over a frequency range of 5.5 GHz to 6.2 GHz. With a compact 14.82 mm² chip area, an output power density of 3.2 W/mm² is demonstrated.     

AlGaN/GaN Based Ultra‐wideband 15‐W High‐Power Amplifier with Improved Return Loss

An ultra‐wideband microwave monolithic integrated circuit high‐power amplifier with excellent input and output return losses for phased array jammer applications was designed and fabricated using commercial 0.25‐μm AlGaN/GaN technology. To improve the wideband performance, resistive matching and a shunt feedback circuit are employed. The input and output return losses were improved through a balanced design using Lange‐couplers. This three‐stage amplifier can achieve an average saturated output power of 15 W, and power added efficiency of 10% to 28%, in a continuous wave operation over a frequency range of 6 GHz to 18 GHz. The input and output return losses were demonstrated to be lower than over a wide frequency range.     

Low‐Power,All Digital Phase‐Locked Loop with a Wide‐Range,High Resolution TDC

In this paper, we propose a low‐power all‐digital phase‐ locked loop (ADPLL) with a wide input range and a high resolution time‐to‐digital converter (TDC). The resolution of the proposed TDC is improved by using a phase‐interpolator and the time amplifier. The phase noise of the proposed ADPLL is improved by using a fine resolution digitally controlled oscillator (DCO) with an active inductor. In order to control the frequency of the DCO, the transconductance of the active inductor is tuned digitally. The die area of the ADPLL is 0.8 mm² using 0.13 µm CMOS technology. The frequency resolution of the TDC is 1 ps. The DCO tuning range is 58% at 2.4 GHz and the effective DCO frequency resolution is 0.14 kHz. The phase noise of the ADPLL output at 2.4 GHz is ‐120.5 dBc/Hz with a 1 MHz offset. The total power consumption of the ADPLL is 12 mW from a 1.2 V supply voltage.     

A 77 GHz mHEMT MMIC Chip Set for Automotive Radar Systems

A monolithic microwave integrated circuit (MMIC) chip set consisting of a power amplifier, a driver amplifier, and a frequency doubler has been developed for automotive radar systems at 77 GHz. The chip set was fabricated using a 0.15 µm gate‐length InGaAs/InAlAs/GaAs metamorphic high electron mobility transistor (mHEMT) process based on a 4‐inch substrate. The power amplifier demonstrated a measured small signal gain of over 20 dB from 76 to 77 GHz with 15.5 dBm output power. The chip size is 2 mm × 2 mm. The driver amplifier exhibited a gain of 23 dB over a 76 to 77 GHz band with an output power of 13 dBm. The chip size is 2.1 mm × 2 mm. The frequency doubler achieved an output power of –6 dBm at 76.5 GHz with a conversion gain of ?16 dB for an input power of 10 dBm and a 38.25 GHz input frequency. The chip size is 1.2 mm × 1.2 mm. This MMIC chip set is suitable for the 77 GHz automotive radar systems and related applications in a W‐band.     

A 0.13 μm CMOS UWB RF Transmitter with an On‐Chip T/R Switch

This paper presents a fully integrated 0.13 μm CMOS MB‐OFDM UWB transmitter chain (mode 1). The proposed transmitter consists of a low‐pass filter, a variable gain amplifier, a voltage‐to‐current converter, an I/Q up‐mixer, a differential‐to‐single‐ended converter, a driver amplifier, and a transmit/receive (T/R) switch. The proposed T/R switch shows an insertion loss of less than 1.5 dB and a Tx/Rx port isolation of more than 27 dB over a 3 GHz to 5 GHz frequency range. All RF/analog circuits have been designed to achieve high linearity and wide bandwidth. The proposed transmitter is implemented using IBM 0.13 μm CMOS technology. The fabricated transmitter shows a ?3 dB bandwidth of 550 MHz at each sub‐band center frequency with gain flatness less than 1.5 dB. It also shows a power gain of 0.5 dB, a maximum output power level of 0 dBm, and output IP3 of +9.3 dBm. It consumes a total of 54 mA from a 1.5 V supply.     

6～18 GHz宽带GaN功率放大器MMIC

报道了一款采用三级拓扑结构的6～18 GHz宽带单片微波功率放大器芯片.放大器采用了微带结构,并使用电抗匹配进行设计,减小输出匹配电路的损耗和提高效率.经匹配优化后放大器在6～18 GHz整个频带内脉冲输出功率大于6 W,小信号增益达到25 dB,在14 GHz频点处峰值输出功率达到10 w,对应的功率附加效率为21%...     

6‐GHz‐to‐18‐GHz AlGaN/GaN Cascaded Nonuniform Distributed Power Amplifier MMIC Using Load Modulation of Increased Series Gate Capacitance

A 6‐GHz‐to‐18‐GHz monolithic nonuniform distributed power amplifier has been designed using the load modulation of increased series gate capacitance. This amplifier was implemented using a 0.25‐μm AlGaN/GaN HEMT process on a SiC substrate. With the proposed load modulation, we enhanced the amplifier's simulated performance by 4.8 dB in output power, and by 13.1% in power‐added efficiency (PAE) at the upper limit of the bandwidth, compared with an amplifier with uniform gate coupling capacitors. Under the pulse‐mode condition of a 100‐μs pulse period and a 10% duty cycle, the fabricated power amplifier showed a saturated output power of 39.5 dBm (9 W) to 40.4 dBm (11 W) with an associated PAE of 17% to 22%, and input/output return losses of more than 10 dB within 6 GHz to 18 GHz.     

一种小型化高线性 GaN 功放器设计

采用ADS软件对一种高线性GaN功率放大器进行匹配电路设计,并制作了一款超小尺寸的高线性放大电路。该电路采用0.254 mm厚的Al2 O3陶瓷作为基板,放大晶体管选用无封装芯片,在5 mm ×6 mm的小尺寸范围内完成电路制作。制作的小尺寸高线性放大电路实现了在输入双音信号频率为4 G Hz和4.002 G Hz、输出总功率为2 W时,三阶互调抑制35 dBc ,功率附加效率35％。     

Ultra‐small Form‐Factor Helix on Pad‐Type Stage‐Bypass WCDMA Tx Power Amplifier Using a Chip‐Stacking Technique and a Multilayer Substrate

A fully integrated small form‐factor HBT power amplifier (PA) was developed for UMTS Tx applications. For practical use, the PA was implemented with a well configured bottom dimension, and a CMOS control IC was added to enable/disable the HBT PA. By using helix‐on‐pad integrated passive device output matching, a chip‐stacking technique in the assembly of the CMOS IC, and embedding of the bulky inductive lines in a multilayer substrate, the module size was greatly reduced to 2 mm × 2.2 mm. A stage‐bypass technique was used to enhance the efficiency of the PA. The PA showed a low idle current of about 20 mA and a PAE of about15% at an output power of 16 dBm, while showing good linearity over the entire operating power range.     

SOA‐Integrated Dual‐Mode Laser and PIN‐Photodiode for Compact CW Terahertz System

We designed and fabricated a semiconductor optical amplifier‐integrated dual‐mode laser (SOA‐DML) as a compact and widely tunable continuous‐wave terahertz (CW THz) beat source, and a pin‐photodiode (pin‐PD) integrated with a log‐periodic planar antenna as a CW THz emitter. The SOA‐DML chip consists of two distributed feedback lasers, a phase section for a tunable beat source, an amplifier, and a tapered spot‐size converter for high output power and fiber‐coupling efficiency. The SOA‐DML module exhibits an output power of more than 15 dBm and clear four‐wave mixing throughout the entire tuning range. Using integrated micro‐heaters, we were able to tune the optical beat frequency from 380 GHz to 1,120 GHz. In addition, the effect of benzocyclobutene polymer in the antenna design of a pin‐PD was considered. Furthermore, a dual active photodiode (PD) for high output power was designed, resulting in a 1.7‐fold increase in efficiency compared with a single active PD at 220 GHz. Finally, herein we successfully show the feasibility of the CW THz system by demonstrating THz frequency‐domain spectroscopy of an α‐lactose pellet using the modularized SOA‐DML and a PD emitter.     

C波段高效率高线性GaN MMIC功率放大器

基于SiC衬底0.25μm GaN HEMT工艺,设计实现了一款C波段、高效率和高线性的单片微波集成电路(MMIC)功率放大器。通过优化电路匹配结构,选择合适的有源器件和恰当的直流偏置条件,实现低视频漏极阻抗;利用后级增益压缩和前级增益扩张对消等手段,实现高功率附加效率和好的线性指标。功率放大器芯片尺寸为2.35 mm×1.40 mm。芯片测试结果表明,在3.7~4.2 GHz频率范围内,漏极电压28 V、末级栅极电压-2.2 V、前级栅极电压-1.8 V和连续波条件下,该功率放大器的小信号增益大于25 dB,大信号增益大于20 dB,饱和输出功率大于39 dBm,在输出功率回退至32 dBm时,功率附加效率大于30%,三阶交调失真小于-37 dBc。     

Ku波段宽带氮化镓功率放大器MMIC

基于0.25μm栅长GaN HEMT工艺,采用三级放大拓扑结构设计了一款Ku波段GaN功率放大器.放大器设计从建立大信号模型出发,输出匹配网络和级间匹配网络均采用电抗匹配减小电路的损耗,从而提高整体放大器的功率效率.测试结果表明,该放大器在14.6~18GHz频带内,小信号增益30dB,脉冲饱和输出功率达15W,功率附加效率(PAE)大于32%;在14.8GHz频点处,放大器的峰值功率达19.5W,PAE达39%.该结果表明GaN MMIC具有高频高功率高效率的优势,具有广阔的应用前景.     

基于GaN的大功率高线性固态发射机研制

介绍了一种GaN大功率高线性固态发射机。利用GaN HEMT的高功率特性,结合新型波导魔T低损耗功率合成的特点,在7.9~8.4GHz范围内实现了连续波饱和输出功率大于200W,效率大于20%。此外,应用新型模拟预失真方法提升功放的线性化指标,在额定输出功率下三阶交调指标(IMD3)优于-30dBc,改善功放的线性度11dB。该发射机具有输出功率大,线性度好等优点,整体性能优于国外同类产品。     

W‐Band MMIC chipset in 0.1‐μm mHEMT technology

We developed a 0.1‐μm metamorphic high electron mobility transistor and fabricated a W‐band monolithic microwave integrated circuit chipset with our in‐house technology to verify the performance and usability of the developed technology. The DC characteristics were a drain current density of 747 mA/mm and a maximum transconductance of 1.354 S/mm; the RF characteristics were a cutoff frequency of 210 GHz and a maximum oscillation frequency of 252 GHz. A frequency multiplier was developed to increase the frequency of the input signal. The fabricated multiplier showed high output values (more than 0 dBm) in the 94 GHz–108 GHz band and achieved excellent spurious suppression. A low‐noise amplifier (LNA) with a four‐stage single‐ended architecture using a common‐source stage was also developed. This LNA achieved a gain of 20 dB in a band between 83 GHz and 110 GHz and a noise figure lower than 3.8 dB with a frequency of 94 GHz. A W‐band image‐rejection mixer (IRM) with an external off‐chip coupler was also designed. The IRM provided a conversion gain of 13 dB–17 dB for RF frequencies of 80 GHz–110 GHz and image‐rejection ratios of 17 dB–19 dB for RF frequencies of 93 GHz–100 GHz.     

S波段35W GaN功率MMIC

报道了一款采用两级拓扑结构的2～4 GHz宽带高功率单片微波功率放大器芯片.放大器采用了微带结构,并使用电抗匹配进行设计,重点在于宽带功率效率平坦化设计.经匹配优化后放大器在2～4 GHz整个频带内脉冲输出功率大于35 W,小信号增益达到22 dB,在2.4 GHz频点处峰值输出功率达到40 W,对应的功率附加效率为3...     

Design of broadband class-F power amplifier for multiband LTE handsets applications

A broadband class-F power amplifier for multiband LTE handsets applications is developed across 2.3-2.7 GHz. The power amplifier maintains constant fundamental impedance at the output matching circuit which is operating for broadband. The nearly zero of second harmonic impedance and nearly infinity of third harmonic impedance are found for highly efficient class-F PA. The harmonic control circuits are immersed into the broadband output matching for fundamental frequency. For demonstration, the PA is implemented in InGaP/GaAs HBT process, and tested across the frequency range of 2.3-2.7 GHz using a long-term evolution signal. The presented PA delivers good performance of high efficiency and high linearity, which shows that the broadband class-F PA supports the multiband LTE handsets applications.     

一款X波段高效率GaN负载调制平衡放大器MMIC

报道了一款采用0.25μm GaN HEMT工艺的X波段高效率负载调制平衡放大器芯片。该芯片由两个射频端口的90°Lange耦合器,一对平衡功率放大器和一个控制信号功率放大器组成。通过改变同频率处控制信号的幅度与相位去调制平衡功率放大器的阻抗。在连续波测试条件下,该负载调制平衡放大器芯片在8~11 GHz范围内,最大输出功率为42.5 dBm,饱和效率为45%~55%,当输出功率回退6 dB时,效率为40%~45%。     

超宽带大功率合成器设计北大核心CSCD

在80 MHz~1 GHz频段,单个功率管输出功率能达到100 W以上,为研制输出功率400 W的功率放大器,文中设计了四路功率合成器。该合成器需要实现功率容量大、工作频带宽、体积小的设计目标。在功率容量方面,文中采用悬置带状线结构,其功率容量远远大于微带线结构;在工作频带方面,采用切比雪夫九节阻抗变换器,将工作带宽拓宽为80 MHz~1 GHz;在体积方面,文中合成器的功率合成部分采用Y型节级联实现四路功率合成,阻抗变换部分采用切比雪夫阻抗变换器进行阻抗变换,该结构相较于磁环巴伦功率合成器,不但具有损耗小、平坦度高的优点,而且通过将阻抗变换器设计成曲折的形状,进一步缩小了合成器体积。仿真与实测结果显示该合成器在80 MHz~1 GHz范围内还具有较高的平坦度,合成效率可达90%以上。     

A Class‐D Amplifier for a Digital Hearing Aid with 0.015% Total Harmonic Distortion Plus Noise

A class‐D audio amplifier for a digital hearing aid is described. The class‐D amplifier operates with a pulsecode modulated (PCM) digital input and consists of an interpolation filter, a digital sigma‐delta modulator (SDM), and an analog SDM, along with an H‐bridge power switch. The noise of the power switch is suppressed by feeding it back to the input of the analog SDM. The interpolation filter removes the unwanted image tones of the PCM input, improving the linearity and power efficiency. The class‐D amplifier is implemented in a 0.13‐μm CMOS process. The maximum output power delivered to the receiver (speaker) is 1.19 mW. The measured total harmonic distortion plus noise is 0.015%, and the dynamic range is 86.0 dB. The class‐D amplifier consumes 304 μW from a 1.2‐V power supply.     

A 60 GHz Medium Power Amplifier for Radio‐over‐Fiber System

We present the design and fabrication of a 60 GHz medium power amplifier monolithic microwave integrated circuit with excellent gain‐flatness for a 60 GHz radio‐over‐fiber system. The circuit has a 4‐stage structure using microstrip coupled lines instead of metal‐insulator‐metal capacitors for unconditional stability of the amplifier and yield enhancement. The gains of each stage of the amplifier are modified to provide broadband characteristics of input/output matching for the first and fourth stages and to achieve higher gains for the second and third stages to improve the gain‐flatness of the amplifier for wideband.