Inkjet-printed InGaZnO thin film transistor

We report inkjet-printed InGaZnO (IGZO) thin film transistors (TFTs). IGZO ink was prepared by dissolving indium nitrate hydrate, gallium nitrate hydrate and zinc acetate dihydrate into 2-methoxyethanol with additional stabilizers. The resulting films were inkjet-printed with a resolution of 300 dots per inch using droplets with a diameter of 40 µm, and a volume of 35 pl. The films exhibited high optical transparency in the visible range and had a polycrystalline phase of InGaO₃(ZnO)₂ after thermal annealing treatment. The chemical composition of this IGZO sample was also determined, and shown to have high stoichiometric characteristics of low oxygen deficiency. The TFTs with a conventional inverted staggered structure using inkjet-printed IGZO as an active channel layer had a field-effect mobility of ~ 0.03 cm²/Vs in saturation region and an on-to-off current ratio greater than ~ 10⁴.     

Deformation characteristics of an organic thin film transistor

An organic thin film transistor (OTFT) on a flexible substrate with electroplated electrodes has many advantages in the fabrication of low cost sensors, e-paper, smart cards, and flexible displays. In this study, we simulated the mechanical characteristics of an OTFT with various compressive stress conditions using COMSOL. An analysis model, which was limited to channel, source, and drain, was used to investigate deformation and internal stress concentrations. The channel length is 40 microm and the OTFT structure is a top-contact structure. The OTFT was fabricated using pentacene as a semiconducting layer and electroplated Ni as a gate electrode. The deformation characteristics of the fabricated OTFT were predicted in terms of strain and internal stress.     

The development of a thin film transistor amplifier

An integrated amplifier has been designed to incorporate vacuum-deposited thin film field-effect transistors. An array of separate transistors was first produced to gain experience in manufacturing techniques and also to optimize the choice of electrode geometry and materials. A registration accuracy between layers of better than 5 μm was achieved by the use of a specially designed evaporator. The effects on the characteristics of water vapour and ion migration were largely eliminated by the complementary use of two transistors. The circuit had a midband gain of 20 db and a gain bandwidth product of approximately 500 kHz.     

Preparation of pentacene thin film deposited using organic material auto-feeding system for the fabrication of organic thin film transistor

In this study, pentacene organic thin film was prepared using newly developed organic material auto-feeding system integrated with linear cell and characterized. The newly developed organic material auto-feeding system consists of 4 major parts: reservoir, micro auto-feeder, vaporizer, and linear cell. The deposition of organic thin film could be precisely controlled by adjusting feeding rate, main tube size, position and size of nozzle. 10 nm thick pentacene thin film prepared on glass substrate exhibited high uniformity of 3.46% which is higher than that of conventional evaporation method using point cell. The continuous deposition without replenishment of organic material can be performed over 144 hours with regulated deposition control. The grain size of pentacene film which affect to mobility of OTFT, was controlled as a function of the temperature.     

Preparation of poly-Si films by Cat-CVD for thin film transistor

Polycrystalline silicon (poly-Si) films have been deposited on low-temperature substrates using a hot-wall type catalytic chemical vapor deposition apparatus. Average grain size of the deposited poly-Si films was 10–20 nm. Hall mobility of 2–5 cm² V⁻¹ s⁻¹ was obtained even for a sample left at ambient conditions for a month. The influence of the sidewall temperature on poly-Si film properties has been investigated. The poly-Si films have been prepared under the hot/cold-wall conditions. Comparing crystalline fractions of both films measured by Raman spectroscopy, the difference was small. The crystalline fractions of 89 and 85% were obtained for the hot- and cold-wall conditions, respectively. As for the results of attenuated total reflection Fourier-transform infrared spectroscopy, a distinct difference between the two films was found, H and O atoms were more incorporated in the films deposited under the cold-wall conditions than in the films under the hot-wall conditions.     

Capacitance analyses of hydrogenated nanocrystalline silicon based thin film transistor

The capacitance-voltage (C-V) measurements within 10⁶-10^− 2 Hz frequency range were performed on the hydrogenated nanocrystalline silicon (nc-Si:H) bottom-gate thin film transistor (TFT) and metal-insulator-amorphous silicon (MIAS) structure, mechanically isolated from the same TFT. It was found that the conducting thin layer in nc-Si:H film expands the effective capacitor area beyond the electrode in the TFT structure, which complicates its C-V curves. Considering the TFT capacitance-frequency (C-F) curves, the equivalent circuit of the TFT structure was proposed and mechanism for this area expansion was discussed. On the other hand, the MIAS C-F curves were fitted by the equivalent circuit models to deduce its electrical properties. nc-Si:H neutral bulk effect was revealed by the dependence of the MIAS capacitance on frequency within 10⁶-10³ Hz at both accumulation and depletion regimes. The inversion in MIAS was detected at 10²-10^− 2 Hz for relatively low negative gate bias without any external activation source. The presence of the ac hopping conductivity in the nc-Si:H film was inferred from the fitting. In addition, the density of the interface traps and its energy distribution were determined.     

Influence of finite semiconductor thickness on thin film transistor characteristics

Through an exact numerical analysis of the electron charge in the conduction band as a function of the gate voltage, the influence of the finite thickness of the semiconductor channel on thin film transistor characteristics is investigated. It is shown that, in various experimentally interesting situations, sufficiently accurate approximations can be found which are much easier to calculate. However, if bulk trapping occurs in a heavily doped semiconductor, no such approximation can be found.     

Effect of Ag doping on the performance of ZnO thin film transistor

Ag-doped zinc oxide (SZO) thin film transistors (TFTs) have been fabricated using a back-gate structure on thermally oxidized and heavily doped p-Si (100) substrate. The SZO thin films were deposited via pulsed laser deposition (PLD) from a 1, 3, and 5 wt.% Ag-doped ZnO (1SZO, 3SZO, and 5SZO, respectively) target using a KrF excimer laser (λ, 248 nm) at oxygen pressure of 350 mTorr. The deposition carried out at both room-temperature (RT) and 200 °C. The SZO thin films had polycrystalline phase with preferred growth direction of (002) as well as a wurtzite hexagonal structure. Compare with ZnO thin films, the SZO thin films were characterized by confirming the shift of (002) peak to investigate the substitution of Ag dopants for Zn sites. The as-grown SZO TFTs deposited at RT and 200 °C showed insulator characteristics. However the SZO TFTs annealed at 500 °C showed good n-type TFT performance because Ag was diffused from Zn lattice site and bound themselves at the high temperature, and it caused generation of electron carriers. The post-annealed 5SZO TFT deposited at 500 °C exhibited a threshold voltage (V_th) of 11.5 V, a subthreshold swing (SS) of 2.59 V/decade, an acceptable mobility (μ_SAT) of 0.874 cm²/V s, and on-to-off current ratios (I_on/off) of 1.44 × 10⁸.     

The effect of annealing on the semiconductor in a thin film transistor

This study is concerned with an investigation of the effect of temperature annealing on the CdSe semiconductor in a thin film transistor. Electron microscopy shows that the CdSe film is polycrystalline. Annealing results in the growth of the crystallites until, for working thin film transistors, the crystallite size distribution becomes a log-normal one, with a mean crystallite size approximately equal to the thickness of the film. Annealing reduces the energy stored in the CdSe by converting grain boundaries from high to low angle ones and by reducing the grain boundary area.     

A thin film metal base transistor structure with amorphous silicon

We describe a metal base transistor structure using amorphous silicon prepared from a silane glow discharge. We give some of the operating characteristics and evidence for true injection. The highest measured injection ratio was 8%. We discuss the reasons for the low injection ratios and suggest some improvements.     

High performance low temperature solution-processed zinc oxide thin film transistor

Amorphous zinc oxide thin films have been processed out of an aqueous solution applying a one step synthesis procedure. For this, zinc oxide containing crystalline water (ZnO⋅ × H₂O) is dissolved in aqueous ammonia (NH₃), making use of the higher solubility of ZnO⋅ × H₂O compared with the commonly used zinc oxide. Characteristically, as-produced layers have a thickness of below 10 nm. The films have been probed in standard thin film transistor devices, using silicon dioxide as dielectric layer. Keeping the maximum process temperature at 125 °C, a device mobility of 0.25 cm²V^− 1s^− 1 at an on/off ratio of 10⁶ was demonstrated. At an annealing temperature of 300 °C, the performance could be optimized up to a mobility of 0.8 cm²V^− 1s^− 1.     

Organic thin film transistor using silver electrodes by the ink-jet printing technology

We have developed a conductive ink containing silver nanoparticles from which the electrodes for organic thin film transistor were directly patterned by ink-jet printing. Nano-sized silver particles having ∼ 20 nm diameter was used for a direct metal printing. Silver conductive ink was printed on the heavily doped n-type silicon wafer with 200-nm thick thermal SiO₂ layer as a substrate. To achieve a high line resolution and smooth conductive path, the printing conditions such as the inter-drop distance, stage moving velocity and temperature of the pre-heated substrates were optimized. After the heat-treatment at temperatures of 200 °C for 30 min, the printed silver patterns exhibit metal-like appearance and the conductivity. To fabricate a coplanar type TFTs, an active material of semiconducting oligomer, α,ω-dihexylquaterthiophene (DH4T) in a chlorobenzene was deposited between the ink-jet printed silver electrodes by drop casting. The OTFT with the ink-jetted source/drain electrodes shows general performance characteristics with good saturation behavior and no significant contact resistance as compared to the one with vacuum deposited electrodes. The electrical characteristic parameters of OTFT show the mobility of 1.3 × 10^− 3 cm² V^− 1 s^− 1 in the saturation regime, on/off current ratio over 10³, and threshold voltage of about − 13 V.     

Effect of carbon nanotube network morphology on thin film transistor performance

The properties of electronic devices based on carbon nanotube networks (CNTNs) depend on the carbon nanotube (CNT) deposition method used, which can yield a range of network morphologies. Here, we synthesize single-walled CNTs using an aerosol (floating catalyst) chemical vapor deposition process and deposit CNTs at room temperature onto substrates as random networks with various morphologies. We use four CNT deposition techniques: electrostatic or thermal precipitation, and filtration through a filter followed by press transfer or dissolving the filter. We study the mobility using pulsed measurements to avoid hysteresis, the on/off ratio, and the electrical noise properties of the CNTNs, and correlate them to the network morphology through careful imaging. Among the four deposition methods thermal precipitation is found to be a novel approach to prepare high-performance, partially aligned CNTNs that are dry-deposited directly after their synthesis. Our results provide new insight into the role of the network morphologies and offer paths towards tunable transport properties in CNT thin film transistors.      

Coplanar amorphous silicon thin film transistor fabricated by inductively-coupled plasma CVD

The electrical and optical properties of the a-Si:H films deposited by inductively-coupled plasma chemical vapour deposition (ICP-CVD) have been investigated. The ICP-CVD a-Si:H films deposited at 30 mTorr exhibited the deposition rate of 0.9 Å/s and the hydrogen content of 17 at.%. A novel coplanar self-aligned a-Si:H thin film transistor has been fabricated using Ni-silicide gate and source/drain contacts. The coplanar a-Si:H TFT exhibited a field effect mobility of 0.6 cm²/Vs, a threshold voltage of 2.3 V, a subthreshold slope of 0.5 V/dec.     

Effects of the composition of sputtering target on the stability of InGaZnO thin film transistor

In this study, we investigated the electrical characteristics and the stability of amorphous indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) from the viewpoint of active layer composition. Active layers of TFTs were deposited by r.f. sputtering. Two kinds of sputtering targets, which have different compositional ratios of In:Ga:Zn, were used to make variations in the active layer composition. All the fabricated IGZO TFTs showed more excellent characteristics than conventional amorphous silicon TFTs. However, in accordance with the Ga content, IGZO TFTs showed somewhat different electrical characteristics in values such as the threshold voltage and the field effect mobility. The device stability was also dependent on the Ga content, but had trade-off relation with the electrical characteristics.     

Numerical modeling of SiH4 discharge for Si thin film deposition for thin film transistor and solar cells

Amorphous and microcrystalline silicon thin films are used in solar cells as a multi-junction photovoltaic device. Plasma enhanced chemical vapor deposition is used and high deposition rate of a few nm/s is required while keeping film quality. SiH₄ is used as a precursor diluted with H₂. Electron impact processes give complex interdependent plasma chemical reactions. Many researchers suggest keeping high H/SiH_x ratio is important. Numerical modeling of this process for capacitively coupled plasma and inductively coupled plasma is done to investigate which process parameters are playing key roles in determining it. A full set of 67 volume reactions and reduced set are used. Under most of conditions, CCP shows 100 times higher H/SiH₃ ratio over ICP case due to its spatially localized two electron temperature distribution. Multi hollow cathode type CCP is also modeled as a 2 × 2 hole array. For Ar, the discharge is well localized at the neck of the hole at a few Torr of gas pressure. H₂ and SiH₄ + H₂ needed higher gas pressure and power density to get a multi hole localized density profile. H/SiH₃ was calculated to be about 1/10.     

Nanometer-scale oxide thin film transistor with potential for high-density image sensor applications

The integration of electronically active oxide components onto silicon circuits represents an innovative approach to improving the functionality of novel devices. Like most semiconductor devices, complementary-metal-oxide-semiconductor image sensors (CISs) have physical limitations when progressively scaled down to extremely small dimensions. In this paper, we propose a novel hybrid CIS architecture that is based on the combination of nanometer-scale amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and a conventional Si photo diode (PD). With this approach, we aim to overcome the loss of quantum efficiency and image quality due to the continuous miniaturization of PDs. Specifically, the a-IGZO TFT with 180 nm gate length is probed to exhibit remarkable performance including low 1/f noise and high output gain, despite fabrication temperatures as low as 200 °C. In particular, excellent device performance is achieved using a double-layer gate dielectric (Al?O?/SiO?) combined with a trapezoidal active region formed by a tailored etching process. A self-aligned top gate structure is adopted to ensure low parasitic capacitance. Lastly, three-dimensional (3D) process simulation tools are employed to optimize the four-pixel CIS structure. The results demonstrate how our stacked hybrid device could be the starting point for new device strategies in image sensor architectures. Furthermore, we expect the proposed approach to be applicable to a wide range of micro- and nanoelectronic devices and systems.     

Asymmetric fingered polysilicon p-channel thin film transistor structure for kink effect suppression

We present, for the first time, the application of the asymmetric fingered thin film transistor (AF-TFT) architecture to self-aligned p-channel TFTs for kink effect suppression. In AF-TFT the transistor channel region is split into two zones with different lengths (L₁ > L₂) separated by a floating p⁺ region. A fourth electrode, contacting the floating p⁺ region, allowed us to measure the individual electrical characteristics of the two sub-TFTs. Output characteristics show that substantial kink effect reduction can be achieved when the sub-TFT placed at the drain end of the device has an L₂ ? L₁. The electrical characteristics were analysed by using numerical simulations in the framework of the two-transistor model and we show that kink effect suppression arises from the operation in saturation regime of the source sub-TFT. The electrical characteristics of the fabricated p-channel AF-TFTs show a complete kink effect suppression, making these devices very attractive for current drivers in organic light emitting displays.