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1.
Estimation of high performance in Schmitt triggers with stacking power‐gating techniques in 45 nm CMOS technology
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Anshul Saxena Akansha Shrivastava Shyam Akashe 《International Journal of Communication Systems》2014,27(12):4369-4383
In the complementary metal oxide semiconductor (CMOS) nanoscale technology ground bounce noise and power consumption are becoming important metric. In presented paper, low leakage Schmitt trigger circuits are proposed for wave shaping or cleaning process with low ground bounce noise. Schmitt trigger play important role in communication electronics. Power‐gating and stacking power‐gating techniques have provided for maintaining the parameter of Schmitt trigger. An ideal approach has been investigated with stacking power‐gating technique. For further reduction in peak of ground bounce noise during sleep to active (power) mode transition, we have performed simulations using cadence specter 45 nm standard CMOS technology at nominal temperature (27°C) with supply voltage Vdd = 0.7 V and input voltage vary from 0.7 V to 1.5 V. The simulation results show that a proposed design provide efficient 6 T and 4 T Schmitt triggers in term of minimum leakage power (8.18 fW), active power (17.80 pW), ground bounce noise (1.65 μV) and propagation delay (1.98 ns), transconductance (4.51 × 10?14 S), voltage gain (29.44 dB), hysteresis width (11.07 V) and efficiency (64.68%). Reported devices use for low‐power communication systems. Copyright © 2013 John Wiley & Sons, Ltd. 相似文献
2.
Analysis of a Parasitic‐Diode‐Triggered Electrostatic Discharge Protection Circuit for 12 V Applications
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In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic‐diode‐triggered silicon controlled rectifier. The breakdown voltage and trigger voltage (Vt) of the proposed ESD protection circuit are improved by varying the length between the n‐well and the p‐well, and by adding n+/p+ floating regions. Moreover, the holding voltage (Vh) is improved by using segmented technology. The proposed circuit was fabricated using a 0.18‐μm bipolar‐CMOS‐DMOS process with a width of 100 μm. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the Vt of the proposed circuit increased from 14 V to 27.8 V, and Vh increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human‐body‐model surges at 7.4 kV and machine‐model surges at 450 V. 相似文献
3.
Chi-Hung Lin Mohammed Ismail Tales Pimenta 《Analog Integrated Circuits and Signal Processing》1999,21(2):153-162
Two robust CMOS rail-to-rail OpAmp input stages are presented for low voltage ( 3 V) applications. The robust input stages are implemented using two recently reported universal approaches to achieve constant transconductance. Transconductance control circuit is also introduced to compensate for K
p
, K
n
mismatch of PMOS and NMOS differential pairs in the input stage. The input stages are designed for operation in the strong inversion and have a rail-to-rail common mode input voltage range. Compared with an OpAmp with simple complementary input pairs, a two stage rail-to-rail OpAmp design example exhibits lower total harmonic distortion (THD) levels over the entire common mode input voltage range.currently on leave as a visiting scholar at OSU 相似文献
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A novel level shift circuit featuring with high dV/dt noise immunity and improved negative V_S capacity is proposed in this paper.Compared with the conventional structure,the proposed circuit adopting two cross-coupled PMOS transistors realizes the selective filtering ability by exploiting the path which filters out the noise introduced by the dV/dt.In addition,a differential noise cancellation circuit is proposed to enhance the noise immunity further.Meanwhile,the negative V_S capacity is improved by unifying the detected reference voltage and the logic block’s threshold voltage.A high voltage half bridge gate drive IC adopting the presented structure is experimentally realized by using a usual 600 V BCD process and achieves the stable operation up to 65 V/ns of the dV/dt characteristics. 相似文献
5.
This article analyses and presents an LLC resonant converter with a high power factor for LCD-TV applications. It integrates the advantages of power factor correction and the LLC resonant converter. It can improve not only power quality but also circuit efficiency. Since the power factor corrector is used in the first stage of the LLC resonant converter, it is suitable for wide input voltage range application. On the basis of the resonant behaviour, zero voltage switching is achieved for the power switches and ZCS is achieved for the rectifier diodes. An experimental prototype of 90–260V rms input and 12V/10A and ?12V/10A outputs with 92.6% efficiency for 32″ LCD-TV application is built in the laboratory to verify the operation principle of the adopted converter. 相似文献
6.
Shih-Lun Chen Ming-Dou Ker 《Circuits and Systems II: Express Briefs, IEEE Transactions on》2005,52(7):361-365
A new Schmitt trigger circuit, which is implemented by low-voltage devices to receive the high-voltage input signals without gate-oxide reliability problem, is proposed. The new proposed circuit, which can be operated in a 3.3-V signal environment without suffering high-voltage gate-oxide overstress, has been fabricated in a 0.13-/spl mu/m 1/2.5-V 1P8M CMOS process. The experimental results have confirmed that the measured transition threshold voltages of the new proposed Schmitt trigger circuit are about 1 and 2.5 V, respectively. The new proposed Schmitt trigger circuit is suitable for mixed-voltage input-output interfaces to receive input signals and reject input noise. 相似文献
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Low voltage CMOS Schmitt trigger circuits 总被引:1,自引:0,他引:1
Two new low voltage Schmitt trigger circuits are presented which use a dynamic body-bias technique. The first circuit is designed for operation at 1 V. The second circuit, derived from the first circuit, is designed for operation at 0.4 V. Experimental results for the new Schmitt trigger circuits are presented. 相似文献
9.
In the present-day VLSI system, low power design plays a noteworthy role. As we know that, a circuit with higher power consumption can ruin the performance of the system because in the modern world most of the systems are portable. Subsequently, they are functioned by the batteries. Therefore, it is desirable to have a system which operates at lower supply voltages along with maintaining the performance of the system. This low power system can be attained by abating the leakages of the devices up-to an enormous magnitude. In the contemporary VLSI system, a major role is being contributed by the Schmitt trigger circuit. Schmitt trigger is fundamentally a comparator. It is implemented by using a positive feedback. The Schmitt trigger circuit is used in various devices such as buffer, sub-threshold SRAM, sensors and PWM circuit. It is also used in analog to digital converter. The most significant property of the Schmitt trigger is that they provide hysteresis in their voltage transfer curve. Consequently, they provide better noise immunity as compared to their counterparts. Therefore it becomes quite important to enhance the performance of the Schmitt trigger circuit. The power dissipation of the device can be minimized by minimizing the sub-threshold current. The Schmitt trigger circuit is very imperative in producing a clean pulse from the input signal comprising of noise. There are various applications of Schmitt trigger circuit such as in scheming the oscillator circuit, analog to digital converter, function generator, signal conditioning and numerous applications. Thus, it becomes noteworthy to boost its performance by plummeting the leakages and power consumption of the Schmitt trigger circuit. We have realized the Schmitt trigger circuit by the use of FinFET. Therefore, we have got some optimum output in the parameters such as hysteresis width, power consumption and total noise of the Schmitt trigger circuit, but the leakages have been augmented. Thereafter, we have implemented several techniques on the Schmitt trigger circuit to shrink the leakage current, leakage power and other parameters further. We have applied Self Controllable Voltage Level, Adaptive voltage level and MTCMOS technique on the Schmitt trigger circuit using FinFET to further augment the presentation. All the circuits have been simulated in the virtuoso tool of the cadence in 45 nm VLSI domain. We have applied 0.7 V of the supply voltage to perform the simulation and got some tremendous outcome. 相似文献
10.
Kousuke Miyaji Shinji NodaTeruyoshi Hatanaka Mitsue Takahashi Shigeki Sakai Ken Takeuchi 《Solid-state electronics》2011,58(1):34-41
A Single-Cell Self-Boost (SCSB) program scheme is proposed to achieve a 1.0 V power supply operation in Ferroelectric (Fe-) NAND flash memories. The proposed SCSB scheme only self-boosts the channel voltage of the cell to which the program voltage VPGM is applied in the program-inhibit NAND string. The program disturb is well suppressed at the 1.0 V power supply voltage in the proposed program scheme. The power consumption of the Fe-NAND at VCC = 1.0 V decreases by 86% compared with the conventional floating gate (FG-) NAND at VCC = 1.8 V without the degradation of the write speed. The number of NAND chips written simultaneously in Solid-State Drives (SSD) increases by 6.7 times and the 9.3 GB/s write throughput of the Fe-NAND SSD is achieved for an enterprise application. 相似文献
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In VLSIs, soft errors resulting from radiation-induced transient pulses frequently occur. In recent high-density and low-power VLSIs, the operation of systems is seriously affected by not only soft errors occurring on memory systems and the latches of logic circuits but also those occurring on the combinational parts of logic circuits. The existing tolerant methods for soft errors on the combinational parts do not provide enough high tolerant capability with small performance penalty. This paper proposes a class of soft error masking circuits by using a Schmitt trigger circuit and a pass transistor. The paper also presents a construction of soft error masking latches (SEM-latches) capable of masking transient pulses occurring on combinational circuits. Moreover, simulation results show that the proposed method has higher soft error tolerant capability than the existing methods. For supply voltage V DD ?=?3.3 V, the proposed method is capable of masking transient pulses of magnitude 4.0 V or less. 相似文献
16.
Mohammadreza Ashraf Nasser Masoumi 《AEUE-International Journal of Electronics and Communications》2014,68(11):1058-1064
This paper presents a boost converter with variable output voltage and a new maximum power point tracking (MPPT) scheme for biomedical applications. The variable output voltage feature facilitates its usage in a wide range of applications. This is achieved by means of a new low-power self-reference comparator. A new modified MPPT scheme is proposed which improves the efficiency by 10%. Also, to further increase the efficiency, a level converter circuit is used to lower the Vdd of the digital section. The low input voltage requirements allow operation from a thermoelectric generator powered by body heat. Using this approach, a thermoelectric energy harvesting circuit has been designed in a 180 nm CMOS technology. According to HSPICE Simulation results, the circuit operates from input voltages as low as 40 mV and generates output voltages ranging from 1 to 3 V. A maximum power of 138 μW can be obtained from the output of the boost converter which means that the maximum end-to-end efficiency is 52%. 相似文献
17.
This paper concerns the design, the implementation and the validation of a fully integrated front-end receiver for a portable ultrasonic system. This front-end receiver includes a logarithmic preamplification circuit and followed by a programmable-gain compensator. The proposed building blocks largely amplify small amplitude signals, and moderately the large amplitude ones. They also compensate signal attenuation due to its traveling of several human body tissues. The ultrasonic receiver is implemented in CMOS 0.35 m technology. Spectre simulations of the front-end receiver show unity gain bandwidth higher than 100 MHz when driving a load of 1 pF. The expected measurements of the fabricated chip are reported. This chip operates at 3.3 V supply voltages, while maintaining wide common mode rejection ratio, high gain and low input offset voltage. The total power consumption is 15.6 mW and the total chip area is 7.2 mm2 including the digital part needed to program the TGC. 相似文献
18.
本文针对相变存储器编程驱动电路,提出了一种超低输出电压纹波的开关电容型电荷泵。该电荷泵可根据输入电压的不同,自适应工作在2X/1.5X升压模式之间,以获得更高的电源转换效率。相比于传统开关电容型电荷泵,在充电阶段泵电容被充电至预先设定的电压值Vo-VDD(Vo为预期的输出电压);放电阶段,泵电容串联在输入电压VDD与输出端,通过此方法将电荷泵输出端电压稳定在Vo,并有效的降低了由于电荷分享所造成的输出纹波。在中芯国际40nm标准CMOS工艺模型下,对电路进行了仿真验证,结果表明在输入电压为1.6-2.1V,输出2.5V电压,最大负载电流为10mA,输出电压纹波低于4mV,电源效率最高可达91%。 相似文献
19.
Changku Hwang Akira Hyogo Hong-sun Kim Mohammed Ismail Keitaro Sekine 《Analog Integrated Circuits and Signal Processing》2000,25(3):347-350
A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to |V
t
|+2 V
ds,sat
and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 m N-well process with a 3 V supply are given. 相似文献
20.
面向高速光通信系统的应用,提出了一种全速率线性25Gb/s时钟数据恢复电路(Clock and Data Recovery Circuit,CDRC)。CDRC采用了混频器型线性鉴相器和自动锁频技术来实现全速率时钟提取和数据恢复。在设计中没有使用外部参考时钟。基于45nm CMOS工艺,该CDR电路从版图后仿真结果得到:恢复25Gb/s数据眼图的差分电压峰峰值Vpp和抖动峰峰值分别为1.3V和2.93ps;输出25GHz时钟的差分电压峰峰值Vpp和抖动峰峰值分别为1V和2.51ps,相位噪声为-93.6dBc/Hz@1MHz。该芯片面积为1.18×1.07mm2,在1V的电源电压下功耗为51.36mW。 相似文献