1/f noise in n+-p-n microwave transistors

1/f noise measurements in the base current and the collector current of NEC 57807 n⁺-p-n microwave transistors show that the noise is not of the mobility fluctuation type, since the current dependence of S_IR(f) and S_IC(f) differs from the theoretical predictions. The low collector current 1/f noise makes it doubtful whether the mobility fluctuation concept is applicable in this case.     

Calculation from the current-voltage and capacitance-voltage measurements of characteristics parameters of Cd/CdS/n-Si/Au-Sb structure with CdS interface layer grown on n-Si substrate by SILAR method

The CdS thin film has been directly formed on n-type Si substrate to form an interfacial layer between cadmium (Cd) and n-type Si with Successive Ionic Layer Adsorption and Reaction (SILAR) method. An Au-Sb electrode has been used as an ohmic contact. The Cd/CdS/n-Si/Au-Sb structure has demonstrated clearly rectifying behaviour by the current-voltage (I-V) curves studied at room temperature. The characteristics parameters such as barrier height, ideality factor and series resistance of Cd/CdS/n-Si/Au-Sb structure have been calculated from the forward bias I-V and reverse bias C⁻²-V characteristics. The diode ideality factor and the barrier height have been calculated as n = 2.06 and Φ_b = 0.92 eV by applying a thermionic emission theory, respectively. The diode shows non-ideal I-V behaviour with an ideality factor greater than unity that can be ascribed to the interfacial layer, the interface states and the series resistance. At high current densities in the forward direction, the series resistance (R_s) effect has been observed. The values of R_s obtained from dV/d(lnI)-I and H(I)-I plots are near to each others (R_s = 182.24 Ω and R_s = 186.04 Ω, respectively). This case shows the consistency of the Cheung′s approach. In the same way, the barrier height calculated from C⁻² -V characteristics varied from 0.698 to 0.743 eV. Furthermore, the density distribution of interface states (N_ss) of the device has been obtained from the forward bias I-V characteristics. It has been seen that, the N_ss has almost an exponential rise with bias from the mid gap toward the bottom of conduction band.     

Technological Features of Irradiation of Sip+-n-n+ Diodes with Electrons at Elevated Temperatures

The behavior of the lifetime of nonequilibrium charge carriers τ_p, the reverse current I _R, and the forward-voltage drop U _F in electron-irradiated (E _irr = 6 MeV) commercial p ⁺-n-n ⁺ diodes at irradiation temperatures in the range of T _irr = 20–400°C is studied. Studies have been performed for samples fabricated on a single-crystal Si substrate either doped with phosphorus in the course of growth by the Czochralski method (Cz-n-Si:P) or doped with phosphorus by nuclear transmutations, neutron-transmutation doped Si (NTD n-Si:P). It is shown that, by choosing the temperature conditions of technological irradiation, one can solve the problem of attaining small values of τ_p at a minimal increase in U _F and I _R in fast-response diodes. It is established that, in the case of comparable variations in τ_p in the base region of diodes, the best relation between U _F and I _R is observed at T _irr = 300°C in n-Si:P samples doped by the Czochralski method and at T _irr = 350°C in samples doped by reactions induced by thermal neutrons.     

Lateral current flow in thyristors with partially shorted cathodes—II: Three-terminal operation,theory of turn-on area,plasma spreading velocity and the effect of gold doping

The lateral current flow I_G(x) in the p-gate region of a thyristor under three-terminal operation in the high-impedance region is investigated, the cathode except where stated, being partially short-circuited. For the simple model employed it appears that a large fraction of the gate current drive flows out of the shorting dot (SD). In the region of high cathode bias, close to the gate contact, I_G(x) follows a very different—though admittedly estimated—course compared to the two-terminal case of paper (I). It falls in value with increasing distance from the gate contact until V_K the cathode junction voltage bias has fallen to such a low value that I_G(x) starts rising again similarly to the two-terminal case. Estimates are also made of V_K(x) and J_K(x) the cathode current density and a theory of the turn-on area is put forward based upon the assumptions of (a) a much faster n-p-n transistor response compared to the p-n-p section and (b) a critical cathode current density derived from the two-terminal (no SD) breakover condition. The influence of gold doping is surmised in keeping with the measured differences between gold-doped and nominally gold-free devices. Finally, as in paper (I) an expression for effective current gain is sought for three-terminal operation proving successful for an n-p-n transistor but more elusive for a thyristor structure. Nevertheless the equations graphically illustrate the influence of the SD in reducing the applied gate drive to an effective gate drive. Approximate analytical solutions are obtained for I_G(x), J_K(x) and turn-on area, the latter two also as a function of gate drive. This solution also yields important constants of the theory. Initial computer calculations confirm this.     

Analysis of interface states and series resistance of MIS Schottky diodes using the current-voltage (I-V) characteristics

The purpose of this paper is to analyze interface states in Al/SiO₂/p-Si (MIS) Schottky diodes and determine the effect of SiO₂ surface preparation on the interface state energy distribution. The current-voltage (I-V) characteristics of MIS Schottky diodes were measured at room temperature. From the I-V characteristics of the MIS Schottky diode, ideality factor (n) and barrier height (Φ_B) values of 1.537 and 0.763 eV, respectively, were obtained from a forward bias I-V plot. In addition, the density of interface states (N_ss) as a function of (E_ss-E_v) was extracted from the forward bias I-V measurements by taking into account both the bias dependence of the effective barrier height (Φ_e), n and R_s for the MIS Schottky diode. The diode shows non-ideal I-V behaviour with ideality factor greater than unity. In addition, the values of series resistance (R_s) were determined using Cheung’s method. The I-V characteristics confirmed that the distribution of N_ss, R_s and interfacial insulator layer are important parameters that influence the electrical characteristics of MIS Schottky diodes.     

Correlation impedance in transistors at high injection

It is shown that the correlation impedance R_cor of a p⁺-n-p transistor at high injection and low frequencies is given as $\text{R}{}_{\mathrm{<mtext>cor</mtext>}}\text{= 2(}\text{μ}{}_{\mathrm{<mtext>p</mtext>}}\text{μ}{}_{\mathrm{n}}\text{)(}\text{k}\text{T}\text{q}\text{I}{}_{\mathrm{<mtext>Ep</mtext>}}\text{)}$, which is small for silicon transistors. For n⁺-p-n transistors under the same conditions $\text{R}{}_{\mathrm{<mtext>cor</mtext>}}\text{= 2(}\text{μ}{}_{\mathrm{n}}\text{μ}{}_{\mathrm{p}}\text{)(}\text{k}\text{T}\text{q}\text{I}{}_{\mathrm{<mtext>EP</mtext>}}\text{)}$, which is large for silicon transistors. This strong asymmetry between p⁺-n-p and n⁺-p-n silicon transistors should be measurable.     

Effect of series resistance on the electrical characteristics and interface state energy distributions of Sn/p-Si (MS) Schottky diodes

In this study, electrical characteristics of the Sn/p-type Si (MS) Schottky diodes have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) measurements at room temperature. The barrier height obtained from C-V measurement is higher than obtained from I-V measurement and this discrepancy can be explained by introducing a spatial distribution of barrier heights due to barrier height inhomogeneities, which are available at the nanostructure Sn/p-Si interface. A modified Norde’s function combined with conventional forward I-V method was used to extract the parameters including barrier height (Φ_b) and the series resistance (R_S). The barrier height and series resistance obtained from Norde’s function was compared with those from Cheung functions. In addition, the interface-state density (N_SS) as a function of energy distribution (E_SS-E_V) was extracted from the forward-bias I-V measurements by taking into account the bias dependence of the effective barrier height (Φ_b) and series resistance (R_S) for the Schottky diodes. While the interface-state density (N_SS) calculated without taking into account series resistance (R_S) has increased exponentially with bias from 4.235 × 10¹² cm⁻²eV⁻¹ in (E_SS - 0.62) eV to 2.371 × 10¹³ cm⁻²eV⁻¹ in (E_SS - 0.39) eV of p-Si, the N_SS obtained taking into account the series resistance has increased exponentially with bias from of 4.235 × 10¹² to 1.671 × 10¹³ cm⁻²eV⁻¹ in the same interval. This behaviour is attributed to the passivation of the p-doped Si surface with the presence of thin interfacial insulator layer between the metal and semiconductor.     

Increasing the current-handling capability of TIL GTO thyristors up to its limits—I. Analysis and design

A rigorous analysis of the novel two-interdigitation levels gate turn-off thyristors (TIL GTOs) is performed with the aim of increasing their current-handling capability up to their limits. A closed form relationship correlating the maximum controllable anode current I_ATO with the peculiar geometry of the TIL pattern and the main technological parameters is obtained. Design rules with general validity are set out for the worst premises and correlated with the physics underlying the peculiar behaviour of TIL GTOs in various modes of operation. Based on the advanced three-transistor model of the TIL GTO structure, the basic theory underlying the device behaviour in the ‘on’ state is developed. The mechanisms of the current balancing between the two types of p-n-p-n sections (standard and quasi-non-regenerative) constituting the TIL GTO structure are disclosed. The broad implications of the current balancing on the current-handling capability of devices are presented in detail. The optimized design criteria were applied to 4 × 4 mm area, TO-220-packed TIL GTOs. The projected value of I_ATO in the worst case is 45 A, which would be the highest value of I_ATO ever reported in the literature for this class of GTOs (identical device area and case).     

Ta/Si Schottky diodes fabricated by magnetron sputtering technique

Electrical properties of Ta/n-Si and Ta/p-Si Schottky barrier diodes obtained by sputtering of tantalum (Ta) metal on semiconductors have been investigated. The characteristic parameters of these contacts like barrier height, ideality factor and series resistance have been calculated using current voltage (I-V) measurements. It has seen that the diodes have ideality factors more than unity and the sum of their barrier heights is 1.21 eV which is higher than the band gap of the silicon (1.12 eV). The results have been attributed the effects of inhomogeneities at the interface of the devices and native oxide layer. In addition, the barrier height values determined using capacitance-voltage (C-V) measurements have been compared the ones obtained from I-V measurements. It has seen that the interface states have strong effects on electrical properties of the diodes such as C-V and R_s-V measurements.     

A simplified theory of the p-i-n diode

A simplified theory of the p-i-n diode is developed for the case of heavy injection in the base, and light injection in the end regions. The current I is taken as the fundamental parameter. The carrier densities n₁ and n₂ at the base boundaries are given directly as functions of the current I by means of simple approximate expressions. The approximation improves with increasing base width and increasing current. It is always within 15% of the correct value for base widths of about 2 diffusion lengths or higher. The accuracy is much better still on the voltage drop across the device, as calculated from the approximate equations for the carrier densities within the base.     

Leakage currents over the Surface of CdHgTe-based photodiodes

The leakage current I _p over the surface of Cd_xHg_1−x Te-based photodiodes that have a cutoff wavelength of the photosensitivity spectrum of λ=9.8–11.6 μm and are fabricated by implanting Zn⁺⁺ ions into the p-type solid solution is investigated. The surface character of the I _p current is indicated by a coordinate shift of the peak in the sensitivity profile of n ⁺-p junctions, which is measured in a scanning mode by the beam of a CO₂ laser with a wavelength of 10.6 μm, with an increase in voltage U across the photodiode and the shift of spectral characteristics to shorter wavelengths with increasing U. __________ Translated from Fizika i Tekhnika Poluprovodnikov, Vol. 38, No. 7, 2004, pp. 890–895. Original Russian Text Copyright ? 2004 by Biryulin, Turinov, Yakimov.     

Traps centers and deep defects contribution in current instabilities for AlGaN/GaN HEMT's on silicon and sapphire substrates

AlGaN/GaN high electron mobility transistors (HEMTs) with Si and Al₂O₃ substrates reveals anomalies on I_ds-V_ds-T and I_gs-V_gs-T characteristics (degradation in drain current, kink effect, barrier height fluctuations, etc.). Stress and random telegraph signal (RTS) measurements prove the presence of trap centers responsible for drain current degradation. An explanation of the trapping mechanism responsible for current instabilities is proposed. Deep defects analysis performed by capacitance transient spectroscopy (C-DLTS), frequency dispersion of the output conductance (G_ds(f)), respectively, on gate/source and drain/source contacts and RTS prove the presence of deep defects localized, respectively, in the gate and in the channel regions. Defects detected by C-DLTS and G_ds(f) are strongly correlated, respectively, to barrier height inhomogeneities and kink anomalies. Gate current analysis confirms the presence of (G-R) centers acting like traps at the interface GaN/AlGaN. Finally, the localization of these traps defects is proposed.     

Degradation of solar cell performance by areal inhomogeneity

Calculations have been made that show how severely areal inhomogeneity can degrade solar-cell conversion efficiency. Two general types of areal inhomogeneity are discussed. In the first type, the emitter recombination current controls the I-V characteristics for voltages near the maximum power voltage, and areal variations in the structural or material parameters of the emitter are assumed to occur. For this type of areal inhomogeneity, the base recombination current controls the dark I-V characteristics, and areal variations in the base minority-carrier lifetime are assumed to occur. For this type, the poor-quality area again dominates in determining the conversion efficiency, though less strongly than for the first type of areal inhomogeneity. An extension of the method used to demonstrate this behavior can provide a first-order solution of the general three-dimensional boundary-value problem resulting from areal inhomogeneity; this extension is briefly described.     

Effect of substrate generation current on oxide I-V measurement on p-type MOS structures

The values of the bulk generation current and surface generation current extracted from slow ramp I-V and C-V measurements of p-type substrate MOS capacitors are found to be consistent with the results from transient capacitance measurement. The shape of the I-V curve for high positive gate biases is found to depend on the formation of a deep depletion region in the p-type substrate.     

The one-lump Linvill model of a semiconductor region with arbitrary doping profile and recombination. Application for a model of lateral transistor

The current space-dependent due to recombination, and likewise the concentration of minority carriers exceeding equilibrium can be described as function series in a particular case when the carrier concentration is zero at one boundary of the examined region. By superimposing two series where this requirement is fulfilled at the two opposite boundaries, the general solutions of current and the minority carrier concentration are demonstrated. Using the general solution of the current, the one-lump Linvill model of a region with arbitrary doping profile is determined. As an example of this method, the one-lump model of the p-n-p lateral transistor was developed. By calculating the currents in the model arms, the d.c. current gain, the frequency limit f_T and I_{c max} are determined.     

The influence of heavy doping effects on the reverse recovery storage time of a diode

During the reverse recovery process in a modern Si p-n junction diode, the value of J_EO/J_BO (the ratio of emitter to base dark saturation currents) increases and the recombination of carriers in the emitter becomes important due to heavy doping effects. A theory is developed to take these effects into account. The emitter and the base components of the current during the reverse recovery phase are found to vary with time. However, their sum remains equal to the constant reverse current J_R, which flows in the external circuit. The ratio of the total quantity of charge present in the base to that present in the emitter is found to increase rapidly with time. Values of the storage time t_s for different values of J_EO/J_BO are calculated. In a typical case, the storage time is reduced by a factor 5 in a diode with J_EO/J_BO = 2. In such cases, the values of lifetime τ_B calculated using measured t_s values and the Kingston's formula, become inaccurate. Theoretical expression for the total charge Q_BS left in the base at t = t_s in a base dominated diode is derived.An earlier semi-empirical formula known as Kuno's formula is derived theoretically. It is found that the formula is valid both for the base dominated diode as well as in a diode with large contribution of the emitter but only when J_R/J_F is small. According to this formula t_s vs 1n(1 + J_F/J_R) plot is approximately a straight line with slope approximately equal to τ_B in both cases. For large values of J_R/J_F when t_s values are small, the correct formula shows that the plot is highly curved. An analysis of this part of the curve yields a value of J_EO/J_BO.     

Some aspects of current gain variations in bipolar transistors

This paper deals with the study of the main mechanisms involved in the bipolar transistor current-gain variations.In the first part, we describe some properties of characteristic parameters N_S and I_SR of the surface “diode”; an attempt is made to explain the strong correlation between N_S and I_SR.In a second part, we analyse the influence of emitter current crowding, high injection in the base region, and base widening effects on the high level bias current gain value. Critical current densities beyond which each of these effects takes place are defined, allowing us to evaluate their comparative importance at a given collector current value. Our study shows that, on the one hand, for transistors affected by emitter-current crowding, the surface currents play an essential part in the high level bias current gain fall off and, on the other hand, the base widening effect has a very great influence on the static (I_C, V_EB) characteristic and on the emitter injection efficiency value.In the third part, the experimental results obtained are reported and compared with previously proposed analytical relations.     

Improvement in the light conversion efficiency of silicon solar cells by pure hydrogen annealing

In this report, the effects of pure hydrogen gas annealing on series resistance (R_s), shunt resistance (R_sh), open circuit voltage (V_oc), short circuit current (I_sc), fill factor, and efficiency were investigated systematically using standard, commercially available polysilicon solar cells. Improvements on the electrical characteristics, fill factors, and efficiency of the solar cells were observed after annealing by pure hydrogen gas at 350 °C for 15 min. In the best case, the conversion efficiency was raised by nearly 1% point. Judging from our experimental evidences, the improvement on cell performance could be mostly attributed to the reduction of R_s and improvement in Ag grid/emitter contact resistance in the cells during the annealing process.     

On the current-voltage characteristics of epitaxial Schottky barrier diodes

The J-V characteristics of epitaxial Schottky barrier diodes are analyzed. Based on the assumption of negligible recombination in the epitaxial layer, formal solution from which the J-V characteristics can be calculated is derived. The solution is valid for all injection levels and reduces to the form I = I_s[exp (q(V?IR)/kT) ? 1], where R is the series resistance of the epitaxial layer, under C12 C12V low-injection conditions. The analysis is justified by very close correspondence with exact numerical calculations using the Finite Element Device Analysis Program (FIELDAY) in which thermionic emission boundary conditions are implemented for both electrons and holes. It is shown that for low barrier Schottky diodes the minority carrier injection is negligible and the expression I = I_s[exp (q(V?IR)/kT) ? 1] describes the I-V characteristics over large bias range. For high barrier C12 C12 V Schottky diodes the exact solution must be used as minority carriers are injected and the series resistance is decreased due to conductivity modulation effect.     

On the profile of frequency and voltage dependent interface states and series resistance in (Ni/Au)/Al0.22Ga0.78N/AlN/GaN heterostructures by using current-voltage (I-V) and admittance spectroscopy methods

In order to explain the experimental effect of interface states (N_ss) and series resistance (R_s) of device on the non-ideal electrical characteristics, current-voltage (I-V), capacitance-voltage (C-V) and conductance-voltage (G/ω-V) characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures were investigated at room temperature. Admittance measurements (C-V and G/ω-V) were carried out in frequency and bias voltage ranges of 2 kHz-2 MHz and (−5 V)-(+5 V), respectively. The voltage dependent R_s profile was determined from the I-V data. The increasing capacitance behavior with the decreasing frequency at low frequencies is a proof of the presence of interface states at metal/semiconductor (M/S) interface. At various bias voltages, the ac electrical conductivity (σ_ac) is independent from frequencies up to 100 kHz, and above this frequency value it increases with the increasing frequency for each bias voltage. In addition, the high-frequency capacitance (C_m) and conductance (G_m/ω) values measured under forward and reverse bias were corrected to minimize the effects of series resistance. The results indicate that the interfacial polarization can more easily occur at low frequencies. The distribution of N_ss and R_s is confirmed to have significant effect on non-ideal I-V, C-V and G/ω-V characteristics of (Ni/Au)/Al_0.22Ga_0.78N/AlN/GaN heterostructures.