Simulation and Fabrication Studies of Semi‐superjunction Trench Power MOSFETs by RSO Process with Silicon Nitride Layer

In this letter, we propose a new RESURF stepped oxide (RSO) process to make a semi‐superjunction (semi‐SJ) trench double‐diffused MOSFET (TDMOS). In this new process, the thick single insulation layer (SiO₂) of a conventional device is replaced by a multilayered insulator (SiO₂/SiN_x/TEOS) to improve the process and electrical properties. To compare the electrical properties of the conventional RSO TDMOS to those of the proposed TDMOS, that is, the nitride_RSO TDMOS, simulation studies are performed using a TCAD simulator. The nitride_RSO TDMOS has superior properties compared to those of the RSO TDMOS, in terms of drain current and on‐resistance, owing to a high nitride permittivity. Moreover, variations in the electrical properties of the nitride_RSO TDMOS are investigated using various devices, pitch sizes, and thicknesses of the insulator. Along with an increase of the device pitch size and the thickness of the insulator, the breakdown voltage slowly improves due to a vertical field plate effect; however, the drain current and on‐resistance degenerate, owing to a shrinking of the drift width. The nitride_RSO TDMOS is successfully fabricated, and the blocking voltage and specific on‐resistance are 108 V and 1.1 mΩcm², respectively.     

High‐Performance,Air‐Stable,Top‐Gate,p‐Channel WSe2 Field‐Effect Transistor with Fluoropolymer Buffer Layer

High‐performance, air‐stable, p‐channel WSe₂ top‐gate field‐effect transistors (FETs) using a bilayer gate dielectric composed of high‐ and low‐k dielectrics are reported. Using only a high‐k Al₂O₃ as the top‐gate dielectric generally degrades the electrical properties of p‐channel WSe₂, therefore, a thin fluoropolymer (Cytop) as a buffer layer to protect the 2D channel from high‐k oxide forming is deposited. As a result, a top‐gate‐patterned 2D WSe₂ FET is realized. The top‐gate p‐channel WSe₂ FET demonstrates a high hole mobility of 100 cm²_­ V^?1 s^?1 and a I_ON/I_OFF ratio > 10⁷ at low gate voltages (V_GS ca. ?4 V) and a drain voltage (V_DS) of ?1 V on a glass substrate. Furthermore, the top‐gate FET shows a very good stability in ambient air with a relative humidity of 45% for 7 days after device fabrication. Our approach of creating a high‐k oxide/low‐k organic bilayer dielectric is advantageous over single‐layer high‐k dielectrics for top‐gate p‐channel WSe₂ FETs, which will lead the way toward future electronic nanodevices and their integration.     

20.0% Efficiency Si Nano/Microstructures Based Solar Cells with Excellent Broadband Spectral Response

Spectral response of solar cells determines the output performance of the devices. In this work, a 20.0% efficient silicon (Si) nano/microstructures (N/M‐Strus) based solar cell with a standard solar wafer size of 156 × 156 mm² (pseudo‐square) has been successfully fabricated, by employing the simultaneous stack SiO₂/SiN_x passivation for the front N/M‐Strus based n⁺‐emitter and the rear surface. The key to success lies in the excellent broadband spectral responses combining the improved short‐wavelength response of the stack SiO₂/SiN_x passivated Si N/M‐Strus based n⁺‐emitter with the extraordinary long‐wavelength response of the stack SiO₂/SiN_x passivated rear reflector. Benefiting from the broadband spectral response, the highest open‐circuit voltage (V_oc) and short‐circuit current density (J_sc) reach up to 0.653 V and 39.0 mA cm^?2, respectively. This high‐performance screen‐printed Si N/M‐Strus based solar cell has shown a very promising way to the commercial mass production of the Si based high‐efficient solar cells.     

Novel Multistate Quantum Dot Gate FETs Using SiO2 and Lattice-Matched ZnS-ZnMgS-ZnS as Gate Insulators

Multistate behavior has been achieved in quantum dot gate field-effect transistor (QDGFET) configurations using either SiO _x -cladded Si or GeO _x -cladded Ge quantum dots (QDs) with asymmetric dot sizes. An alternative method is to use both SiO _x -cladded Si and GeO _x -cladded Ge QDs in QDGFETs. In this paper, we present experimental verification of four-state behavior observed in a QDGFET with cladded Si and Ge dots site-specifically self-assembled in the gate region over a thin SiO₂ tunnel layer on a Si substrate. This paper also investigates the use of lattice-matched high-κ ZnS-ZnMgS-ZnS layers as a gate insulator in mixed-dot Si QDGFETs. Quantum-mechanical simulation of the transfer characteristic (I _D–V _G) shows four-state behavior with two intermediate states between the conventional ON and OFF states.     

Normally-off AlGaN/AlN/GaN/Si oxide-passivated HEMTs and MOS-HEMTs by using CF4 plasma and ozone water oxidization treatment

The letter reports normally-off device characteristics of Al_0.26Ga_0.74N/AlN/GaN oxide-passivated high electron mobility transistors (HEMTs) and metal-oxide-semiconductor HEMTs (MOS-HEMTs) grown on a Si substrate. Al₂O₃ was formed as the surface passivation oxide or gate dielectric on a thin AlGaN barrier layer by using a cost-effective ozone water oxidization technique. CF₄ plasma was used to enable normally-off operation. For the gate dimensions of 1×100 µm², the present oxide-passivated HEMT and MOS-HEMT (a control Schottky-gate HEMT) have demonstrated superior on/off-current ratio (I_on/I_off) of 2.5×10⁶ and 1×10⁷ (3.9×10³), maximum extrinsic transconductance (g_{m, max}) of 154 and 175 (120) mS/mm, maximum drain-source current density (I_{DS, max}) of 312 and 349 (300) mA/mm, two-terminal gate-drain breakdown voltage (BV_GD) of −80 and −140 (−36) V, turn-on voltage (V_on) of 1.2 and 1.3 (1) V, and three-terminal on-state breakdown voltage (BV_DS) of 93 and 109 (48) V. Excellent BV_GD and BV_DS enhancements of 122% (288%) and 94% (127%) are achieved in the present oxide-passivated HEMT (MOS-HEMT) design.     

SiC JBS二极管和SiC MOSFET的空间辐照效应及机理

基于第六代650 V碳化硅结型肖特基二极管(SiC JBS Diode)和第三代900 V碳化硅场效应晶体管(SiC MOSFET),开展SiC功率器件的单粒子效应、总剂量效应和位移损伤效应研究。20～80 MeV质子单粒子效应实验中,SiC功率器件发生单粒子烧毁(SEB)时伴随着波浪形脉冲电流的产生,辐照后SEB器件的击穿特性完全丧失。SiC功率器件发生SEB时的累积质子注量随偏置电压的增大而减小。利用计算机辅助设计工具(TCAD)开展SiC MOSFET的单粒子效应仿真,结果表明,重离子从源极入射器件时,具有更短的SEB发生时间和更低的SEB阈值电压。栅-源拐角和衬底-外延层交界处为SiC MOSFET的SEB敏感区域,强电场强度和高电流密度的同时存在导致敏感区域产生过高的晶格温度。SiC MOSFET在栅压偏置(U_GS=3 V,U_DS=0 V)下开展钴源总剂量效应实验,相比于漏压偏置(U_GS=0 V,U_DS=300 V)和零压偏置(U_GS=U_DS=0...     

Fabrication of Metal–Oxide–Diamond Field-Effect Transistors with Submicron-Sized Gate Length on Boron-Doped (111) H-Terminated Surfaces Using Electron Beam Evaporated SiO<Subscript>2</Subscript> and Al<Subscript>2</Subscript>O<Subscript>3</Subscript>

A H-terminated surface conductive layer of B-doped diamond on a (111) surface was used to fabricate a metal–oxide–semiconductor field-effect transistor (MOSFET) using an electron beam evaporated SiO₂ or Al₂O₃ gate insulator and a Cu-metal stacked gate. When the bulk carrier concentration was approximately 10¹⁵/cm³ and the B-doped diamond layer was 1.5 μm thick, the surface carrier mobility of the H-terminated surface on the (111) diamond before FET processing was 35 cm²/Vs and the surface carrier concentration was 1.5 × 10¹³/cm². For the SiO₂ gate (0.76 μm long and 50 μm wide), the maximum measured drain current at a gate voltage of −3.0 V was −75 mA/mm and the maximum transconductance was 24 mS/mm, and for the Al₂O₃ gate (0.64 μm long and 50 μm wide), these features were −86 mA/mm and 15 mS/mm, respectively. These values are among the highest reported direct-current (DC) characteristics for a diamond homoepitaxial (111) MOSFET.     

DC and pulsed measurements of on-state breakdown voltage in GaAs MESFETs and InP-based HEMTs

The BV_DS–I_D breakdown characteristics of MESFET and HEMT devices measured at constant gate current are correlated with conventional measurements of gate current due to impact-ionization. The influence of thermal effects on breakdown DC measurements is demonstrated. By adopting pulsed measurements, we confirm that on-state breakdown voltage of InP HEMTs decreases by increasing the temperature, while the opposite occurs in GaAs based MESFETs and HEMTs. We show that DC measurements are not suitable for evaluating on-state breakdown of power MESFETs and HEMTs, and we propose pulsed measurements as a viable alternative.     

MOSFET output characteristics after oxide breakdown

The performance of nMOSFETs after the gate oxide (SiO₂) dielectric breakdown (BD) has been studied. Different BD hardness, BD path locations along the channel and device aspect ratios have been considered. The results show that the BD of the gate oxide affects the overall I_D-V_DS characteristics and that the BD impact depends on BD hardness and location and device geometry. To describe the post-BD data, a simple BD MOSFET model has been used, which accounts for the after BD additional gate current and drain current effects. The model is able to fit all the observed post-BD behaviours and can be easily included in a circuit simulator, to evaluate the impact of device BD on the post-BD performance of circuits.     

Analog and radio-frequency performance analysis of silicon-nanotube MOSFETs

This work presents a comparative study of the influence of various parameters on the analog and RF properties of silicon-nanotube MOSFETs and nanowire-based gate-all-around (GAA) MOSFETs. The important analog and RF performance parameters of SiNT FETs and GAA MOSFETs, namely drain current (I_d), transconductance to drain current ratio (g_m/I_d), I_on/I_off, the cut-off frequency (f_T) and the maximum frequency of oscillation (f_MAX) are evaluated with the help of Y- and H-parameters which are obtained from a 3-D device simulator, ATLAS^TM. It is found that the silicon-nanotube MOSFETs have far more superior analog and RF characteristics (g_m/I_d, f_T and f_MAX) compared to the nanowire-based gate-all-around GAA MOSFETs. The silicon-nanotube MOSFET shows an improvement of~2.5 and 3 times in the case of f_T and f_MAX values respectively compared with the nanowire-based gate-all-around (GAA) MOSFET.     

Gate leakage properties of MOS devices with tri-layer high-k gate dielectric

Gate leakage of deep-submicron MOSFET with stack high-k dielectrics as gate insulator is studied by building a model of tunneling current. Validity of the model is checked when it is used for MOSFET with SiO₂ and high-k dielectric material as gate dielectrics, respectively, and simulated results exhibit good agreement with experimental data. The model is successfully used for a tri-layer gate-dielectric structure of HfON/HfO₂/HfSiON with a U-shape nitrogen profile and a like-Si/SiO₂ interface, which is proposed to solve the problems of boron diffusion into channel region and high interface-state density between Si and high-k dielectric. By using the model, the optimum structural parameters of the tri-layer dielectric can be determined. For example, for an equivalent oxide thickness of 2.0 nm, the tri-layer gate-dielectric MOS capacitor with 0.3-nm HfON, 0.5-nm HfO₂ and 1.2-nm HfSiON exhibits the lowest gate leakage.     

Approach for Al2O3 rear surface passivation of industrial p‐type Si PERC above 19%

Atomic layer deposition (ALD) of thin Al₂O₃ (≤10 nm) films is used to improve the rear surface passivation of large‐area screen‐printed p‐type Si passivated emitter and rear cells (PERC). A blister‐free stack of Al₂O₃/SiO_x/SiN_x is developed, leading to an improved back reflection and a rear recombination current (J_0,rear) of 92 ± 6 fA/cm². The Al₂O₃/SiO_x/SiN_x stack is blister‐free if a 700°C anneal in N₂ is performed after the Al₂O₃ deposition and prior to the SiO_x/SiN_x capping. A clear relationship between blistering density and lower open‐circuit voltage (V_OC) due to increased rear contacting area is shown. In case of the blister‐free Al₂O₃/SiO_x/SiN_x rear surface passivation stack, an average cell efficiency of 19.0% is reached and independently confirmed by FhG‐ISE CalLab. Compared with SiO_x/SiN_x‐passivated PERC, there is an obvious gain in V_OC and short‐circuit current (J_SC) of 5 mV and 0.2 mA/cm², respectively, thanks to improved rear surface passivation and rear internal reflection. Copyright © 2012 John Wiley & Sons, Ltd.     

Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric

In this paper, the length scaling of the silicon Double Gate Tunnel Field Effect Transistor (DG Tunnel FET) is studied. It is found that scaling limits are reached sooner by Tunnel FETs with an SiO₂ gate dielectric, while those with a high-K dielectric can be scaled further before threshold voltage, and average and point subthreshold swing are affected. It is demonstrated that the scaling of the high-K Tunnel FET is completely different than that of conventional MOS transistors. An outstanding feature of the Tunnel FET switch is that length scaling has a much weaker impact on device characteristics than does gate control (e.g. the use of a high-K dielectric), which primarily dictates the tunneling barrier width and consequently, device conduction. This paper demonstrates that while some improvements are observed, the length scaling does not dramatically affect switch figures of merit such as subthreshold slope, I_on and I_off down to about 20 nm, and an optimized device design can be extended over a much larger window of sub-micron dimensions, compared to the MOSFET. A discussion of the length dependence of the transconductance, g_m, and output conductance, g_ds of the Tunnel FET is presented for the first time.     

An investigation of surface state capture cross-sections for metal–oxide–semiconductor field-effect transistors using HfO2 gate dielectrics

MOSFETs and MOSCs incorporating HfO₂ gate dielectrics were fabricated. The I_DS–V_DS, I_DS–V_GS, gated-diode and C–V characteristics were investigated. The subthreshold swing and the interface trap density were obtained. The surface recombination velocity and the minority carrier lifetime in the field-induced depletion region measured from the gated diodes were about 2.73 × 10³ cm/s and 1.63 × 10⁻⁶ s, respectively. The effective capture cross section of surface state was determined to be 1.6 × 10⁻¹⁵ cm² using the gated-diode technique in comparison with the subthreshold swing measurement. A comparison with conventional MOSFETs using SiO₂ gate oxide was also made.     

High Tg Cyclic Olefin Copolymer Gate Dielectrics for N,N′‐Ditridecyl Perylene Diimide Based Field‐Effect Transistors: Improving Performance and Stability with Thermal Treatment

A novel application of ethylene‐norbornene cyclic olefin copolymers (COC) as gate dielectric layers in organic field‐effect transistors (OFETs) that require thermal annealing as a strategy for improving the OFET performance and stability is reported. The thermally‐treated N,N′‐ditridecyl perylene diimide (PTCDI‐C13)‐based n‐type FETs using a COC/SiO₂ gate dielectric show remarkably enhanced atmospheric performance and stability. The COC gate dielectric layer displays a hydrophobic surface (water contact angle = 95° ± 1°) and high thermal stability (glass transition temperature = 181 °C) without producing crosslinking. After thermal annealing, the crystallinity improves and the grain size of PTCDI‐C13 domains grown on the COC/SiO₂ gate dielectric increases significantly. The resulting n‐type FETs exhibit high atmospheric field‐effect mobilities, up to 0.90 cm² V^?1 s^?1 in the 20 V saturation regime and long‐term stability with respect to H₂O/O₂ degradation, hysteresis, or sweep‐stress over 110 days. By integrating the n‐type FETs with p‐type pentacene‐based FETs in a single device, high performance organic complementary inverters that exhibit high gain (exceeding 45 in ambient air) are realized.     

Experimental characterisation of PD SOI MOSFET devices fabricated with diamond-shaped body contact

The design of diamond-shaped body-contacted (DSBC) devices using standard layers in a 0.35?µm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor process is described in this article. The technology is based on a manufacturable partially depleted SOI process targeted for radio frequency applications. The experimental measurements of drain induced barrier lowering for the fabricated DSBC structure showed suppression of floating body effects (FBE) at the promising rate of 24?mV/V. The measurement results confirmed current drive (I _DS) improvement by 25% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional body-tied-source (BTS) device. A constant and steady output conductance (g _DS) in the saturation region was observed for the DSBC structure. The gate trans-conductance (g _m) is improved by 34% at V _DS?=?1.5?V and V _GS?=?1.5?V compared to conventional BTS device. Three-dimensional device simulation provides insight on FBE suppression and channel current improvement. Experimental results confirmed the area efficiency of the DSBC structure and its excellent current drive performance.     

Effects of quantization on random telegraph signals observed in deep-submicron MOSFETs

Random telegraph signals (RTS) have been investigated in the drain to source voltage of W_eff×L_eff=1.37×0.17 μm² medium-doped drain (MDD) n-type MOSFETs. The emission (τ_e) and capture (τ_c) times of the probed trap were studied as a function of gate voltage as well as substrate voltage. The small size and high doping density of the n-MOSFETs studied create a strong electric field in the MOSFET inversion layer, which makes the surface conduction band split into discrete energy levels. Therefore, modified expressions of τ_e and τ_c including the influence of bulk bias (V_SB), which changes the degree of quantization, are presented. The trap position in the oxide with respect to the Si–SiO₂ interface, and the trap energy, were calculated from the gate voltage dependence of the emission and capture times under different bulk bias conditions. The behavior of the emission and capture times predicted by the two-dimensional (2D) surface quantization effects is in qualitative agreement with the experimental results. The RTS amplitude (ΔV_DS/V_DS) shows a positive dependence on V_SB. The coefficient α for screened oxide charge scattering was calculated at different gate voltages and bulk bias from the RTS amplitude. In addition, the theoretical calculation of the scattering coefficient α, using a 2D surface mobility fluctuation model, was presented, which shows a good agreement with the experimental data.     

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported,to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions.This novel structure offers low barrier height at the source and offers high ON-state current.The ION/IoFF of ISE-CGAA-SB-MOS-FET increases by 1177 times and offers steeper subthreshold slope (～60 mV/decade).However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate,dual metal gate,single metal gate with ISE,and dual metal gate with ISE has been presented.The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design.The numerical simulation is performed using the ATLAS-3D device simulator.     

AlGaN/GaN metal-oxide semiconductor heterostructure field-effect transistor with photo-chemical-vapor deposition SiO<Subscript>2</Subscript> gate oxide

High-quality SiO₂ was successfully deposited onto GaN by photo-chemicalvapor deposition (photo-CVD) using a D₂ lamp as the excitation source. The AlGaN/GaN metal-oxide semiconductor, heterostructure field-effect transistors (MOSHFETs) were also fabricated with photo-CVD oxide as the insulating layer. Compared with AlGaN/GaN metal-semiconductor HFETs (MESHFETs) with similar structure, we found that we could reduce the gate-leakage current by more than four orders of magnitude by inserting the photo-CVD oxide layer in between the AlGaN/GaN and the gate metal. With a 2-μm gate, it was found that the saturated I_ds, maximum g_m, and gate-voltage swing (GVS) of the fabricated nitride-based MOSHFET were 512 mA/mm, 90.7 mS/mm, and 6 V, respectively.