Hot-carrier memory effect in an Al/SiN/SiO2/Si MNOS diode due to electrical stress

An Al/SiN(70 Å)/SiO2(126 Å)/(p)Si MNOS diode was fabricated by using the LOCOS process. The interface trap densities at SiN-SiO2and at the SiO2-Si interface were measured by a CV method. Successive stresses of biasing at -20 V introduces both trap densities. Memory effect of the flat-band shifts was observed. The electron traps were first produced at the SiN-SiO2interface. In addition, the hole traps were also produced owing to the two-step barrier formation in the insulators. Fowler-Nordheim tunneling may be responsible for the trapping in the oxide. The hole traps can be annealed while the electron traps cannot be.     

Endurance of thin-oxide nonvolatile MNOS memory transistors

A discussion of the factors which determine the endurance of thin-oxide MNOS memory transistors is presented. Si-SiO2interface states are influential in the early stages of erase/write cycling, while charge movement into the nitride controls the long term cycling characteristics. Other important variables include the method of preparation of the thin-oxide region, its composition, dielectric properties and thickness; the high density of spatially localized traps near the nitride-oxide interface; the low conductivity Si3N4dielectric, and electric field strengths. Optimizing these variables permits MNOS memory transistors to be operated with high endurance, reliably to beyond 10¹⁰erase/write cycles with ±20-V, 100-µs pulses and demonstrate a minimum 2-V memory window at 2900 h retention time.     

Trapping,emission and generation in MNOS memory devices

This study is concerned with trapping phenomena occuring at the semiconductor-oxide interface and in the nitride layer of variable-threshold metal-nitride-oxide-semiconductor (MNOS) memory devices. The technique consits of biasing the device in such a manner as to charge or discharge either the interface traps or the nitride traps, or both sets of traps simultaneously. The device is then cooled to low temperature with the bias still applied, and at the low temperature the biasing condition is changed, in order to induce the device into a non-steady mode that is quasi-stable at the low temperature. The temperature of the device is then raised at a constant rate, and the resulting current vs temperature (I-T) characteristics is found to be rich in structure. By means of a series of systematic experiments the various portions of the I-T characteristic are identified with emission of electrons from interface states and the nitride traps, and surface generation. From this data the energy distribution of interface states is determied. It is shown that the memory charge in the nitride is distributed throughout the nitride, and temporary memory charge and semi-permanent memory charge are distinguished.     

Determination of the energy distribution of interface traps in MIS systems using non-steady-state techniques

Experimental techniques are described for determining the energy distribution of interface traps at the semiconductor-insulator interface of MIS devices. The device used here was an MNOS capacitor in which the semiconductor was n-type. The first technique which is described is that of measuring the thermally stimulated currents. The method consists of biasing the capacitor into the accumulation mode at a low temperature thereby filling the traps at the semiconductor oxide interface. The device is then biased into the deep-depletion mode in which state the traps remain filled because the temperature is too low to allow the electrons to be thermally excited out of the traps. The temperature of the device is then raised at a uniform rate, and the current associated with the release of electrons from the trap is monitored. The shape of the I?T characteristic is a direct image of the interface trap distribution is a broad peak with a maximum at 0·35 eV below the bottom of the conduction band, and of height approximately 6 × 10¹³ cm^?2eV^?1. The experiments were carried out at two heating rates (0·1°K/sec and 0·01°K/sec), and the trap densities so obtained were identical.The second method consists of biasing the device into the accumulation mode at a fixed temperature thereby filling the traps at the silicon-silicon oxide interface. It is then short-circuited and the non-steady state transient current associated with the release of electrons from the interface traps is monitored. The energy distribution of the interface traps in the upper half of the forbidden gap is shown to be readily obtained from the transient currents, and is found to be identical to that obtained using the thermal technique.     

The charging and discharging of high-voltage stress-generated trapsin thin silicon oxide

Excess high-voltage stress-generated low-level leakage currents through 10 nm silicon oxides, previously described as DC currents, are shown to decay to the limit of detection given adequate observation time and, thus, have no discernible component. A physical model is presented which describes the majority of the excess low-level leakage currents in terms of the charging and discharging of traps previously generated by the high voltage stress. Excess low-level leakage currents measured with voltage pulses with polarity opposite to that of the stress voltage are found to contain an additional current component, which is explained by the transient charging and discharging of certain traps inside the oxide. Evidence is presented which suggests that an oxide trap generated by the high-voltage stress can contain either a positive or a negative charge, in addition to being neutral and that the traps are located near both oxide interfaces. All of the trap charging and discharging currents can be explained by the flow of electrons into and out of traps generated by the high voltage stress, without resorting to the flow of holes in the oxide     

Theory of the maximum charge stored in the thin oxide MNOS memory transistor

The maximum charge stored in the thin oxide metal-nitride-oxide-silicon (MNOS) memory transistor is calculated using a previously developed theory for the oxide current and experimental values for the nitride currents. The calculation is performed for oxide thicknesses of 15-50 Å and for six different nitride deposition temperatures. The theoretical results are shown to agree with recently published experimental data.     

The determination of the energy distribution of interface traps in metal-nitride-oxide-silicon (memory) devices using non-steady-state techniques

New techniques are used to study the emission and generation processes through, and to obtain the energy distribution of, interface traps situated throughout the bandgap of MNOS devices. The techniques are based on thermal and isothermal dielectric relaxation current techniques. The trap distribution is observed to contain two peaks, the maxima of which occur at 0·4 eV and 0·74 eV below the bottom of the conduction band. The results of the two techniques compared extremely well, lending confidence to the techniques. It is demonstrated that the techniques are capable of detecting small changes in the trap density, such as might occur due to ageing or temperature cycling.     

MOSFET degradation due to stressing of thin oxide

Oxide and interface traps in 100 Å SiO2created by Fowler-Nordheim tunneling current have been investigated using capacitor C-V, I-V, and transistor I-V measurements. The net oxide trapped charge is initially positive due to hole trapping near the anode interface and, at sufficiently high fluence, it becomes negative due to the trapping of electrons with a centroid of 60 Å from the injector (cathode) interface. Interface traps (Surface states) are created by tunneling electrons flowing to and from the substrate. The interface-trap energy distribution gives a distinct peak at 0.65 eV above the valence band edge. The positive charge trapping and interface traps generation saturate at high electron fluence, but not the electron trap generation. The generation rates for electron traps and interface traps are weak functions of tunneling current density over the range tested. The interface traps cause degradations in subthreshold current slope and surface electron mobility. The threshold-voltage shift can be either positive or negative under the combined influence of the oxide charges and the interface charges.     

Switching mechanism in thin-oxide MNOS devices

The results of pulsed switching experiments and the dcI-Vcharacteristics of thin-oxide (∼20 Å) MNOS devices indicate that the dominant switching mechanism is not necessarily the direct tunneling of electrons to and from states at or near the oxide-nitride interface. Instead, it appears that switching may actually be the result of the tunneling of electrons (holes) from the silicon conduction (valence) band into the nitride conduction (valence) band, with subsequent trapping in the nitride.     

Interpretation of flatband voltage shifts in terms of charge distributions in MNOS structures

It is theoretically shown, how profiles of spatially and energetically distributed trapped charge influence the flatband voltage shift of MNOS capacitors during discharge. A monoenergetic charge density increasing from the oxide-nitride interface towards the gate and a charge distribution over a continuum of energy levels both cause a slower drop of the flatband voltage, whereas a spatial decrease in the charge distribution yields a more rapid change of the flatband voltage. Applied to the experiments, it is shown that for structures with oxides in the range 2–3 nm or when charged with high voltages (30 V) for structures with oxides even thicker than 3 nm, an initial increase in the charge profile was obtained. In the case of tunneling oxides below 2 nm a thin layer close to the oxide-nitride interface is shown to be free of trapped charge. As an extension to the charge profiling the comparison of theory and experiment allows us to determine important discharge parameters, so it is shown that a high temperature treatment of the memory nitride after deposition yields a trap level 0.4 V closer to the bottom of the nitride conduction band.     

Properties of MNOS structures

The properties of thin oxide MNOS structures are studied. An analytical theory for the switching time constant is derived and curves of the switching time constant versus the nitride field are computed. These curves are useful in the design of MNOS-memory transistors. The theory is compared with experiments. The normal current in the thin oxide MNOS structures is assumed to be a modified Fowler-Nordheim current. At small oxide thicknesses and low nitride field, an additional current is shown to exist that is attributed to direct tunneling into traps in the nitride. The discharge of MNOS structures is briefly discussed and is shown to be due to a direct tunneling of charge carriers from traps in the nitride into the semiconductor.     

复合栅控二极管新技术提取热载流子诱生的NMOS/SOI器件界面陷阱的横向分布

提出了用复合栅控二极管新技术提取MOS/SOI器件界面陷阱沿沟道横向分布的原理,给出了具体的测试步骤和方法.在此基础上,对具有体接触的NMOS/SOI器件进行了具体的测试和分析,给出了不同的累积应力时间下的界面陷阱沿沟道方向的横向分布.结果表明:随累积应力时间的增加,不仅漏端边界的界面陷阱峰值上升,而且沿沟道方向,界面陷阱从漏端不断向源端增生.     

Charge distributions in silicon nitride of MNOS devices

Positive charge profiles in the silicon nitride film of MNOS device are investigated in conjunction with the distributions of electron traps and injected electrons which play the most important role on the write/erase operations as a nonvolatile memory. The results are: (1) the donor-like electron traps in the form of positive charges are uniformly distributed in the nitride bulk and the density is approximately 4 × 10¹⁷ cm^?3, (2) the injected electrons are trapped deeply into the nitride, where their depth depends on the magnitude of applied voltage to the gate, (3) the motion of positive charges retained for 50 days, is also measured, resulting in the diffusion coefficient of injected electrons of 10^?20 ～ 10^?19 cm²/sec.     

Memory-window-size-temperature dependence of the metal-nitride-oxide-silicon (MNOS) structure

MNOS capacitors were used to study the variation in memory window size as a function of temperature. Results of the investigation indicate that devices written with nonsaturating write/erase pulses exhibit a positive temperature coefficient due to the increase in conductivity of the nitride layer with increasing temperature. Devices written with saturating write/erase pulses exhibit a negative temperature coefficient as a result of fewer traps being available to trap charge as temperature is increased. Average values for the positive and negative temperature coefficients of all devices studied were 0.5 and ?0.15 V per 25°C rise in temperature, respectively.     

New scaling guidelines for MNOS nonvolatile memory devices

New phenomena in MNOS retention characteristics that originate from stored charge distribution are described and new scaling guidelines are indicated. The most significant phenomenon is that write-state retentivity is less dependent on the programmed depth, and is improved by reducing silicon nitride thickness. This behavior suggests that write-state charges are distributed rectangularly, while erase-state charges are distributed exponentially. The lower limit of the programming voltage is determined by write-state retentivity and not erase-state retentivity, and the write-state charge distribution depth determines the lower limit of silicon nitride thickness. The upper limit of the programming voltage is determined by erase-state retentivity after erase/write cycles. The scaling guidelines indicate that 16-Mb EEPROMs can be designed using MNOS memory devices     

SiO_2-Si_3N_4栅介质膜陷阱特性的高频C-V分析

采用高频 C-V特性测试技术 ,研究由热氧化生成的超薄 Si O2 膜和低压化学汽相淀积法制备的非均匀结构 Si3N4膜 ,两者组成的栅介质膜的陷阱特性 (包括陷阱密度、能量和空间分布深度等参数 )。结果表明 :在栅复合膜陷阱电荷非稳态释放模型下建立的高频 C-V理论及其分析方法 ,可以很好地表征实验曲线 ,并获取所需的存储陷阱分布参数     

Electrical and charge storage characteristics of the tantalum oxide-silicon dioxide device

The electrical characteristics of the tantalum oxide-silicon dioxide double-dielectric structure are described. The MTOS structure (metal-tantalum oxide-silicon dioxide-silicon) is similar to the MNOS double dielectric which is used as a nonvolatile memory element except tantalum oxide (Ta2O5) is used to replace the silicon nitride as the second dielectric. Capacitance voltage measurements show a negative QSSwith magnitudes smaller than those in compatable MNOS devices. Conduction characteristics of both anodic and thermally grown Ta2O5have been studied and both have been found to follow a Poole-Frenkel mechanism. The memory characteristics of the MTOS have been investigated and preliminary data are presented. Where MNOS data are available, the MTOS characteristics have been compared with those of the MNOS structure. It is shown that the threshold voltage of the MTOS device can be shifted using lower gate voltages than are needed for a comparable MNOS device. It thus appears that the MTOS device has some decided potential advantages over the MNOS structure as a nonvolatile memory element.     

Transient Charging and Discharging Behaviors of Border Traps in the Dual-Layer HfO2/SiO2 High- κ Gate Stack Observed by Using Low-Frequency Charge Pumping Method

Transient charging and discharging of border traps in the dual-layer HfO₂/SiO₂ high-kappa gate stack have been extensively studied by the low-frequency charge pumping method with various input pulse waveforms. It has been demonstrated that the exchange of charge carriers mainly occurs through the direct tunneling between the Si conduction band states and border traps in the HfO₂ high-kappa dielectric within the transient charging and discharging stages in one pulse cycle. Moreover, the transient charging and discharging behaviors could be observed in the time scale of 10^-8- 10^-4 s and well described by the charge trapping/detrapping model with dispersive capture/emission time constants used in static positive bias stress. Finally, the frequency and voltage dependencies of the border trap area density could also be transformed into the spatial and energetic distribution of border traps as a smoothed 3-D mesh profiling     

Properties of high-voltage stress generated traps in thin siliconoxide

It has previously been shown that trap generation inside thin oxides during high voltage stressing can be coupled to time-dependent-dielectric-breakdown distributions through the statistics linking wearout to breakdown. Since the stress-generated traps play a crucial role in the wearout/breakdown process, it is important to understand the properties of these traps. The properties of the traps in oxides with thicknesses between 2.5 nm and 22 nm have been studied, with emphasis on oxides in the 8.5-nm to 13-nm thickness range. The Coulombic scattering cross section of the traps responsible for the reduction in the tunneling current, an estimate of the spatial and energy distribution of the traps, and the charging/discharging properties of the traps have been measured. It will be shown that the measured properties of the high-voltage, stress-generated traps can be adequately described by the tunneling of electrons into and out of traps     

The light-sensitive MNOS memory transistor

In a simple memory application the threshold voltage VTof an MNOS transistor is switched by means of write and erase pulses of opposite polarities between two levels, representing logical ONEs and ZEROs. It is shown that by isolating the source and drain during the write pulse, the magnitude of the VTshift can be made dependent on the intensity of light on the MNOS device. By choosing the light intensity and the width of the write pulse properly, the device can be made to operate in either a digital or analog mode. The theory of this effect, applicable to both transistors and capacitors, is developed by generalizing the well-understood behavior of the MNOS memory device to include conduction in the silicon space-charge region. The operation of the device depends on the current-field relationships for the nitride, oxide, and silicon space-charge layers. It is shown how these three functions may be obtained from steady-state I-V measurements on the MNOS device. Good agreement is found between experimental and calculated charging curves for both transistors and capacitors.