High‐Performance Top‐Gated Organic Field‐Effect Transistor Memory using Electrets for Monolithic Printed Flexible NAND Flash Memory

High‐performance top‐gated organic field‐effect transistor (OFET) memory devices using electrets and their applications to flexible printed organic NAND flash are reported. The OFETs based on an inkjet‐printed p‐type polymer semiconductor with efficiently chargeable dielectric poly(2‐vinylnaphthalene) (PVN) and high‐k blocking gate dielectric poly(vinylidenefluoride‐trifluoroethylene) (P(VDF‐TrFE)) shows excellent non‐volatile memory characteristics. The superior memory characteristics originate mainly from reversible charge trapping and detrapping in the PVN electret layer efficiently in low‐k/high‐k bilayered dielectrics. A strategy is devised for the successful development of monolithically inkjet‐printed flexible organic NAND flash memory through the proper selection of the polymer electrets (PVN or PS), where PVN/‐ and PS/P(VDF‐TrFE) devices are used as non‐volatile memory cells and ground‐ and bit‐line select transistors, respectively. Electrical simulations reveal that the flexible printed organic NAND flash can be possible to program, read, and erase all memory cells in the memory array repeatedly without affecting the non‐selected memory cells.     

Nonvolatile Ferroelectric P(VDF‐TrFE) Memory Transistors Based on Inkjet‐Printed Organic Semiconductor

Nonvolatile ferroelectric poly(vinylidene fluoride‐co‐trifluoroethylene) memory based on an organic thin‐film transistor with inkjet‐printed dodecyl‐substituted thienylenevinylene‐thiophene copolymer (PC12TV12T) as the active layer is developed. The memory window is 4.5 V with a gate voltage sweep of ?12.5 V to 12.5 V. The field effect mobility, on/off ratio, and gate leakage current are 0.1 cm²/Vs, 10⁵, and 10^?10 A, respectively. Although the retention behaviors should be improved and optimized, the obtained characteristics are very promising for future flexible electronics.     

Printed,Flexible, Organic Nano‐Floating‐Gate Memory: Effects of Metal Nanoparticles and Blocking Dielectrics on Memory Characteristics

The effects of using a blocking dielectric layer and metal nanoparticles (NPs) as charge‐trapping sites on the characteristics of organic nano‐floating‐gate memory (NFGM) devices are investigated. High‐performance NFGM devices are fabricated using the n‐type polymer semiconductor, poly{[N,N′‐bis(2‐octyldodecyl)‐naphthalene‐1,4,5,8‐bis(dicarboximide)‐2,6‐diyl]‐alt‐5,5′‐(2,2′‐bithiophene)} (P(NDI2OD‐T2)), and various metal NPs. These NPs are embedded within bilayers of various polymer dielectrics (polystyrene (PS)/poly(4‐vinyl phenol) (PVP) and PS/poly(methyl methacrylate) (PMMA)). The P(NDI2OD‐T2) organic field‐effect transistor (OFET)‐based NFGM devices exhibit high electron mobilities (0.4–0.5 cm² V^?1 s^?1) and reliable non‐volatile memory characteristics, which include a wide memory window (≈52 V), a high on/off‐current ratio (I_on/I_off ≈ 10⁵), and a long extrapolated retention time (>10⁷ s), depending on the choice of the blocking dielectric (PVP or PMMA) and the metal (Au, Ag, Cu, or Al) NPs. The best memory characteristics are achieved in the ones fabricated using PMMA and Au or Ag NPs. The NFGM devices with PMMA and spatially well‐distributed Cu NPs show quasi‐permanent retention characteristics. An inkjet‐printed flexible P(NDI2OD‐T2) 256‐bit transistor memory array (16 × 16 transistors) with Au‐NPs on a polyethylene naphthalate substrate is also fabricated. These memory devices in array exhibit a high I_on/I_off (≈10^{4 ± 0.85}), wide memory window (≈43.5 V ± 8.3 V), and a high degree of reliability.     

Rational Design of Small Molecules to Implement Organic Quaternary Memory Devices

Organic small‐molecule‐based devices with multilevel electroresistive memory behaviors have attracted more and more attentions due to their super‐high data‐storage density. However, up to now, only ternary memory molecules have been reported, and ternary storage devices may not be compatible with the binary computing systems perfectly. In this work, a donor–acceptor structured molecule containing three electron acceptors is rationally designed and the field‐induced charge‐transfer processes can occur from the donors. Organic quaternary memory devices based on this molecule are successfully demonstrated for the first time. The switching threshold voltages of the memory device are –2.04, –2.73, and –3.96 V, and the current ratio of the “0,” “1,” “2,” and “3” states is 1:10^1.78:10^3.47:10^5.36, which indicate a low possibility of read and write errors. The results represent a further step in organic high‐density data‐storage devices and will inspire the further study in this field.     

Design of Multi‐time Programmable Memory for PMICs

In this paper, a multi‐time programmable (MTP) cell based on a 0.18 μm bipolar‐CMOS‐DMOS backbone process that can be written into by using dual pumping voltages — VPP (boosted voltage) and VNN (negative voltage) — is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p‐wells are used — one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n‐well is used for the 256‐bit MTP cell array. In addition, a three‐stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of and a user memory area of , is newly proposed in this paper.     

A Transparent Logic Circuit for RFID Tag in a‐IGZO TFT Technology

This paper proposes a transparent logic circuit for radio frequency identification (RFID) tags in amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistor (TFT) technology. The RFID logic circuit generates 16‐bit code programmed in read‐only memory. All circuits are implemented in a pseudo‐CMOS logic style using transparent a‐IGZO TFTs. The transmittance degradation due to the transparent RFID logic chip is 2.5% to 8% in a 300‐nm to 800‐nm wavelength. The RFID logic chip generates Manchester‐encoded 16‐bit data with a 3.2‐kHz clock frequency and consumes 170 μW at . It employs 222 transistors and occupies a chip area of 5.85 mm².     

Non‐Volatile Polymer Electroluminescence Programmable with Ferroelectric Field‐Induced Charge Injection Gate

Electroluminescence (EL) of organic and polymeric fluorescent materials programmable in the luminance is extremely useful as a non‐volatile EL memory with the great potential in the variety of emerging information storage applications for imaging and motion sensors. In this work, a novel non‐volatile EL memory in which arbitrarily chosen EL states are programmed and erased repetitively with long EL retention is demonstrated. The memory is based on utilizing the built‐in electric field arising from the remnant polarization of a ferroelectric polymer which in turn controls the carrier injection of an EL device. A device with vertically stacked components of a transparent bottom electrode/a ferroelectric polymer/a hole injection layer/a light emitting layer/a top electrode successfully emits light upon alternating current (AC) operation. Interestingly, the device exhibits two distinctive non‐volatile EL intensities at constant reading AC voltage, depending upon the programmed direct current (DC) voltage on the ferroelectric layer. DC programmed and AC read EL memories are also realized with different EL colors of red, green and blue. Furthermore, more than four distinguishable EL states are precisely addressed upon the programmed voltage input each of which shows excellent EL retention and multiple cycle endurance of more than 10⁵ s and 10² cycles, respectively.     

Printable Ferroelectric PVDF/PMMA Blend Films with Ultralow Roughness for Low Voltage Non‐Volatile Polymer Memory

Here, a facile route to fabricate thin ferroelectric poly(vinylidene fluoride) (PVDF)/poly(methylmethacrylate) (PMMA) blend films with very low surface roughness based on spin‐coating and subsequent melt‐quenching is described. Amorphous PMMA in a blend film effectively retards the rapid crystallization of PVDF upon quenching, giving rise to a thin and flat ferroelectric film with nanometer scale β‐type PVDF crystals. The still, flat interfaces of the blend film with metal electrode and/or an organic semi‐conducting channel layer enable fabrication of a highly reliable ferroelectric capacitor and transistor memory unit operating at voltages as low as 15 V. For instance, with a TIPS‐pentacene single crystal as an active semi‐conducting layer, a flexible ferroelectric field effect transistor shows a clockwise I–V hysteresis with a drain current bistability of 10³ and data retention time of more than 15 h at ±15 V gate voltage. Furthermore, the robust interfacial homogeneity of the ferroelectric film is highly beneficial for transfer printing in which arrays of metal/ferroelectric/metal micro‐capacitors are developed over a large area with well defined edge sharpness.     

High‐Transconductance Organic Thin‐Film Electrochemical Transistors for Driving Low‐Voltage Red‐Green‐Blue Active Matrix Organic Light‐Emitting Devices

Switching and control of efficient red, green, and blue active matrix organic light‐emitting devices (AMOLEDs) by printed organic thin‐film electrochemical transistors (OETs) are demonstrated. These all‐organic pixels are characterized by high luminance at low operating voltages and by extremely small transistor dimensions with respect to the OLED active area. A maximum brightness of ≈900 cd m^?2 is achieved at diode supply voltages near 4 V and pixel selector (gate) voltages below 1 V. The ratio of OLED to OET area is greater than 100:1 and the pixels may be switched at rates up to 100 Hz. Essential to this demonstration are the use of a high capacitance electrolyte as the gate dielectric layer in the OETs, which affords extremely large transistor transconductances, and novel graded emissive layer (G‐EML) OLED architectures that exhibit low turn‐on voltages and high luminescence efficiency. Collectively, these results suggest that printed OETs, combined with efficient, low voltage OLEDs, could be employed in the fabrication of flexible full‐color AMOLED displays.     

An Experimental 0.8 V 256‐kbit SRAM Macro with Boosted Cell Array Scheme

This work presents a low‐voltage static random access memory (SRAM) technique based on a dual‐boosted cell array. For each read/write cycle, the wordline and cell power node of selected SRAM cells are boosted into two different voltage levels. This technique enhances the read static noise margin to a sufficient level without an increase in cell size. It also improves the SRAM circuit speed due to an increase in the cell read‐out current. A 0.18 µm CMOS 256‐kbit SRAM macro is fabricated with the proposed technique, which demonstrates 0.8 V operation with 50 MHz while consuming 65 µW/MHz. It also demonstrates an 87% bit error rate reduction while operating with a 43% higher clock frequency compared with that of conventional SRAM.     

Designing Multi‐Level Resistance States in Graphene Ferroelectric Transistors

Conventional memory elements code information in the Boolean “0” and “1” form. Devices that exceed bistability in their resistance are useful as memory for future data storage due to their enhanced memory capacity, and are also a necessity for contemporary applications such as neuromorphic computing. Here, with the aid of an experimentally validated device model, design rules are outlined and more than two stable resistance states in a graphene ferroelectric field‐effect transistor are experimentally demonstrated. The design methodology can be extrapolated for on‐demand introduction of multiple resistance states in ferroelectric transistors for applications both in data storage and neuromorphic computing.     

2-V/100-ns 1T/1C nonvolatile ferroelectric memory architecture withbitline-driven read scheme and nonrelaxation reference cell

Nonvolatile memory embedded in microcontrollers has required a 100 ns access time at 2.0 V for mobile information terminals operating with a rechargeable battery. To achieve this, this paper proposes a new ferroelectric nonvolatile memory (FeRAM) architecture that utilizes a bitline-driven read scheme and a nonrelaxation reference cell for high-speed and low-voltage operations, respectively. Using this architecture, FeRAM with a one transistor and one capacitor per bit (1T/1C) cell can achieve 100 ns access time at 2.0 V     

Self‐Assembled Nanowires of Organic n‐Type Semiconductor for Nonvolatile Transistor Memory Devices

Organic nonvolatile transistor‐type memory (ONVM) devices are developed using self‐assembled nanowires of n‐type semiconductor, N,N′‐bis(2‐phenylethyl)‐perylene‐3,4:9,10‐tetracarboxylic diimide (BPE‐PTCDI). The effects of nanowire dimension and silane surface treatment on the memory characteristics are explored. The diameter of the nanowires is reduced by increasing the non‐solvent methanol composition, which led to the enhanced crystallinity and high field‐effect mobility. The BPE‐PTCDI nanowires with small diameters induce high electrical fields and result in a large memory window (the shifting of the threshold voltage, ΔV_th). The ΔV_th value of BPE‐PTCDI nanowire based ONVM device on the bare substrate can reach 51 V, which is significantly larger than that of thin film. The memory window is further enhanced to 78 V with the on/off ratio of 2.1 × 10⁴ and the long retention time (10⁴ s), using a hydrophobic surface (such as trichloro(phenyl)silane‐treated surface). The above results demonstrate that the n‐type semiconducting nanowires have potential applications in high performance non‐volatile transistor memory devices.     

High‐Performance Organic Transistor Memory Elements with Steep Flanks of Hysteresis

High‐performance organic transistor memory elements with donor‐polymer blends as buffer layers are presented. These organic memory transistors have steep flanks of hysteresis with an ON/OFF memory ratio of up to 2 × 10⁴, and a retention time in excess of 24 h. Inexpensive materials such as poly(methyl methacrylate), ferrocene and copper phthalocyanine are used for the device fabrication, providing a convenient approach of producing organic memory transistors at low cost and high efficiency.     

Effects of the Ionic Currents in Electrolyte‐gated Organic Field‐Effect Transistors

Polyelectrolytes are promising materials as gate dielectrics in organic field‐effect transistors (OFETs). Upon gate bias, their polarization induces an ionic charging current, which generates a large double layer capacitor (10–500 µF cm^?2) at the semiconductor/electrolyte interface. The resulting transistor operates at low voltages (<1 V) and its conducting channel is formed in ～50 µs. The effect of ionic currents on the performance of the OFETs is investigated by varying the relative humidity of the device ambience. Within defined humidity levels and potential values, the water electrolysis is negligible and the OFETs performances are optimum.     

Metal‐Organic Framework Nanofilm for Mechanically Flexible Information Storage Applications

Metal‐organic frameworks (MOFs), which are formed by association of metal cations or clusters of cations (“nodes”) with soft organic bridging ligands (“linkers”), are a fascinating class of flexible crystalline hybrid materials offering potential strategy for the construction of flexible electronics. In this study, a high‐quality MOF nanofilm, HKUST‐1, on flexible gold‐coated polyethylene terephthalate substrates is fabricated using liquid phase epitaxy approach. Uniform and reproducible resistive switching effect, which can be sustained under the strain of as high as 2.8%, and over the wide temperature range of –70 to +70 °C, is observed for the first time in the all solid‐state Au/HKUST‐1/Au/thin film structures. Through conductive atomic force microscopic and depth‐profiling X‐ray photoelectron spectroscopicanalysis, it is proposed that the electric field‐induced migration of the Cu_­²⁺ ions, which may lead to subsequent pyrolysis of the trimesic acid linkers and thus the formation of highly conducting filaments, could be the possible origin for the observed uniform resistance switching in HKUST‐1 nanofilms.     

High‐Speed,Low‐Voltage,and Environmentally Stable Operation of Electrochemically Gated Zinc Oxide Nanowire Field‐Effect Transistors

Single‐crystal, 1D nanostructures are well known for their high mobility electronic transport properties. Oxide‐nanowire field‐effect transistors (FETs) offer both high optical transparency and large mechanical conformability which are essential for flexible and transparent display applications. Whereas the “on‐currents” achieved with nanowire channel transistors are already sufficient to drive active matrix organic light emitting diode (AMOLED) displays; it is shown here that incorporation of electrochemical‐gating (EG) to nanowire electronics reduces the operation voltage to ≤2 V. This opens up new possibilities of realizing flexible, portable, transparent displays that are powered by thin film batteries. A composite solid polymer electrolyte (CSPE) is used to obtain all‐solid‐state FETs with outstanding performance; the field‐effect mobility, on/off current ratio, transconductance, and subthreshold slope of a typical ZnO single‐nanowire transistor are 62 cm²/Vs, 10⁷, 155 μS/μm and 115 mV/dec, respectively. Practical use of such electrochemically‐gated field‐effect transistor (EG FET) devices is supported by their long‐term stability in air. Moreover, due to the good conductivity (≈10^?2 S/cm) of the CSPE, sufficiently high switching speed of such EG FETs is attainable; a cut‐off frequency in excess of 100 kHz is measured for in‐plane FETs with large gate‐channel distance of >10 μm. Consequently, operation speeds above MHz can be envisaged for top‐gate transistor geometries with insulator thicknesses of a few hundreds of nanometers. The solid polymer electrolyte developed in this study has great potential in future device fabrication using all‐solution processed and high throughput techniques.     

Controllable Shifts in Threshold Voltage of Top‐Gate Polymer Field‐Effect Transistors for Applications in Organic Nano Floating Gate Memory

Organic field‐effect transistor (FET) memory is an emerging technology with the potential to realize light‐weight, low‐cost, flexible charge storage media. Here, solution‐processed poly[9,9‐dioctylfluorenyl‐2,7‐diyl]‐co‐(bithiophene)] (F8T2) nano floating gate memory (NFGM) with a top‐gate/bottom‐contact device configuration is reported. A reversible shift in the threshold voltage (V_Th) and reliable memory characteristics was achieved by the incorporation of thin Au nanoparticles (NPs) as charge storage sites for negative charges (electrons) at the interface between polystyrene and cross‐linked poly(4‐vinylphenol). The F8T2 NFGM showed relatively high field‐effect mobility (µ_FET) (0.02 cm² V^?1 s^?1) for an amorphous semiconducting polymer with a large memory window (ca. 30 V), a high on/off ratio (more than 10⁴) during writing and erasing with an operation voltage of 80 V of gate bias in a relatively short timescale (less than 1 s), and a retention time of a few hours. This top‐gated polymer NFGM could be used as an organic transistor memory element for organic flash memory.     

A Solar Transistor and Photoferroelectric Memory

This study presents a new self‐powered electronic transistor concept “the solar transistor.” The transistor effect is enabled by the functional integration of a ferroelectric‐oxide thin film and an organic bulk heterojunction. The organic heterojunction efficiently harvests photon energy and splits photogenerated excitons into free electron and holes, and the ferroelectric film acts as a switchable electron transport layer with tuneable conduction band offsets that depend on its polarization state. This results in the device photoconductivity modulation. All this (i.e., carrier extraction and poling) is achieved with only two sandwiched electrodes and therefore, with the role of the gating electrode being taken by light. The two‐terminal solar‐powered phototransistor (or solaristor) thus has the added advantages of a compact photodiode architecture in addition to the nonvolatile functionality of a ferroelectric memory that is written by voltage and nondestructively read by light.     

Room‐Temperature Printing of Organic Thin‐Film Transistors with π‐Junction Gold Nanoparticles

Printing semiconductor devices under ambient atmospheric conditions is a promising method for the large‐area, low‐cost fabrication of flexible electronic products. However, processes conducted at temperatures greater than 150 °C are typically used for printed electronics, which prevents the use of common flexible substrates because of the distortion caused by heat. The present report describes a method for the room‐temperature printing of electronics, which allows thin‐film electronic devices to be printed at room temperature without the application of heat. The development of π‐junction gold nanoparticles as the electrode material permits the room‐temperature deposition of a conductive metal layer. Room‐temperature patterning methods are also developed for the Au ink electrodes and an active organic semiconductor layer, which enables the fabrication of organic thin‐film transistors through room‐temperature printing. The transistor devices printed at room temperature exhibit average field‐effect mobilities of 7.9 and 2.5 cm² V^?1 s^?1 on plastic and paper substrates, respectively. These results suggest that this fabrication method is very promising as a core technology for low‐cost and high‐performance printed electronics.