Drain current thermal noise modeling for deep submicron n- and p-channel MOSFETs

The drain current thermal noise has been measured and modeled for the short-channel devices fabricated with a standard 0.18 μm CMOS technology. We have derived a physics-based drain current thermal noise model for short-channel MOSFETs, which takes into account the velocity saturation effect and the carrier heating effect in gradual channel region. As a result, it is found that the well-known Q_inv/L²––formula, previously derived for long-channel, remains valid for even short-channel. The model excellently explained the carefully measured drain thermal noise for the entire V_GS and V_DS bias regions, not only in the n-channel, but also in the p-channel MOSFETs. Large excess noise, which was reported earlier in some other groups, was not observed in both the n-channel and the p-channel devices.     

Analytical expressions for the static MOS transistor characteristics based on the gradual channel model

Analytical solutions are derived from Pao and Sah's double integral formula for the theoretical static I–V characteristics of MOS transistors including both the diffusion and drift currents based on the gradual channel model. Expressions for the entire saturation, non-saturation and low level current regions are given, while the specific importance of the theory is seen in the cross-over region between low level and normal operation. Reddi and Sah's formula for channel shrinkage is modified and included to account for the small drain conductance in the saturation region by taking the drain avalanche breakdown voltage into consideration. The solutions are compared with experimental data, and the effectiveness and the limit of the theory is quickly examined.     

Noise studies in internal field emission diodes

The breakdown process of a zener diode in reverse direction is governed by internal field emission at low voltage and by impact ionization at higher voltage. For breakdown voltage in the transition range between 3 and 6 V, both physical processes appear in combination. Measuring the I–V characteristic and the noise current fluctuations spectral density it is possible to show the zener current multiplication by the multiplication effect described by Tager. In addition the I–V characteristic can be written empirically I = Vⁿ.     

p-n heterojunctions

A classical kinetic emission model coupled with an assumed energy band diagram which includes the effects of a discontinuity in the electron affinity, effective mass, permittivity and the energy gap at the junction interface is used as the basis for an analysis of the static current-voltage characteristic of the abrupt p-n heterojunction. The derived characteristic is then used to determine regions of quasi-equilibrium within the depletion layer and to predict the position dependence of the quasi-Femri levels.

Two distinct modes of operation are predicted for the heterojunctions I–V characteristic: Metal-semiconductor type operation where the current is limited by the ability of the carriers to surmount the potential barrier at the junction interface and homojunction type operation where the current is limited by the ability of the carriers to diffuse away from the junction depletion region. The predicted extrapolated saturation current for the former type of operation, is in general, significantly less than that for the latter. The position dependence of the quasi-Fermi levels is also different for the two types of operation. For metal-semiconductor type operation a drop in the quasi-Fermi level across the depletion layer is expected, whereas for homodiode type operation there is a negligible variation of the quasi-Fermi level in this region.

The heterojunction I–V characteristic presented here, which differs significantly from previous models, agrees favourably with experimental data on Ge-GaAs heterojunctions reported in the literature and with others recently fabricated by the present authors.     

Two-dimensional analysis of ion-implanted, bipolar-compatible,long- and short-channel junction field-effect transistors

A two-dimensional analysis of ion-implanted, bipolar-compatible, long- and short-channel JFETs is presented. The two-dimensional device simulator PISCES is used to study the steady-state characteristics. The linear and saturation regions are analyzed, and insight about the transition region between them is obtained. Short-channel JFET behavior deviates considerably from the conventional theory developed based on the gradual channel approximation, because the x-direction electric field in the channel of the short-channel JFET is much stronger than that in the long-channel JFET. The study shows that the short-channel JFET has several properties that were not previously emphasized: (a) no pinch-off in saturation operation: (b) free-carrier drift velocity saturates in saturation operation: and (c) power-law I-V characteristics in the cutoff region. Details regarding the shape of the conducting channel, the electric field vectors, the current vectors, and the current-voltage characteristics are provided     

Electrical properties of W/Si interfaces with embedded Ge/Si islands

In this work, we investigated electrical and morphological properties of W/p-type Si Schottky diodes with intentional inhomogeneities introduced by macroscopic Ge-islands embedded beneath the interface. The Si-cap layer thickness (or the island-distance to the interface) was progressively reduced by successive chemical etching cycles. Electrical characterizations were achieved through reverse current–voltage (I–V) at room temperature and forward I–V measurements as a function of the temperature. In parallel, Rutherford backscattering spectroscopy analyses were performed to follow the Si-cap/Ge islands chemical thinning down with increasing the number of etching cycles. In addition, the comparison of topographical and electrical properties of the etched silicon-cap layer was carried out by conductive atomic force microscopy analyses with a nanometer-scale resolution. Our results indicate that the areas on the top of islands exhibit lower resistance than those which covered the wetting layer. This lateral variation of resistance at the surface of the semiconductor may correspond to Schottky barrier height inhomogeneities observed on broad area I–V characteristics of Schottky contacts.     

Procedure for determining diode parameters at very low forward voltage

A technique is proposed to extract the reverse saturation current parameter and ideality factor of semiconductor junctions from the low forward voltage region of the device’s characteristics. The method involves performing a mathematical operation on the experimental data that allows to calculate the parameters at values of forward current smaller than the reverse saturation current. The procedure was tested and its accuracy verified on synthetic I–V characteristics, with and without added simulated experimental error or noise. Good agreement is obtained between the parameters used in modeling and the extracted values. The procedure was also applied to experimentally measured I_B–V_BE characteristics of a real power BJT.     

Electrical properties of high permittivity ZrO2 gate dielectrics on strained-Si

Deposition and electrical properties of high dielectric constant (high-k) ultrathin ZrO₂ films on tensilely strained silicon (strained-Si) substrate are reported. ZrO₂ thin films have been deposited using a microwave plasma enhanced chemical vapor deposition technique at a low temperature (150 °C). Metal insulator semiconductor (MIS) structures are used for high frequency capacitance–voltage (C–V), current–voltage (I–V), and conductance–voltage (G–V) characterization. Using MIS capacitor structures, the reliability and the leakage current characteristics have been studied both at room and high temperature. Schottky conduction mechanism is found to dominate the current conduction at a high temperature. Observed good electrical and reliability properties suggest the suitability of deposited ZrO₂ thin films as an alternative as gate dielectrics. Compatibility of ZrO₂ as a gate dielectric on strained-Si is shown.     

A complete analytical model of GaN MESFET for microwave frequency applications

A simple physics-based analytical model for a non-self-aligned GaN MESFET suitable for microwave frequency applications is presented. The model includes the effect of parasitic source/drain resistances and the gate length modulation. The model is then extended to evaluate I–V and C–V characteristics, transconductance, cut-off frequency, transit time, RC time constant, optimum noise figure and maximum power density. The transconductance of about 21 mS/mm is obtained for GaN MESFET using the present theory in comparison to 23 mS/mm of the reported data. The cut-off frequency of more than 1 GHz, optimum noise figure of 6 dB and maximum output power density of more than 1 W/mm are predicted.     

Analytical modeling of the subthreshold current in short-channel MOSFET's

In this paper an analytical model for subthreshold current for both long-channel and short-channel MOSFET's is presented. The analytical electrostatic potential derived from the explicit solution of a two-dimensional Poisson's equation in the depletion region under the gate for uniform doping is used. The case for nonuniform doping can easily be incorporated and will be published later. The results are compared to a numerical solution obtained by using MINIMOS, for similar device structures. An analytical expression for the channel current is obtained as a function of drain, gate, substrate voltages, and device parameters for devices in the subthreshold region. The short-channel current equation reduces to the classical long-channel equation as the channel length increases.     

Temperature-dependence of steady-state characteristics of SCR-type ESD protection circuits

Experimental analysis of the temperature-dependent I–V characteristics of various SCR (Silicon-Controlled Rectifier) electrostatic discharges (ESD) protection circuits have been carried out. These circuits include diode-chain-triggering SCR (DCTSCR), low-voltage zener diode trigger SCR (ZDSCR), low-voltage trigger SCR (LVTSCR) and gate-coupled low-voltage trigger SCR (GCSCR) circuits. The ZDSCR uses the zener breakdown mechanism of a reverse-biased p⁺–n⁺ diode as a trigger mechanism, the DCTSCR uses the current flowing through forward-biased diode chain as a trigger mechanism, the LVTSCR uses the grounded-gate MOSFET breakdown current as the trigger mechanism and the steady-state I–V characteristics of GCSCR also uses the avalanche breakdown as a triggering mechanism. The trigger voltage can decrease or increase with increasing temperature depending upon the triggering mechanism used in the circuit, however the holding voltages of these SCRs decrease with increasing temperature.     

Breakdown degradation associated with elementary screw dislocations in 4H-SiC pn junction rectifiers

It is well-known that SiC wafer quality deficiencies are delaying the realization of outstandingly superior 4H-SiC power electronics. While efforts to date have centered on eradicating micropipes (i.e., hollow core super-screw dislocations with Burgers vector>2c), 4H-SiC wafers and epilayers also contain elementary screw dislocations (i.e., Burgers vector=1c with no hollow core) in densities on the order of thousands per cm², nearly 100-fold micropipe densities. This paper describes an initial study into the impact of elementary screw dislocations on the reverse-bias current–voltage (I–V) characteristics of 4H-SiC p⁺n diodes. First, synchrotron white beam X-ray topography (SWBXT) was employed to map the exact locations of elementary screw dislocations within small-area 4H-SiC p⁺n mesa diodes. Then the high-field reverse leakage and breakdown properties of these diodes were subsequently characterized on a probing station outfitted with a dark box and video camera. Most devices without screw dislocations exhibited excellent characteristics, with no detectable leakage current prior to breakdown, a sharp breakdown I–V knee, and no visible concentration of breakdown current. In contrast, devices that contained at least one elementary screw dislocation exhibited 5–35% reduction in breakdown voltage, a softer breakdown I–V knee, and visible microplasmas in which highly localized breakdown current was concentrated. The locations of observed breakdown microplasmas corresponded exactly to the locations of elementary screw dislocations identified by SWBXT mapping. While not as detrimental to SiC device performance as micropipes, the undesirable breakdown characteristics of elementary screw dislocations could nevertheless adversely affect the performance and reliability of 4H-SiC power devices.     

A circuit-compatible analytical device model for ballistic nanowire transistors

Silicon nanowire transistors (SNWTs) have attracted broad attention as a promising device structure for future integrated circuits. Silicon nanowires with a diameter as small as 2 nm and having high carrier mobility have been achieved. Consequently, to develop TCAD tools for SNWT design and to model SNWT for circuit-level simulations have become increasingly important. This paper presents a circuit-compatible closed-form analytical model for ballistic SNWTs. Both the current–voltage (I–V) and capacitance–voltage (C–V) characteristics are modeled in terms of device parameters and terminal voltages. Such a model can be efficiently used in a conventional circuit simulator like SPICE to facilitate transistor-level simulation of large-scale nanowire or mixed nanowire-CMOS circuits and systems.     

Analytical model for I-V characteristics ofion-implanted MESFET's with heavily doped channel

A theoretical model for the I-V characteristics of ion-implanted metal-semiconductor field-effect transistors (MESFETs) has been developed. A formula for effective drift saturation velocity for electrons and a Gaussian approximation for the inverse of reduced distances in the channel have erased the process of formulation. Theoretical formulas for early saturation of drain current and transconductance obtained in the framework of the Lehovec-Zuleeg procedure are quite simple and accurate. When calculated results from the present model are compared with available experimental results, an encouraging correspondence between the two is observed. A study of the appropriateness of the velocity overshoot and the softening of pinch-off voltage indicates that both of these phenomena are real in short-channel MESFETs and need to be carefully accounted for in a realistic model. The model is equally applicable also to ion-implanted JFETs     

Performances of novel Pd/Sn and Pd/Sn/Au ohmic metallizations to n-GaAs

Performance of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations to n-GaAs have been investigated. Metallizations were deposited using a resistance heating evaporator and annealings were performed utilizing a conventional graphite strip annealer (cGSA). Metallization samples were characterized using scanning tunneling microscopy (STM), secondary ion mass spectrometry (SIMS) and current–voltage (I–V) measurements. Contact resistivities, ρ_c, of the metallizations were measured utilizing conventional transmission line model (cTLM) method. Novel Pd/Sn and Pd/Sn/Au Ohmic contacts exhibit better thermal stability compared to non-alloyed Pd/Ge metallization. In order to investigate the effectiveness of novel Pd/Sn and Pd/Sn/Au Ohmic metallizations in device applications, gallium arsenide metal-semiconductor field-effect transistors (GaAs MESFETs) have been fabricated. MESFETs fabricated with Pd/Sn/Au Ohmic contacts show a extrinsic transconductance, g_me, of more than 133 mS/mm for a gate length, L_G, of 2 μm.     

Forward Body Biasing as a Bulk-Si CMOS Technology Scaling Strategy

Forward body biasing is a promising approach for realizing optimum threshold-voltage (V _TH) scaling in the era when gate dielectric thickness can no longer be scaled down. This is confirmed experimentally and by simulation of a 10-nm gate length MOSFET. Because forward body bias (VF) decreases the depletion width (X _DEP) in the channel region, it reduces V _TH rolloff significantly. MOSFET performance is maximized under forward body bias with steep retrograde channel doping, and such channel doping profiles are required to accomplish good short-channel behavior (small X _DEP ) at low V _TH notwithstanding body bias; therefore, the combination of forward body biasing with steep retrograde channel doping profile can extend the scaling limit of conventional bulk-Si CMOS technology to 10-nm gate length MOSFET. Considering forward biased p-n junction current, parasitic bipolar transistor, and CMOS latch-up phenomena, the upper limit for |VF| should be set at 0.6-0.7 V, which is sufficient to realize significant advantages of forward body biasing.     

Analysis of I–V measurements on PtSi-Si Schottky structures in a wide temperature range

I–V Measurements on PtSi-Si Schottky structures in a wide temperature range from 90 to 350 K were carried out. The contributions of thermionic-emission current and various other current-transport mechanisms were assumed when evaluating the Schottky barrier height Φ₀. Thus the generation-recombination, tunneling and leak currents caused by inhomogeneities and defects at the metal-semiconductor interface were taken into account.

Taking the above-mentioned mechanisms and their temperature dependence into consideration in the Schottky diode model, an outstanding agreement between theory and experiment was achieved in a wide temperature range.

Excluding the secondary current-transport mechanisms from the total current, a more exact value of the thermionic-emission saturation current I_te and thus a more accurate value ofΦ_b was reached.

The barrier height Φ_b and the modified Richardson constant A^** were calculated from the plot of thermionic-emission saturation current I_te as a function of temperature too. The proposed method of finding Φ_b is independent of the exact values of the metal-semiconductor contact area A and of the modified Richardson constant A^**. This fact can be used for determination of Φ_b in new Schottky structures based on multicomponent semiconductor materials.

Using the experimentally evaluated value A^** = 1.796 × 10⁶ Am⁻²K⁻² for the barrier height determination from I–V characteristics the value of Φ_b = 0.881 ± 0.002 eV was reached independent of temperature.

The more exact value of barrier height Φ_b is a relevant input parameter for Schottky diode computer-aided modeling and simulation, which provided a closer correlation between the experimental and theoretical characteristics.     

Analytical modelling for the current-voltage characteristics of undoped or lightly-doped symmetric double-gate MOSFETs

An analytical drain current model for undoped (or lightly-doped) symmetric double-gate (DG) MOSFETs is presented. This model is based on the subthreshold leakage current in weak inversion due to diffusion of carriers from source to drain and an analytical expression for the drain current in strong inversion of long-channel DG MOSFETs, both including the short-channel effects. In the saturation region, the series resistance, the channel length modulation, the surface-roughness scattering and the saturation velocity effects were also considered. The proposed model has been validated by comparing the transfer and output characteristics with simulation and experimental results.     

Effect of Channel Width Shortening on the Stability of a-Si:H/nc-Si:H Bilayer Thin-Film Transistors

The static bias-stress-induced degradation of hydrogenated amorphous/nanocrystalline silicon bilayer bottom-gate thin-film transistors is investigated by monitoring the turn-on voltage (V _on) and on-state current (I _on) in the linear region of operation. Devices of constant channel length 10 mum and channel width varying from 3 to 400 mum are compared. The experimental results demonstrate that the device degradation is channel-width dependent. In wide channel devices, substantial degradation of V _on is observed, attributed to electron injection into the gate dielectric, followed by I _on reduction due to carrier scattering by the stress-induced gate insulator trapped charge. With shrinking the channel width down to 3 mum, the device stability is substantially improved due to the possible reduction of the electron thermal velocity during stress or due to the gate insulator quality uniformity over small dimensions.     

Analysis of current conduction in short-channel accumulation-modeSOI PMOS devices

This paper reports a compact analytical current conduction model for short-channel accumulation-mode SOI PMOS devices. Based on the study, the current conduction mechanism in a short-channel accumulation-mode SOI PMOS device is different from that in a long-channel one. As verified by the experimental data, the compact analytical model considering channel length modulation and prepinchoff velocity saturation gives an accurate prediction of the drain current characteristics