Algorithm and Implementation of Parallel Multiplication in a Mixed Number System

This paper presents a high-speed multiplication algorithm for the mixed number system of the ordinarybinary number and the symmetric redundant binary number.It is implemented with the multivalned logictheory,and 3-valued and 2-valued circuits are used.The 3-valued circuit proposed in this paper is anemitter-coupled logic circuit with high speed,simplicity and powerful functions.A 3-valued ECL thresholdgate can simultaneously produce six types of one-variable operations.The array multiplier,designed withthe algorithm and the circuits,is fast and simple,and is suitable for building LSI.It can be used in a high-speed computer just as an ordinary binary multiplier.     

LORES-2: A Logic Reorganization System

LORES-2 is a logic reorganization system which greatly contributes to the effective automation of logic design. LORES-2 uses a macro-expansion technique to help designers transform printed-circuit assembly logic composed of SSI and MSI circuits into master-slice LSI logic circuits. The number of gates of the most reorganized LSI circuit falls within ± 20 percent of the number of gates of the original circuit. When ROMS and/or PLAs are not-allowed on the target LSI circuit, those elements are converted into optimized, multilevel random logic using logic minimization, factoring and macro-expansion techniques.     

Integrating an Electron-Beam System into VLSI Fault Diagnosis

Using design data, the system can prepare a logic-state map for the device under test. The map draws top-layer connections in different colors according to their expected logic states so the map may be compared to the DUT image observed by the electron-beam tester. The system has successfully tested a 75K-transistor VLSI device.     

Advanced CMOS speech synthesizers

Employing an updated C²MOS (clocked CMOS) technique, two types of speech synthesizer LSI circuits, based on the Parcor (partial correlation) and the ADM (adoptive delta modulation) methods, and recording watch system, are introduced and described.

These LSI circuits and system have several functions

• • The new Parcor LSI circuit has the circuits needed by the Parcor synthesis algorithm. It has a 64 kbit speech data ROM, output low pass filter and preamplifier. Using only this LSI circuit, 30 s to 60 s of speech can be synthesized.

• • The new ADM LSI circuit has encoding and decoding circuits, a 64 kbit speech data ROM and RAM control circuit. The record and synthesis system can be easily constructed with this LSI circuit and RAM.

• • The recording watch system consists of the watch LSI circuit with the ADM system and the analogue LSI circuit.

In the Parcor system, various high quality and low data-rate speech outputs are obtainable. The ADM system is applied for recording and synthesizing. By applying these systems to meet market needs, it is possible to achieve good cost performance in a simple system.     

A Microprocessors-Controlled DIC Test System*

The objective of this paper is to bring forth the benefits that can be realized by using LSI microprocessors in test equipment and instrument applications. We will attempt to do this by describing the Qualifier* 901, which is a low-cost bench top digital integrated circuit tester controlled by an LSI microprocessor. First, we identify the scope of low-cost testers and describe the general principles of operation of such testers using fixed logic control. Then we describe the Qualifier 901, and finally, we point out the advantages gained by the usage of the intelligence of the microprocessor in Qualifier 901 versus fixed logic controlled testers.     

CAI in digital logic design,debugging, and programming

This paper describes design techniques for generative computer-assisted instruction (CAI) systems. These are systems which are capable of generating problems for students and deriving and monitoring the solutions to these problems. The difficulty of the problem, the pace of instruction, and the depth of monitoring are all tailored to the individual student. Parts of the solution algorithms can also be used to analyze an incorrect student response and determine the exact nature of the student's error in order to supply him with meaningful remedial comments.A generative CAI system which teaches logic design and machine-language programming will be discussed. This CAI system covers the material in an introductory course in digital systems aimed at electrical engineering juniors. It does not replace classroom lectures or the textbook, but instead serves to provide practice and instruction in applying this material to solve problems.In addition, a companion system to teach laboratory principles has been designed. This system teaches a student how to construct a combinational or sequential logic circuit using standard integrated circuits. The student's logic circuit is automatically interfaced to the computer and tested; the computer then aids the student in debugging his circuit. In addition to teaching the student how to use integrated circuits to realize a paper design, the system also teaches the student good debugging techniques.     

随机信号环形高速采集电路

为了对随机到来的信号进行不丢失的高速采集,提出了一种基于CPLD的随机信号环形高速采集卡的设计与实现;通过采用三套采集电路形成一个环形结构,可以对随机到来的信号进行不遗漏的高速采集,而且在采集过程中利用阈值的方法鉴别出有用信号,并舍弃了大量的冗余无用数据,从而只将有用数据以DMA的方式传于主机,便于进行信号的处理;电路设计简洁可靠,并给出了主要的逻辑电路示意图与主要部件说明;该系统已经应用在采集α核素的工程实践中.     

Emitter-couple logic circuit design based on the threshold-arithmetic algebraic system

Based on the threshold-arithmetic algebraic system which has been proposed for current-mode circuit design,we propose a systematic methodology for emitter-couple logic(ECL)circuit design.Compared to the traditional methodologies and the theory of differential current switches,the proposed methodology uses the HE map and the characteristics of the internal current signals of ECL circuits to determine the external voltage signals.The operations of the HE map are direct and simple,and the current signals are easy to add or subtract,which make this methodology more flexible,direct,and effective,and make it possible to design arbitrary binary and multi-valued logic functions.Two example circuits are designed and simulated by HSPICE using 0.18μm TSMC technology.Simulation results confirm the validity of the proposed methodology.     

Symbolic pattern manipulation of Karnaugh-Veitch maps for pneumatic circuits

Pneumatics continue to play a vital role in low-cost automation. The designing of pneumatic control circuits has to date been a slow manual process. This paper describes the computational symbolic manipulation of the Karnaugh-Veitch (KV) map which is the heart of the prototype expert system called PNEUMAES. The symbolic manipulation of a KV map is governed by two sets of generic rules for signal flow plotting and for logic equation minimisation applicable for complex pneumatic circuits. As the complexity of the circuit increases, the symbolic manipulation of a KV map leads to the combinatorial explosion problem. Because of this problem, PNEUMAES can only automatically generate pure pneumatic circuit design equations which will yield minimised circuit configuration for up to four cylinders with auxiliary control valves. A case study is included and issues and problems relating to the implementation of the KV map are discussed. Symbolic and sub-symbolic learning approaches are suggested as a means by which the search space of the symbolic patterns of the KV map can be pruned.     

智能CAD工具

本文介绍我们开发的运用人工智能技术的CAD工具:演绎CAD数据库;具有推理能力并内含演绎版图数据库的版图语言;能从晶体管网络中识别基本逻辑单元和从基本逻辑单元网络中识别复杂逻辑电路的电路识别工具。     

Research in Design Automation for VLSI Layout

Since Japanese R&D efforts began in the late 1960s, advances in LSI circuit design automation have made possible the design of custom logic VLSI circuits with up to 10,000 gates. Automatic placement and routing programs have become essential DA tools in both master-slice LSI circuit design, and the custom design of VLSI circuits with up to 100,000 gates. Algorithms for VLSI DA systems include automatic floor planning, automatic cell placement, and automatic routing. Hierarchical design is an efficient approach to the layour of huge numbers of transistors; a VLSI circuit with 74,000 transistors and 17,000 gates was designed using such an approach. The layout design effort required less than 10 man-months, and the chip was fabricated with no error on the first design.     

Gaelic logic simulator: an interactive CAD tool

The use of digital logic simulation in the design of integrated circuits has long been established. In this role, however, simulation in general has remained a non-interactive CAD tool. In an attempt to alter this situation a simulator has been developed which will permit the designer to interact with the circuit, thus making simulation an even more effective design tool particularly in its use for debugging incorrect designs.     

Scaling up genetic circuit design for cellular computing: advances and prospects

Synthetic biology aims to engineer and redesign biological systems for useful real-world applications in biomanufacturing, biosensing and biotherapy following a typical design-build-test cycle. Inspired from computer science and electronics, synthetic gene circuits have been designed to exhibit control over the flow of information in biological systems. Two types are Boolean logic inspired TRUE or FALSE digital logic and graded analog computation. Key principles for gene circuit engineering include modularity, orthogonality, predictability and reliability. Initial circuits in the field were small and hampered by a lack of modular and orthogonal components, however in recent years the library of available parts has increased vastly. New tools for high throughput DNA assembly and characterization have been developed enabling rapid prototyping, systematic in situ characterization, as well as automated design and assembly of circuits. Recently implemented computing paradigms in circuit memory and distributed computing using cell consortia will also be discussed. Finally, we will examine existing challenges in building predictable large-scale circuits including modularity, context dependency and metabolic burden as well as tools and methods used to resolve them. These new trends and techniques have the potential to accelerate design of larger gene circuits and result in an increase in our basic understanding of circuit and host behaviour.     

Personal computers in automation systems

Historically, computer control of processes and experiments has been the domain of large scale industry and research organizations. For small quantity or ‘one off’ systems, the availability of the microprocessor and associated LSI and MSI logic components have lowered the cost of such automation and process control systems by perhaps an order of magnitude. In the case of large quantities, the cost reduction figures are much more dramatic, particularly where the system is realized on a specialized customized VLSI chip. Microprocessor control systems can be realized in a number of ways. This paper explores the conditions and environment in which a personal computer, such as the Commodore PET, can offer lower costs and simpler software and hardware development than systems designed from micromodules i.e. sets of printed circuit boards each performing a specific function.     

水听器全频测试仪的设计

介绍了一种基于LPC2194的水听器全频测试仪,用来在施工前确定检波器的好坏。全频测试仪采用绝对测量法对水听器各项性能参数进行测试,即在相同条件下测量未知待测水听器和声压计的响应,计算出待测水听器的最终响应值。测试仪硬件主要由信号源模块、功率放大模块、数据采集模块和串口通信模块等几部分组成,利用A/D转换芯片AD7705和AD7899进行数据采集,并采用串口与PC机通信,通过上位机进行显示;下位机软件采用Keil对主控制器进行编程,上位机采用VC6.0。利用本测试仪对被测水听器作了多次重复性试验,将测得参数与标准参数进行对比,结果表明,本系统稳定可靠,操作方便灵活,测试结果准确。     

Computer Aided Design for Large-Scale Integrated Circuits

The complexity of integrated circuits has increased steadily over the past several years from circuits consisting of simple gates through Medium Scale Integration (MSI) and Large Scale Integration (LSI). Fabrication techniques for LSI have evolved from well-established integrated circuit technology. Because of the large physical size and the large number of components on the individual silicon die, production techniques have been substantially improved in order to maintain reasonable yields. However, the most significant effects of LSI on the semiconductor manufacturer are in the areas of design and testing; techniques used in the past for simpler integrated circuits are inadequate for LSI.     

Development of a user friendly gate-level logic simulator

A design of a digital logic simulator is developed and presented. BASIC on an IBM Personal Computer using interactive graphics tools is employed to make the simulator easy to use. The simulator can handle gate level logic circuits, and can be used for both logic verification and fault testing.

Efficient and correct simulation in a user-friendly environment was the main design objective. Concepts of interactive computer graphics are extensively applied to enable the drawing of the circuit. Menu structures have been used to simplify the interaction of user and computer. The foundation has been laid for a simulator that uses pattern recognition for circuit data acquisition.

The simulator permits the verification of the logic of a circuit without fault. The design also includes provision for inserting delays and simulating to detect hazards. Test sequences to detect the presence of faults in the circuit can be generated using deductive simulation. The design provides a reliable basis for further research into logic simulation.     

Hitest: A Knowledge-Based Test Generation System

Efforts to develop computer-based automatic test generation for digital circuits have been generally unsuccessful, except in the case of combinational circuitry. Current ATPG methods for sequential circuits often require a considerable amount of computer time and generate unstructured test waveforms of limited value. Experienced human test programmers, on the other hand, appear to have little difficulty in generating high-quality tests for complex sequential circuits when they have a good understanding of how the circuit operates. This article considers the causes of failure in automatic test generation algorithms and describes a new system called Hitest. This system lets the computer use human understanding of circuit operations to generate more effective tests.     

Defect-Tolerant Mapping of CMOL Circuit Targeting Delay Optimization

In view of the significant number of defective nanodevices in the Cmos/nanowire/MOLecular hybrid (CMOL)circuit,defect-tolerant mapping is an essential step to achieve correct logic operations in defective CMOL circuits.However,less effort has been made to improve circuit delay by defect-tolerant strategies.In this paper,the factors affecting the delay of mapped circuits are analyzed,and the path-tree based defect-tolerant mapping method for the delay optimization is proposed.From the logic-domain,the terminology of the path tree is presented,and the logic circuit is first partitioned into multiple path trees.Then,the mapping areas in the physic-domain are pre-planned for (near) critical path trees.During the mapping process,the specific mapping modes and an updating strategy are formulated to map the path trees:inputs are mapped based on input sorting;(near) critical path trees are mapped with priority,while the others are mapped in a hierarchical way.Finally,an improved tabu search algorithm is employed to verify the validity of the proposed defect-tolerant mapping method.Experimental evaluations on the ISCAS benchmarks show that the proposed method can reduce circuit delay by 15.22％.     

基于单片机的WQ-5型弯曲梁应变测量系统设计

为了增加WQ-5型弯曲梁应变量测量实验仪的数据通信功能,利用PC机进行数据处理、实时曲线显示等,介绍了用基于单片机系统的设计方法对实验仪进行了重新设计。在设计时,继承现有仪器的模拟电路部分,同时增加了微机及数字通信的电路;以及汇编语言下位机程序、PC机上位机程序等系统设计的程序等,对传统仪器的改进具有一定的指导意义。