Current hogging logic (CHL)-a new bipolar logic for LSI

Logic functions of current hogging logic (CHL) are established by switching the lateral injection current in intermediate collector p-n-p structures. High functional density is achieved, since NOR, NAND, and complex gates can readily be realized and all logic elements can be placed within a common isolation region. CHL is fabricated with a standard buried collector process, and hence is compatible with linear bipolar circuits and other bipolar logic families. Current levels are employed as the logical variables, and the transfer characteristics of an AND-NOR gate are discussed. CHL offers high static and dynamic noise immunity. The paper demonstrates a static frequency divider as an example of an CHL circuit.     

LSI processing technology for planar GaAs integrated circuits

A planar GaAs integrated circuit (IC) fabrication technology capable of LSI complexity has been developed. The circuit and fabrication approaches were chosen to satisfy LSI requirements for high yield, high density, and low power. This technology utilizes Schottky-diode FET logic (SDFL) incorporating both high-speed switching diodes and 1-µ m GaAs MESFET's. Circuits are fabricated directly on semi-insulating GaAs using multiple localized implantations. Rapid progress in the development of this technology has already led to the successful demonstration of high-speed (tau_{d} sim 100ps) low-power (∼500 µW/gate) GaAs MSI (∼60-100 gates) circuits. Extension of the current MSI technology to the LSI/VLSI domain will depend critically on device yield which will be dictated by the GaAs material properties and by the fabrication processes used. The purpose of this paper is to describe a GaAs IC process technology which combines advanced planar device and multilevel interconnect structures with several LSI compatible processes including multiple localized ion implantations, reduction photolithography, plasma etching, reactive ion etching, and ion milling.     

An advanced PSA technology for high-speed bipolar LSI

An advanced method for polysilicon self-aligned (PSA) bipolar LSI technology has realized a miniaturized transistor for high performance. By introducing the overlapping structure for double polysilicon electrodes, the emitter area is reduced to 1 µm × 3 µm and the base junction is reduced to 0.3 µm. The CML integrated circuit composed of this transistor has achieved a minimum propagation delay time of 0.29 ns/gate with power dissipation of 1.48 mW/gate. Compared to the conventional PSA method, this technology promises to fabricate higher speed and higher density LSI's.     

Supply-current analysis (scan) as a screen for bipolar integrated circuits

A novel technique utilising the analysis of supply-current variations is proposed as a screen for digital integrated circuits. The application of the method to a simple m.s.i. circuit is used to demonstrate its capability of indicating the presence of flaws at internal circuit nodes.     

A very simple Al-gate technology for high performance LSI circuits

This paper deals with a very simple technology for fabrication of high performance n-channel Al-gate enhancement load digital integrated circuits. Using a nine-stage ring oscillator with triode load, an intrinsic time delay of 1·9 ns and a speed-power product of 1·45 pJ were measured. A two kbit ROM memory with 50 ns access time was designed and fabricated with this technology.     

Advanced bipolar circuits

Advances in high-speed, low-power bipolar circuits aimed at achieving superior power-delay performance and load-driving capability over conventional ECL and NTL circuits are reviewed. The basic principles underlying power/speed improvement including charge-buffering, DC/AC-coupled active pull-down schemes, and complementary push-pull approaches, are examined. The utilization and combination of these basic principles to form various high-speed, low-power circuits in both n-p-n-only and complementary circuit configurations and the design tradeoffs of these circuits are discussed     

Quality assurance system and reliability testing of LSI circuits

The development of LSI circuits as well as their quality and reliability assurance in the current production require, due to the specified high quality levels, a precisely defined Quality Assurance System. Such a System was presented in the first two Sections.For the predictions of field failure rate generally the time-temperature acceleration in accordance with the Arrhenius model has to be applied. Field reliability at lower operating temperatures has to be determined from the results and defectives of sampling life-tests at elevated temperatures. Obviously for LSI circuits the time-temperature acceleration depends very strongly on different failure mechanisms involved. For this reason an efficient and correct failure rate prediction can only be performed, if the failure mechanisms in the defective chips are exactly known and classified.     

Lifetime prediction for submicrometer LSI circuits and programmable logic: An overview

An overview is given of the experience gained in lifetime prediction for submicrometer LSI circuits and programmable logic, as reported by leading manufacturers including Siemens AG, Analog Devices, Atmel, Xilinx, Altera, QuickLogic, and Actel. The main conclusions are as follows: (i) The Arrhenius equation remains a major tool for describing the temperature dependence of circuit lifetime. (ii) The lifetime of LSI circuits continues to display a bimodal pattern. (iii) Bias-temperature stressing constitutes a generally useful technique for identifying failure mechanisms. (iv) The chi-squared distribution should be employed in predicting useful-life failure rate.Translated from Mikroelektronika, Vol. 34, No. 2, 2005, pp. 138–158.Original Russian Text Copyright © 2005 by Strogonov.     

A bipolar 2500-gate subnanosecond masterslice LSI

A bipolar 2500-gate subnanosecond masterslice LSI has been developed for use in computer mainframes. A walled-emitter structure has been realized by using double boron ion implantation with an n-type epitaxial layer to obtain high performance and high packing density. A new cell composed of a pair of adjacent gates provides high utilization of input transistors. A gate delay of 0.58 ns with power dissipation of 0.54 mW/gate has been achieved. The masterslice has been applied to an 18-bit memory data register circuit consisting of 1983 internal logic gates and has been mounted on a new 224-pin plug-in package.     

A pair of bipolar memory LSI chips for mainframe computers

A pair of bipolar memory chips has been developed. One is an LSI consisting of a 3072 bit RAM and 470 logic gates on the same chip. It has a typical address access time of 6.7 ns and a typical power dissipation of 3.9 W. It is used in the translation lookaside buffer and the buffer address array of Hitachi's M200H computer to speed up dynamic address translation and buffer storage control. The other chip is a standard 1K bit RAM with a typical address access time of 5.5 ns and a typical power dissipation of 800 mW. It is used in the buffer storage. The primary fabrication process employs oxide isolation with double layer metallization, with minimum line width-plus-spacing of 8 /spl mu/m.     

Analog statistical simulation for bipolar integrated circuits

Analog circuit design automation continues to gain attention in methods to improve, automate, and reduce design cycle time. These techniques address the needs of improving design for functionality, however the importance of design for manufacturability continues to be neglected. The emphasis of design for manufacturability is shown when the quality of a part is measured. Parts designed with no consideration for process/design variations result in poor yield. To address the need in analog design for manufacturability, new techniques that involve the areas of physical process, geometric modeling of electrical parameters, and statistical simulation techniques using independent process parameters, yield and Cpk analysis are defined and implemented. Results from these techniques provide the analog designer with the ability to simulate and predict circuit quality with process and design variations. To support the defined techniques, a design tool called MSTAT (Motorola Statistical Analysis Tool) is developed. Results of these techniques accompanied with MSTAT output is presented.     

Fault coverage requirement in production testing of LSI circuits

A technique is described for evaluating the effectiveness of production tests for large scale integrated (LSI) circuit chips. It is based on a model for the distribution of faults on a chip. The model requires two parameters, the average number (n/SUB 0/) of faults on a faulty chip and the yield (y) of good chips. It is assumed that the yield either is known or can be calculated from the available formulas. The other parameter, n/SUB 0/, is determined from an experimental procedure. Once the model is fully characterized, it allows calculation of the field reject rate as a function of the fault coverage. The technique implicitly takes into account such variables as fault simulator characteristics, the feature size, and the manufacturing environment. An actual LSI circuit is used as an example.     

A Si bipolar 1.4-GHz time space switch LSI for B-ISDN

A 155-MB/s 32×32 Si bipolar switch LSI designed for wide application in the broadband ISDN was implemented. The operating speed is 1.4 GHz using an A-BSA Si bipolar process. Its throughput is 5.0 Gb/s by handling four 1.4-GHz interfaces, each of which supports an eight-channel multiplexed data stream. To realize a highly integrated high-speed bipolar LSI, power consumption and chip area should be reduced. Two technologies were developed for the LSI: (1) an active pull-down circuit with an embedded bias circuit in each gate, and (2) a modified standard cell with overlapped cell-channel structure. Using these technologies, total power consumption and chip area were reduced to 60% and 70%, respectively, of what is expected when conventional emitter-coupled logic (ECL) technologies and standard cell structures are used. The LSI evaluation results show that the developed LSI has sufficient performance to realize a large-scale B-ISDN switching system     

Silicon bipolar integrated circuits for multigigabit-per-secondlightwave communications

Recent results on silicon bipolar ICs for lightwave communications in the multigigabits-per second (Gb/s) range are presented. These state-of-the-art results demonstrate the inherent speed difference between the different types of basic circuits. With the fastest ones (multiplexing and demultiplexing), bit rates above 10 Gb/s are achieved, even with production technologies. The technologies, as well as circuit and design principles to achieve such high operating speeds, are discussed, and some experimental examples are described in more detail. Moreover, the high-speed potential of present 1-μm silicon bipolar technologies is demonstrated by the simulation of carefully optimized communication ICs. With most of the basic circuits, bit rates above 10 Gb/s, and in some cases above 20 Gb/s, are achievable     

Heterostructure bipolar transistors and integrated circuits

Two new epitaxial technologies have emerged in recent years (molecular beam epitaxy (MBE) and metal-organic chemical vapor deposition (MOCVD)), which offer the promise of making highly advanced heterostructures routinely available. While many kinds of devices will benefit, the principal and first beneficiary will be bipolar transistors. The underlying central principle is the use of energy gap variations beside electric fields to control the forces acting on electrons and holes, separately and independently of each other. The resulting greater design freedom permits a re-optimization of doping levels and geometries, leading to higher speed devices. Microwave transistors with maximum oscillation frequencies above 100 GHz and digital switching transistors with switching times below 10 ps should become available. An inverted transistor strucure with a smaller collectors on top and a larger emitter on the bottom becomes possible, with speed advantages over the common "emitter-up" design. Double-heterostructure (DH) transistors with both wide-gap emitters and collectors offer additional advantages. They exhibit better performance under saturated operation. Their emitters and collectors may be interchanged by simply changing biasing conditions, greatly simplifying the architecture of bipolar IC's. Examples of heterostructure implementations of I²L and ECL are discussed. The present overwhelming dominance of the compound semiconductor device field by FET's is likely to come to an end, with bipolar devices assuming an at least equal role, and very likely a leading one.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

The use of threshold functions and Boolean-controlled network elements for macromodeling of LSI circuits

The concept of threshold functions and Boolean-controlled network elements is introduced. It allows for digital macromodeling and mixing logic and timing simulation with transient analysis at device or macromodel level. A simulator for four-phase MOS LSI (4PHASE) showing a two orders of magnitude improvement in CPU time and a digital-analog simulator (DIANA) capable of mixing logic, timing, and analog simulation are shown as examples. DIANA typically allows for the simulation of an analog circuit complexity up to 50 nodes together with 400 digital macromodels on a 32K word minicomputer.     

Inclusion-exclusion principle in the design of a BIST unit for LSI and VLSI circuits

The basic inclusion-exclusion algorithm is considered in the context of binary vectors. A connection is revealed between the algorithm and the generation of convolution codes for BIST applications in LSI and VLSI circuits. A strategy for changing from combinatorial identities to theoretical probabilities (with infinitely many vectors) is used to extend some classical relations of discrete mathematics and to investigate the results from the viewpoint of signature synthesis. It is shown that the inclusion-exclusion approach is not an identification algorithm in its own right, as it essentially gives the sum of i empirical probabilities.     

Method for online nondestructive hardness assurance for CMOS LSI circuits realized in SOS technology

The radiation performance of digital CMOS circuits realized in SOS technology is investigated in relation to the radiation-induced charge at the silicon-sapphire interface. A nondestructive hardness-assurance method based on radiation annealing is proposed, and reasons are given why this approach should be feasible. The limits of applicability of the method are assessed.     

Arsenic-doped polycrystalline silicon film for bipolar integrated circuits

The advantages of the use of As-doped polycrystalline silicon film over that of As-doped glass film in the fabrication of high speed bipolar integrated circuits have been shown. The films have been used for doping buried layer and emitter. Deposition conditions optimized for the As-doped polycrystalline silicon film allows low junction leakage to be attained with low pipe density. During the course of the work the mechanism for the formation of pipes have been suggested.