Study on discharge stability of cost-effective driving method based on V/sub t/ close-curve analysis in AC plasma-display panel

A new cost-effective driving method that can drive plasma-display panel cells without applying any driving waveform to the common electrode is proposed based on a V/sub t/ close-curve analysis. In this driving method, it is very important to prevent a misfiring discharge due to the inversion of the polarity of the wall charges accumulated between the scan and address electrodes. The measured V/sub t/ close-curve showed that a misfiring discharge caused by the polarity inversion phenomenon of the wall charges on the scan and address electrode could be prevented by minimizing the potential difference between the scan and address electrodes by applying a positive auxiliary pulse to the address electrode, especially while applying the positive sustain pulse during a sustain period. As a result, the proposed cost-effective driving method can reduce the driving cost by about 20% through eliminating the common driving board and successfully display various image patterns, such as the white, red, green, and blue patterns, on a 42-in plasma television without any misfiring discharge.     

Reset-while-address (RWA) driving scheme for high-speed address in AC plasma display panel with high Xe content

A new reset while-address (RWA) driving scheme for a single scan of an XGA grade (1024 /spl times/ 768) ac-plasma display panel (PDP) is proposed to improve the address discharge characteristics with a high Xe gas mixture (15%). To solve the conventional address problem of the gradual decrease in priming particles during an address period, the falling ramp waveform in the reset period is separated into two parts; the first part is applied at the beginning of the reset period and provides the priming particles during the first half of the address period, while the second part is applied in the middle of the address period to provide an additional supply of priming particles during the second half of the address period. As a result of adopting the proposed RWA driving scheme, address discharges were successfully produced within a 1.0-/spl mu/s pulsewidth due to the presence of priming particles throughout the address period.     

高对比度等离子体显示器驱动方法

提出了一种提高等离子体显示器(PDP)显示对比度的驱动方法，该方法以传统的寻址与显示分离(ADS)方式为基础，一场只需要一次全屏放电。在各子场的复位期，采用分别加在X和Y电极上的斜坡电压脉冲擦除壁电荷，斜坡电压脉冲末端的电位与X，Y电极在寻址期中被扫描到时所加电压一致，不仅提高了寻址的准确性，且有利于增大寻址电压动态范围并降低寻址电压。     

Improvement of address discharge characteristics using asymmetric variable-width scan waveform in ac plasma display panel

A new asymmetric variable-width scan waveform is proposed to improve the characteristics of an address discharge, including a reduced address time and increased dynamic voltage margin, based on the formative and statistical time lags of an address discharge in an ac-plasma display panel (ac-PDP). The new asymmetric variable-width scan waveform has a progressively increasing scan pulsewidth that is wider than the address pulsewidth, thereby enabling stable wall charge accumulation under short address pulsewidth conditions. When adopting this new scan waveform, the address pulsewidth was reduced from 3.0 to 1.4 /spl mu/s and the address voltage lowered from 65 to 55 V without any misfiring problem at an address pulsewidth of 1.4 /spl mu/s.     

New Reset Waveform for a Large-Sustain-Gap Structure in an Alternating Current Plasma Display Panel

A new reset waveform for a large-sustain-gap structure in an ac plasma display panel is proposed. In the driving of a large-sustain-gap structure with a conventional ramp reset waveform, we cannot avoid the condition of an address electrode being a cathode, which causes lots of trouble in stabilizing the reset discharge. To resolve these problems, a square pulse instead of the conventional rising-ramp pulse is used. In order to stabilize the strong discharge in which the address electrode becomes a cathode, a priming discharge between the address (anode) and scan (cathode) electrodes is made prior to making a strong discharge between the address (cathode) and scan (anode) electrodes. With this scheme, a minimum address voltage of 60 V when the sustain gaps are 250 and 350 $muhbox{m}$, respectively, is obtained. However, the contrast ratio using the square reset pulse is lower than that using the conventional ramp pulse. To improve the contrast ratio, the reset waveforms in each subfield are replaced by selective erase waveforms except for the first subfield. In the case of nonselective reset waveform, the background luminance is 19.4 $ hbox{cd/m}^{2}$, whereas the background luminance of 2.4 $ hbox{cd/m}^{2}$ is obtained with selective reset waveform.      

New reset waveform for the contrast ratio improvement of AC-PDP

We propose a new reset waveform for the improvement of contrast ratio. A square pulse is applied to the address electrode while the reset pulse ramps and before the discharge between the sustain electrodes occurs. The square pulse induces a discharge between the address electrode and the X electrode, and the induced wall charge between the sustain electrodes is opposite to the applied ramping voltage between the sustain electrodes. Thus, the next discharge between the sustain electrodes becomes weaker. The weaker discharge during the reset period lowers background luminance and improves contrast ratio. The experimental results show that the contrast ratio can be improved by 35/spl sim/58% using this method compared with the conventional ramp reset method.     

Driving Characteristics of a High-Efficacy AC PDP With an Auxiliary Electrode

A new driving waveform was proposed in order to stabilize the driving characteristics of a high-efficacy AC plasma-display panel (PDP) with a coplanar gap of 200 mum and an auxiliary electrode. To stabilize the reset and address discharge, an erase pulse was applied to the auxiliary electrode instead of the sustain electrode after the sustain period. The write pulse was applied to the scan electrode, and a reset discharge was induced between the scan and auxiliary electrodes. As a result, the minimum address voltage could be reduced to a level similar to that achieved with a conventional ac PDP with a coplanar gap of 80 mum. Furthermore, the address-discharge time lag of the ac PDP with a coplanar gap of 200 mum was improved to a level that is comparable with that of the ac PDP with a coplanar gap of 80 mum.     

Characteristics of an address discharge time lag in terms of a wall voltage in an AC PDP

The characteristics of an address discharge have been investigated in terms of a wall voltage, which plays an important role in achieving a high-speed address discharge in an ac plasma display panel. The wall-voltage conditions generated in a reset period are a considerable factor to reduce the address-discharge time lag. Based on the experimental results, the reset driving scheme in which an address bias voltage is applied to the address electrode in a reset period is proposed to enhance the characteristics of an address-discharge time lag.     

A GaAs 1K static RAM using tungsten silicide gate self-aligned technology

This paper reports a GaAs 1K static RAM, fabricated using tungsten silicide gate self-aligned technology with full ion implantation. With 2-/spl mu/m gate length, an address access time of 3.6 ns and a minimum write-enable pulse width of 1.6 ns were achieved with a power dissipation of 68 mW. The access time compares favorably to those of currently reported high-speed Si bipolar memories, and the greatly decreased power dissipation is better by one order of magnitude. An address access time of 0.88 ns can be achieved by shortening the gate length to 1 /spl mu/m and adopting a 2-/spl mu/m design rule in the layout.     

New Address-While-Display Driving Method for High Contrast Ratio and Wide Operation Margin PDP Using Short Ramp Reset (SRR) and Short Pulse Erase (SPE) Schemes

We propose a new address-while-display (AWD) driving method for a plasma display panel to obtain a high contrast ratio and a wide operation margin, which is composed of a short ramp reset (SRR) period, a short erase period, a sustain period, and an address period as the basic units. The SRR pulse and the short pulse erase period make it possible to obtain a wide operating voltage margin and minimize the background luminance by redistributing the wall charges in a short initialization time between the address and the scan electrode. As a result, a high darkroom contrast ratio of 10 000 : 1 could be achieved with a wide operating voltage margin of 40 V for a stable address.      

New addressing method using overlapping scan time of AC-PDP

A new plasma display panel driving method was proposed to reduce the address period. The scan time of the address method using overlapping scan time overlaps with the next scan time during the formative lag time of the discharge. Thus, without reducing the address pulsewidth and the scan pulsewidth, the driving method can reduce the address period. We could overlap the scan time of about 100 /spl sim/300 ns. However, the driving method has a narrow address voltage margin compared with a conventional method. In order to improve the address voltage margin of the driving method, the scan direction is set to the opposite direction compared with the conventional direction. As shown in experimental results, the address voltage margin of the new driving method is increased by 7/spl sim/10 V when the opposite scan direction is used.     

The addressing characteristics of an alternating current plasmadisplay panel adopting a ramping reset pulse

The characteristics of the address discharge of an alternating current plasma display panel (ac PDP) adopting a ramping reset pulse were studied using two-dimensional (2-D) numerical simulation. We investigated the principal parameters of the reset pulse for a successful address discharge. In this paper, we suggest a new parameter, the terminal voltage of the ramping reset pulse, and its effects on the minimum address voltage and current flow characteristics during the address discharge. The minimum addressing voltage decreased with increase in the ramping-down time and with increase in the terminal voltage of the ramping reset pulse, which were explained with the wall charge characteristics obtained by a 2-D simulation and confirmed through an ac PDP experiment     

A new driving waveform to improve dark room contrast ratio in acplasma display panel

A high dark room contrast ratio is necessary for realizing good image quality in ac plasma display panels (PDP). However, the conventional PDPs have low dark room contrast ratio because the background light mainly results from the reset discharges between the address, scan, and sustain electrodes in every subfield. In this study, a new driving method [improved waveform of contrast ratio (ICR)] is suggested to enhance the dark room contrast ratio. The principle of ICR is that the facing discharges during the reset period occur between the scan and address electrodes instead of surface discharges by applying almost the same voltage waveform as the scan voltage to the sustain electrode after the conventional first subfield. Moreover, the reset discharge occurs only for the cells that experienced sustain discharge in the preceding subfield after the first subfield. The dark room contrast ratio of ICR is improved more than 7× as compared to the conventional method     

A 3.5-ns, 2-W, 20-mm/SUP 2/, 16-kbit ECL bipolar RAM

A 3.5-ns emitter-coupled logic (ECL) 16-kbit bipolar RAM with a power dissipation of 2 W, a cell size of 495 /spl mu/m/SUP 2/, and a chip size of 20 mm/SUP 2/ has been developed. High performance is achieved using a high-speed Schottky barrier diode decoder with a pull-up circuit and a double-stage discharge circuit for a word-line driver. Small cell size is obtained using ultra-thin Ta/SUB 2/O/SUB 5/ film capacitors and 1-/spl mu/m U-groove isolation technology. An access time of 3.5 ns in this 16-kb bipolar RAM is equivalent to an effective access time of 2.5 ns at the system level, due to an on-chip address buffer and latch.     

荫罩式等离子体复合放电驱动波形的研究

提出了一种适合三电极荫罩式PDP结构的新型高效复合放电驱动波形.采用二维流体模型研究了三电极荫罩式PDP结构复合放电驱动波形的放电过程,分析了空间电位、壁电荷及带电粒子分布的演变情况.讨论了复合放电驱动波形维持期寻址电极电压对放电特性的影响,计算了维持期真空紫外辐射功耗、放电效率的变化趋势以及电子平均浓度随时间的变化关系,并与传统表面放电驱动波形比较.结果表明复合放电驱动波形在响应频率、放电强度和放电效率等方面均优于传统表面放电驱动波形.     

交流等离子体显示器驱动方法的改进

对三电极表面放电交流等离子体显示器驱动方法的物理过程进行了详细的分析，根据其放电原理对常规的寻址与显示分离驱动方法的准备期波形进行了改进。实验结果表明，改进的驱动方法不仅简化了驱动电路，降低了寻址电极驱动芯片的耐压值和功耗，而且增强了显示图像的对比度，降低了驱动电路的成本。     

A 0.85-ns 1-kbit ECL RAM

A 1-kb ECL RAM with an address access time of 0.85 ns is described. This excellent performance is achieved by combining super self-aligned technology (SST) with 1-/spl mu/m design rules and high-speed circuit design. SST provides a narrow emitter stripe width of 0.5 /spl mu/m and a high cutoff frequency of 12.4 GHz at V/SUB CE/=3 V. A two-level metallization process is used. The minimum metallization pitches are 3 /spl mu/m in the first layer and 6 /spl mu/m in the second one. The chip size is 2.5/spl times/2.5 mm/SUP 2/ and the power dissipation is 950 mW. This RAM is promising for use in super computers and/or high-speed digital systems.     

A high performance 1 Mbit EPROM

A high-performance 1-Mb EPROM has been developed by utilizing advanced 1.2-/spl mu/m minimum design rule technology. The device technology used is n-channel E/D MOS. The memory cell size is 5.5/spl times/7.5 /spl mu/m and the die size is 9.4/spl times/7.2 mm. The word organization is changeable between 64K words/spl times/16 bits and 128K words/spl times/8 bits. The active power dissipation is 500 mW and the standby power dissipation is 150 mW. The access time is typically 200 ns. The programming voltage is 12-14 V and the programming pulse width is typically 1 ms/word. In order to realize such a high-density, high-speed, low power 1-Mb EPROM, 1.2-/spl mu/m minimum patterning process technology, a high-speed sense amplifier, and a high-speed decoder are used.     

A high-speed 128-kb MRAM core for future universal memory applications

A 128-kb magnetic random access memory (MRAM) test chip has been fabricated utilizing, for the first time, a 0.18-/spl mu/m V/sub DD/=1.8 V logic process technology with Cu metallization. The presented design uses a 1.4-/spl mu/m/sup 2/ one-transistor/one-magnetic tunnel junction (1T1MTJ) cell and features a symmetrical high-speed sensing architecture using complementary reference cells and configurable load devices. Extrapolations from test chip measurements and circuit assessments predict a 5-ns random array read access time and random write operations with <5-ns write pulse width.     

Effects of pre-reset conditions on reset discharge from ramp reset waveforms in AC plasma display panel

The basic characteristics of reset discharges related to a wall voltage and a priming effect were investigated under a conventional ramp driving scheme. The reset discharges could be minimized by controlling the wall voltage which is determined by pre-reset conditions. Accordingly, the current study presents a simple pre-reset condition for minimizing the reset discharge. Essentially, it is not only to reduce the duration of reset discharges but also to reduce the intensity of light emissions when the wall voltage polarity is opposite to the external voltage polarity.