用三维蒙特卡罗模拟栅-源/漏不对准对体硅FinFET器件性能的影响

We investigate the influence of gate-source/drain(G-S/D) misalignment on the performance of bulk fin field effect transistors(FinFETs) through the three-dimensional(3D) full band Monte Carlo simulator.Several scattering mechanisms,such as acoustic and optical phonon scattering,ionized impurity scattering,impact ionization scattering and surface roughness scattering are considered in our simulator.The influence of G-S/D overlap and underlap on the on-states performance and carrier transport of bulk FinFETs are mainly discussed in our work.Our results show that the on-states currents increase with the increment of G-D/S overlap length and the positions of a potential barrier and average electron energy maximum vary with the G-D/S overlap length.The carrier transport phenomena in bulk FinFETs are due to the effect of scattering and the electric field in the overlap/underlap regime.     

Spurious source/drain underlap of large junction area NFET's

When a 0.35-μm CMOS technology was introduced into manufacturing, a small fraction of the tested devices exhibited symptoms of source/drain underlap, despite the fact that all other monitors were well within the design control limits. Additional measurements showed variable overlap on various monitor structures on the same chip. The specific formulation of an HF wet clean was shown to be responsible for the underlapped devices, and the problem was eliminated by altering this process step. High-volume manufacturing data are presented to show the problem and the solution     

Nanoscale ultrathin body PMOSFETs with raised selective germaniumsource/drain

Nanoscale ultrathin body (UTB) p-channel MOSFETs with body thickness down to 4 nm and raised source and drain (S/D) using selectively deposited Ge are demonstrated for the first time. Devices with gate length down to 30 nm show high drive current, low off current, and excellent short-channel behavior. Mobility enhancement and threshold-voltage shift due to the quantum confinement of inversion charge in the ultrathin body are investigated     

Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

Nanoscale double-gate (DG) FinFETs with undoped fin bodies are shown to have threshold voltages (Vt) that can be adjusted for independent I _ON and I _OFF control by allowing limited source/drain (S/D) dopants in the channel. S/D engineering of the lateral doping profile in the extension is proposed as a viable means for effecting such channel doping [as well as gate-S/D (G-S/D) underlap] and, thus, adjusting Vt for optimal I _ON/I _OFF in low-power and high-performance applications of nanoscale-FinFET CMOS. Physics-based device simulations, numerical simulations, and measured current-voltage characteristics are used to demonstrate and support the proposed Vt design approach.     

Impact of strain and source/drain engineering on the low frequency noise behaviour in n-channel tri-gate FinFETs

The impact of strain-engineering on the low frequency of n-channel tri-gate FinFETs fabricated on silicon on insulator (SOI) substrates noise is reported. The work is first focused on the study of nFinFETs with a standard structure and with strain-engineered channel structures, using either global or local straining techniques, or a combination of both. A carrier number fluctuation dominant flicker noise has been observed for all devices. Whereas no clear correlation between the applied strain techniques and the 1/f noise level has been found, an unusual noise spectral density was observed for the devices with selective epitaxial grown (SEG) source and drain regions. This unusual noise behaviour has been investigated for different fin widths (0.15 μm up to 3 μm) and different temperature conditions (150 K up to 300 K). An empirical model is proposed in order to explain this unusual noise behaviour. Moreover, two Lorentzians attributed to defects in the depletion region of the silicon fin were observed, and energy level and cross-section of these defects were estimated.     

Effect of underlap and gate length on device performance of an AlInN/GaN underlap MOSFET

We investigate the performance of an 18 nm gate length AlInN/GaN heterostructure underlap double gate MOSFET, using 2D Sentaurus TCAD simulation. The device uses lattice-matched wideband Al_0.83In_0.17N and narrowband GaN layers, along with high-k Al₂O₃ as the gate dielectric. The device has an ultrathin body and is designed according to the ITRS specifications. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to the large two-dimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive device simulation of the major device performance metrics such as drain induced barrier lowering (DIBL), subthreshold slope (SS), delay, threshold voltage (V_t), I_on/I_off ratio and energy delay product have been done for a wide range of gate and underlap lengths. Encouraging results for delay, I_on, DIBL and energy delay product are obtained. The results indicate that there is a need to optimize the I_off and SS values for specific logic design. The proposed AlInN/GaN heterostructure underlap DG MOSFET shows excellent promise as one of the candidates to substitute currently used MOSFETs for future high speed applications.     

Impact of High-k Gate Dielectrics on the Device and Circuit Performance of Nanoscale FinFETs

The impact of high-k gate dielectrics on device short-channel and circuit performance of fin field-effect transistors is studied over a wide range of dielectric permittivities k. It is observed that there is a decrease in the parasitic outer fringe capacitance C_of in addition to an increase in the internal fringe capacitance C_if with high-k dielectrics, which degrades the short-channel effects significantly. It is shown that fin width scaling is the most suitable approach to recover the degradation in the device performance due to high-k integration. Furthermore, from the circuit perspective, for the 32-nm technology generation, the presence of an optimum k for a given target subthreshold leakage current has been identified by various possible approaches such as fin width scaling, fin-doping adjustment, and gate work function engineering     

Analysis of the gate-source/drain capacitance behavior of a narrow-channel FD SOI NMOS device considering the 3-D fringing capacitances using 3-D simulation

This paper reports an analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device considering the three-dimensional (3-D) fringing capacitances. Based on the 3-D simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 /spl mu/m, the inner-sidewall-oxide fringing capacitance (C/sub FIS/), due to the fringing electric field at the edge of the mesa-isolated structure of the FD SOI NMOS device biased at V/sub G/=0.3 V and V/sub D/=1 V, is the second largest contributor to the gate-source capacitance (C/sub GS/). Thus, when using nanometer CMOS devices with a channel width smaller than 0.1 /spl mu/m, C/sub FIS/ cannot be overlooked for modeling gate-source/drain capacitance (C/sub GS//C/sub GD/).     

Independent double-gate FinFETs with asymmetric gate stacks

Flexibly controllable threshold voltage (V_th) asymmetric gate oxide thickness (T_ox) independent double-gate (DG) FinFETs (4T-FinFETs) have been demonstrated. Thin drive-gate oxide (HfO₂ or SiON or SiO₂) and slightly thick V_th-control-gate oxide (thick SiO₂+drive-gate oxide) have been successfully incorporated into the 4T-FinFETs by utilizing the ion-bombardment-enhanced etching of SiO₂. It was experimentally confirmed that, all the asymmetric T_ox 4T-FinFETs give the significantly improved subthreshold slope and thus gain higher on-current as compared to the symmetric one. Simulation results showed that the asymmetric T_ox 4T-FinFETs are advantageous even in 20-nm-gate-length region.     

Analysis of Harmonic distortion in asymmetric underlap DG-MOSFET with high-k spacer

In analog and RF circuit applications Harmonic distortion (HD) is an important reliability issue that arises due to non-linear performance of devices. In this paper, the asymmetric underlap double gate MOSFET (AUDG-MOSFET) is analyzed for the HD with high-k spacers. In this analysis the devices are compared for their primary distortion components designated by the second order distortion (HD2), the third order distortion (HD3) and the total harmonic distortion (THD). The distortion characteristics of the device are studied as a function of the gate voltage (V_gs) and the transconductance generation factor (g_m/I_d) considering the influence of drain current (I_d) and the transconductance (g_m). A significant improvement on the HD of the device by using high-k spacers is inferred, thereby ascertaining better reliability for RF applications. In addition to this, the distortion in the output characteristics of Cascode and differential amplifier circuits designed with AUDG-MOSFET device is also analyzed in detail.     

Simulation of the novel high-frequency FET with an opposed gate-source structure

The opposed gate-source transistor (OGST) is a novel high-frequency field-effect device with a symmetry plane and a distributed interaction mode. The operation principles of the OGST have been analyzed using numerical two-dimensional time-dependent device-simulation techniques. The coupled particle balance, momentum balance, and Poisson equations subject to general boundary conditions are solved with finite-difference methods. Device characteristics are simulated using both quasi-static and "ballistic" high-field transport models. The unique symmetry property of the OGST leads to a new pinchoff and current collection mechanism at the source contact. A 60-GHz design has been analyzed in detail. The simulations predict the lower and upper limits of 290 and 709 mS/mm for the transconductance, and 72 and 214 GHz for the cutoff frequency, respectively, for the intrinsic OGST.     

Schottky barrier thin-film transistor (SBTFT) with silicidedsource/drain and field-induced drain extension

A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from low on-off current ratio, the new device exhibits high on/off current ratio up to 10⁶ for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS process integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications     

Short-channel metal-gate TFTs with modified Schottky-barrier source/drain

A thin active layer, a fully silicided source/drain (S/D), a modified Schottky-barrier, a high dielectric constant (high-/spl kappa/) gate dielectric, and a metal gate are integrated to realize high-performance thin-film transistors (TFTs). Devices with 0.1-/spl mu/m gate length were fabricated successfully. Low threshold voltage, low subthreshold swing, high transconductance, low S/D resistance, high on/off current ratio, and negligible threshold voltage rolloff are demonstrated. It is thus suggested for the first time that the short-channel modified Schottky-barrier TFT is a solution to carrier out three-dimension integrated circuits and system-on-panel.     

Raised source/drain MOSFET with dual sidewall spacers

A raised source/drain (S/D) MOSFET with sidewall spacers formed both before and after selective epitaxial silicon deposition in S/D regions is discussed. The second spacer overlies any faceted regions of the epitaxial silicon near the gate edge and has advantages for MOSFETs with implant-doped or in-situ doped epitaxial silicon regions. In particular, the spacer can prevent S/D dopants from being implanted through any thinner faceted regions near the gate edge, which would otherwise result in a deeper than desired junction depth in the silicon substrate. Additionally, the spacer can prevent source-to-substrate salicide shorts through the thinner faceted regions     

Series resistance of devices with submicrometer source/drain areas

The source-drain series resistances of devices contacted by a local interconnection technology utilizing polysilicon strapped with selective CVD tungsten were measured and compared to predictions obtained using a theoretical model. Asymmetrical devices in which the local interconnections were intentionally misaligned to the gate were fabricated to study the effects of misalignment on device characteristics. Experiments indicate that the technology is quite forgiving to the misalignment between the gate and the local interconnection     

Cylindrical surrounding-gate MOSFETs with electrically induced source/drain extension

A novel cylindrical surrounding gate MOSFETs with electrically induced source/drain extension is proposed and demonstrated by numerical simulation for the first time. In the new device, a constant voltage is applied to the side-gate to form inversion layers acting as the extremely shallow virtual source/drain. Using three-dimensional device simulator, we have investigated the device performance focusing on the threshold voltage roll-off, the drain induced barrier lowering, the subthreshold swing, electrical field and carrier temperature. Based on our simulation results, we demonstrate that the proposed structure exhibits better suppression of short channel effects and hot carrier effects when compared to the conventional cylindrical surrounding gate MOSFETs.     

Performance characteristics of <Emphasis Type="Italic">p</Emphasis>-channel FinFETs with varied Si-fin extension lengths for source and drain contacts

The length of Source/Drain (S/D) extension (L_SDE) of nano-node p-channel FinFETs (pFinFETs) on SOI wafer influencing the device performance is exposed, especially in drive current and gate/S/D leakage. In observation, the longer L_SDEpFinFET provides a larger series resistance and degrades the drive current (I_DS), but the isolation capability between the S/D contacts and the gate electrode is increased. The shorter L_SDE plus the shorter channel length demonstrates a higher trans-conductance (G _m ) contributing to a higher drive current. Moreover, the subthreshold swing (S.S.) at longer channel length and longer L_SDE represents a higher value indicating the higher amount of the interface states which possibly deteriorate the channel mobility causing the lower drive current.     

Reduction of source/drain series resistance and its impact ondevice performance for PMOS transistors with raised Si1-xGex source/drain

P-channel MOS transistors with raised Si_1-xGe_x and Si source/drain (S/D) structure selectively grown by ultra high vacuum chemical vapor deposition (UHVCVD) were fabricated for the first time. The impact of Si_1-xGe_x and Si epitaxial S/D layers on S/D series resistance and drain current of p-channel transistors were studied. Our results show that devices with the raised Si_1-xGe_x S/D layer display only half the value of the specific contact resistivity and S/D series resistance (R_SD), compared with those with a Si raised S/D layer. The improvement is even more dramatic when comparing with conventional devices without any raised S/D layer, i.e., R_SD of devices with Si_1-xGe_x raised S/D is only about one fourth that of conventional devices. Moreover, the raised SiGe S/D structure produces a 29% improvement in transconductance (g_m) at an effective channel length of 0.16 μm. These performance improvements, together with several inherent advantages, such as self-aligned selective epitaxial growth (SEG) and the resultant T-shaped gate structure, make the new device with raised Si_1-xGe_x S/D structure very attractive for future sub-0.1 μm p-channel MOS transistors     

Nanoscale ultra-thin-body silicon-on-insulator P-MOSFET with aSiGe/Si heterostructure channel

We report the concept and demonstration of a nanoscale ultra-thin-body silicon on-insulator (SOI) P-channel MOSFET with a Si _1-xGe_x/Si heterostructure channel. First, a novel lateral solid-phase epitaxy process is employed to form an ultra-thin-body that suppresses the short-channel effects. Negligible threshold voltage roll-off is observed down to a channel length of 50 nm. Second, a selective silicon implant that breaks up the interfacial oxide is shown to facilitate unilateral crystallization to form a single crystalline channel. Third, the incorporation of SiGe in the channel resulted in a 70% enhancement in the drive current     

Source/Drain Extension Region Engineering in FinFETs for Low-Voltage Analog Applications

In this letter, we propose a novel design methodology for engineering source/drain extension (SDE) regions to simultaneously improve intrinsic dc gain (A_VO) and cutoff frequency (f_T ) of 25-nm gate-length FinFETs operated at low drain-current (I _ds=10 muA/mum). SDE region optimization in 25-nm FinFETs results in exceptionally high values of A_VO (~45 dB) and f _T (~70 GHz), which is nearly 2.5 times greater when compared to devices designed with abrupt SDE regions. The influence of spacer width, lateral source/drain doping gradient, and the spacer-to-gradient ratio on key analog figures of merit is examined in detail. This letter provides new opportunities for realizing future low-voltage/low-power analog design with nanoscale SDE-engineered FinFETs