Ab-initio simulation of self-interstitial in germanium

Density functional theory (DFT) with local density approximation including on-site Coulomb interaction (LDA+U) has been used to calculate the formation energy of the neutral and charged self-interstitial in germanium as a function of the Fermi level. The calculations suggest that the self-interstitial in germanium can exist in four different charge states: 1–, and 0 for the 1 1 0 split interstitial, 0, 1+, and 2+ for the tetrahedral position. The 1 1 0 split interstitial acts as an acceptor, while the tetrahedral self-interstitial acts as a double donor. Allowing structural changes of the self-interstitial with the charge state, the existence of a “two-state defect” in low-temperature irradiated p-type Ge can be explained.     

Enhancing optical properties of nanocrystalline silicon films with air exposure

We report the effect of air exposure and deposition temperatures, T_d, on the optical property of nanocrystalline silicon (nc-Si). The nc-Si thin films were investigated by photoluminescence (PL), optical absorption, X-ray diffraction (XRD), Fourier-transform infrared (FTIR) absorption and Raman scattering. Experimental results show the structural change from an amorphous to a nanocrystalline phase at T_d=80 °C. In addition, it suggests that T_d low condition leads to the increase in the density of SiH-related bonds and a decrease in the average grain size, δ. The oxygen absorption peak increases with the air-exposure time. The PL exhibited two peaks at around 1.75–1.78 and 2.1–2.3 eV. The PL increases and blue shifts consistently with the decrease of δ and increase of oxygen content. The first peak may be related to nanocrystallites in nc-Si films and the origin of another one may be due to defect-related oxygen. Thus, by the plasma-enhanced chemical vapor deposition (PECVD) technique at low T_d, we can produce the nc-Si films with different grain sizes, causing the corresponding luminescent properties. The new method processes advantages of low deposition temperature and effective oxidation of nc-Si on inexpensive substrates, thus making it more suitable for developing low-cost array or flexible nc-Si optoelectronic devices.     

The impacts of high tensile stress CESL and geometry design on device performance and reliability for 90 nm SOI nMOSFETs

The thickness effects of high-tensile-stress contact etch stop layer (HS CESL) and impact of layout geometry (length of diffusion and gate width) on mobility enhancement of 100/(100) 90 nm SOI nMOSFETs were studied in detail. Additionally, we also inspected the low frequency characteristic with low-frequency noise investigation for FB-SOI nMOSFETs. Experimental results show that devices with 1100 Å HS CESL possess worse characteristics and hot-carrier-induced degradations than devices with 700 Å HS CESL due to serious stress-induced defects happen. The lower plateau of Lorentzian noise spectrum observed from input-referred voltage noise (S_vg) implies higher leakage current for the devices with 1100 Å HS CESL. On the other hand, we found that devices with narrow gate widths possess higher driving capacity because of larger fringing electric fields and higher compressive stress in direction perpendicular to the channel. Owing to the more serious impact of compressive stress in direction parallel to the channel, the device performance was degraded particularly for devices with shorter LOD.     

Elemental specificity of ion cores and ionization entropy of vacancy-group-V-impurity atom pairs in Ge crystals: ACAR and DLTS data

The positron probing of the donor-vacancy (DV) complexes created in the single crystals of n-GeD (D=P, As, Sb, or Bi) by γ -irradiation Co-60 (T_irr.≈315 K) has been carried out by measuring the angular correlation of the annihilation radiation (ACAR). The maximum overlapping of the positron and electron wave functions in the subvalent shells of the ion cores has been determined for [1 1 1] crystallographic direction by normal approximation method. It has been found that this maximum is shifted from the nuclei of DV complexes in passing from the ion cores of atoms of a relatively small “size”, P and As, to more volumetric ion cores, Sb and Bi, respectively. The shift itself is accompanied by the increase of the probability of the high-momentum annihilation process of the trapped positron during its lifetime. This increase correlates well with the augmentation of the entropy of ionization revealed by DLTS (Markevich et al. Phys. Rev. B70 (2004) 235213) for group-V-impurity atom pairs in germanium. Kolmogorov-Chapmen formalism has been used for studying the probability of the high-momentum annihilation of positron trapped by DV complexes. The results obtained suggest that the growth of the configurational entropy in passing from the ion cores of relatively small “size” to more volumetric ones is accompanied by the relaxation of the ion cores inward towards the free volume related to the vacancy in DV complex.     

A high performance pMOSFET with two-step recessed SiGe-S/D structure for 32 nm node and beyond

A novel SiGe-S/D structure for high performance pMOSFET called two-step recessed SiGe-source/drain (S/D) is developed with careful optimization of recessed SiGe-S/D structure. With this method, hole mobility, short channel effect and S/D resistance in pMOSFET are improved compared with conventional recessed SiGe-S/D structure. To enhance device performance such as drain current drivability, SiGe region has to be closer to channel region. Then, conventional deep SiGe-S/D region with carefully optimized shallow SiGe SDE region showed additional device performance improvement without SCE degradation. As a result, high performance 24 nm gate length pMOSFET was demonstrated with drive current of 451 μA/μm at V_dd of 0.9 V and I_off of 100 nA/μm (552 μA/μm at V_dd of 1.0 V). Furthermore, by combining with V_dd scaling, we indicate the extendability of two-step recessed SiGe-S/D structure down to 15 nm node generation.     

Field-effect transistors based on organic single crystals grown by an improved vapor phase method

High-quality organic single crystals are produced directly onto the substrates using an improved vapor phase method. Unlike the conventional vapor phase methods, the present method is characterized by forming a large-sized crystal to which semiconductor devices can readily be made. The relevant method requires small space of only a 10-cm cube in which a couple of plates are put in close proximity. The crystal growth is carried out nearly at the thermodynamic equilibrium within the narrow space surrounded with the two plates. Thin single crystals of several hundreds of micrometers in size are grown on one of those plates. For the organic materials to be crystallized, we have chosen 1,4-bis(5-phenylthiophen-2-yl)benzene (AC5) and 5,5-diphenyl-2,2′:5′,2″:5″,2:5,2-quinquethiophene (P5T) from among thiophene/phenylene co-oligomers. The resulting crystals are well-defined polygons, each side reflecting the specific crystallographic orientation. In particular, those grown on self-assembled monolayers are exceedingly flat and free from cracks. We have directly fabricated top-contact field-effect transistors on these crystals. The devices exhibit the excellent performance and keep it both in air and in vacuum for a maximum of a hundred days.     

Thermal stress concentration factors for defects in plated-through-vias

Plated-through-vias (PTVs) are subject to thermal stress during soldering and in service. Plating and manufacturing defects in the PTV walls (barrels) can create stress concentrations that frequently become the sites of crack initiation during thermal fatigue. This is of growing concern as processing temperatures increase due to the use of lead-free solders, and boards become thicker generating increased stress as PTV aspect ratios rise, making it more difficult to achieve uniform plating thickness throughout the barrel. Finite element analysis (FEA) has been used to develop correlations that can be used to calculate the stress concentration factors (SCFs) for five typical defects as a function of various geometric parameters. In terms of their severity, the defects were ranked as: (1) rapid thickness reduction (SCF  13), (2) occasional waviness (SCF  4.6), (3) gradual thickness reduction (SCF  4), (4) wicking (SCF  4) and (5) waviness (SCF  3.1). The SCF due to an internal pad and the influence of an external pad-barrel corner crack were also investigated. The maximum stress at the defect is found by multiplying the SCF by the von Mises stress at the mid-plane of the corresponding idealized PTV. The latter can be found using either an analytical model or correlations as a function of the aspect ratio and board-to-barrel thickness ratio that were developed using FEA.     

Determining factors affecting ESD failure voltage using DOE

Factors influencing machine model (MM) ESD failure voltage are investigated in two statistically designed experiments. Several variables (or factors), namely wafer lot, type of ESD handling procedure, pulse polarity order and assembly house are studied. The results are examined using three methods: survival analysis, logistic regression and an empirical approach. Each method can be used to predict the cumulative distribution function (cdf) which is the probability of failure on or before a particular voltage. Survival analysis treats the failure voltage as a response to the settings of the various factors. The failure voltage is analogous to the “failure time”. This method predicts the cdf given the settings of the different variables. In contrast, logistic regression treats voltage as a factor, along with the other variables and will similarly predict the cdf given the settings of all the factors. The empirical approach is used to estimate the cdf using only the distribution of failure voltages for each run in a designed experiment and is not derived from the factor settings. This third approach can be used as a check on the first two.In the first DOE, the factors wafer lot, level of ESD-safe handling, pulse polarity order and their interactions are found to change the predicted median failure voltage from 19 to 34 V, a swing of ±30% from the overall median 26 V. The effect of wafer lot along with the interaction between the level of ESD protection and pulse polarity order are found to be statistically significant. In the second DOE, only the effects of wafer and assembly house are studied. Here, just wafer has a significant effect. The range of ESD failure voltages is much smaller in round 2 (30 to 36 V).Although the failure voltages reported here are relatively low, the methods described herein are general. Thus, the approaches described can be applied to circuits with much higher ESD failure voltages.     

Numerical solutions for orthogonal wavelet filters by Newton method

The wavelet transform has recently generated much interest in applied mathematics, signal processing and image coding. Mallat (1989) used the concept of the function space as a bridge to link the wavelet transform and multiresolution analysis. Daubechies (1990) added regularity conditions to find 2N, 2N10, tap coefficients for orthogonal wavelet filters. Owing to the difficulty of finding their closed solutions for large N a numerical method called the Newton method is proposed. We constructed the orthogonal wavelet filter with 2N-tap coefficients by N linear equations and N nonlinear equations. The 2N-tap, 2N10, coefficients we found are very consistent with those of Daubechies. Also, the method can be used to find the orthogonal wavelet filter with N-tap coefficients for N>10.     

Electrical and structural properties of hafnium silicate thin films

Thin (4 nm) hafnium silicate (HfO₂)_x(SiO₂)_1−x/SiO₂ gate stacks (0 < x < 1) grown by metal organic chemical vapour deposition (MOCVD) are investigated in this study. The focus is on extracting the optical constants, and hence bandgaps as well as dielectric constants. The VUV (vacuum ultraviolet) spectroscopic ellipsometry (VUV-SE) technique in the spectral range 140–1700 nm, together with current–voltage and capacitance–voltage techniques were used for studying the optical and electrical properties of the layers, respectively. The bandgap was found to increase from 5.24 eV for HfO₂ to 6 eV for Hf-silicate with 30% Hf. The permittivity was reduced from 21 for HfO₂ layers to 8 for Hf-silicate with x = 0.3. The results suggest that the optimal Hf content is above 0.6, for which the permittivity higher than 10 can be achieved.     

EPR characterization of defects in monoclinic powders of ZrO2 and HfO2

Electron paramagnetic resonance (EPR) measurements have been made on a variety of commercially available samples of the monoclinic form of the high-dielectric constant (high k) materials ZrO₂ and HfO₂ with the aim of characterizing the defects they contain. All EPR measurements were at about 9.5 GHz and at room temperature. An axially symmetric spectrum with g=1.961(2), g=1.976(2) is observed in most of the ZrO₂ samples and a similar one with g=1.940(3), g=1.970(2) is seen for most of the HfO₂ samples; they are attributed to centres involving Zr³⁺and Hf ³⁺, respectively. Their average concentration lies in the approximate range 10¹⁵–10¹⁷ cm⁻³, depending on the product specification, and, with one exception is unaffected by γ-irradiation. Grinding granules to powder and/or γ-irradiation yields further EPR spectra of defects, some of which are likely to involve oxygen, those are probably in the near surface region.     

Indium tin oxide-free semi-transparent inverted polymer solar cells using conducting polymer as both bottom and top electrodes

Poly(3,4-ethylenedioxythiophene):poly(styrenesulfonate) (PEDOT:PSS) is investigated as a transparent cathode to replace indium tin oxide (ITO) in inverted polymer solar cells. Increasing the thickness of the PEDOT:PSS electrode leads to a reduction in transparency and sheet resistance which lowers the photocurrent but increases the fill factor of the solar cells. The offset of photocurrent and fill factor as the thickness is increased leads to a saturation of the power conversion efficiency to 3%. These electrodes were applied to flexible substrates showing similar device performance to glass based devices. Cyclic bending test of these flexible polymer electrodes show improved conversion efficiency retention (92%) when compared to flexible ITO based electrodes (50%) after 300 bend cycles. In addition to using PEDOT:PSS as a cathode replacement for ITO in inverted solar cells, its use as a semi-transparent anode replacement to Ag is also examined. Semi-transparent inverted solar cells fabricated with ITO as the cathode and PEDOT:PSS as the top anode electrode were demonstrated showing efficiencies of 2.51% while replacement of both ITO and Ag with PEDOT:PSS as both the cathode and anode show efficiencies of 0.47%.     

Pentacene organic field-effect transistors with polymeric dielectric interfaces: Performance and stability

Low-voltage pentacene organic field-effect transistors (OFETs) with different gate dielectric interfaces are studied and their performance in terms of electrical properties and operational stability is compared. Overall high electrical performance is demonstrated at low voltage by using a 100 nm-thick high-κ gate dielectric layer of aluminum oxide (Al₂O₃) fabricated by atomic layer deposition (ALD) and modified with hydroxyl-free low-κ polymers like polystyrene (PS), divinyltetramethyldisiloxane-bis(benzocyclobutene) (BCB) (Cyclotene™, Dow Chemicals), and as well as with the widely used octadecyl-trichlorosilane (OTS). Devices with PS and BCB dielectric surfaces exhibit almost similar electrical performance with high field-effect mobilities, low subthreshold voltages, and high on/off current ratios. The higher mobility in pentacene transistors with PS can be correlated to the better structural ordering of pentacene films, as demonstrated by atomic force microscopy (AFM) images and X-ray diffraction (XRD). The devices with PS show good electrical stability under bias stress conditions (V_GS = V_DS = −10 V for 1 h), resulting in a negligible drop (2%) in saturation current (I_DS) in comparison to that in devices with OTS (12%), and to a very high decay (30%) for the devices with BCB.     

Effect of Polarization Mode Coupling on Extrema Counting Fixed Analyzer PMD Measurement Method

We describe the effect of polarization mode coupling in the single-mode optical fibers on the extrema counting fixed analyzer (FA) polarization mode dispersion (PMD) measurement method. We define the polarization mode coupling coefficient for the over (or under) estimation which occurs with the FA method. We investigate the polarization mode coupling coefficient experimentally by comparison with the air-path (cross-correlation) type interferometric PMD measurement method. Moreover, we discuss the polarization mode coupling experimentally as well as analytically by using pseudo-polarization mode coupling which we obtained by splicing highly birefringent (B  4.5 × 10 ^− 4) polarization maintaining fibers (PMFs) with the random splice angles. The results show that the PMD τ of the single-mode optical fibers which has random polarization mode coupling can be approximated by multiplying the PMD τ obtained using the FA method with the random polarization mode coupling coefficient k  0.82.     

Negative bias temperature instabilities in HfSiO(N)-based MOSFETs: Electrical characterization and modeling

Negative bias temperature instabilities (NBTI) in SiO_x(N)/HfSiO(N)/TaN based pMOSFETs are investigated. It is shown that nitrogen-incorporation in the gate stack (either by NH₃ anneals or decoupled plasma nitridation, DPN) result in much enhanced NBTI. Device degradation is mainly due to fast (interface) state generation in the non-nitrided stacks, while a substantial contribution of the defects produced in the nitrided stacks are slow (bulk) states. The kinetics of fast interface states is modeled within a reaction-dispersive transport model, taking into account the dispersive transport of protons generated from the depassivation of trivalent Si dangling bonds at the Si/SiO_x interace (P_b0 centers). The generation of slow states in the nitrided stacks is simulated by an electrochemical model, considering the electric field and hole assisted breaking of nitrogen-related defects, tentatively attributed to Si₂N or Hf₂N dangling bonds. A correlation between NBTI and recovery is also found, namely that enhanced NBTI in nitrided stacks results in enhanced recovery. This suggests that recovery mainly arises from the detrapping of holes at the N-related defects.     

Reliability results of HBTs with an InGaP emitter

Accelerated lifetest results are presented on HBTs with InGaP emitters. An Arrhenius plot indicates the existence of a temperature dependent activation energy, E_a. A low E_a mechanism dominates above T_j 380 °C and a high E_a mechanism dominates at lower temperature. The critical transition temperature between regimes is determined using the method of maximum likelihood. The difference in E_a’s between low and high temperature regimes is statistically significant.A comparison is made between lifetimes determined from at temperature vs. 40 °C data. No significant difference is observed indicating that beta degradation can be monitored at temperature only and cooling to low temperature is not necessary. Other comparisons indicate that junction temperatures up to 367 °C can still provide good estimates of lower temperature behavior.By the method of maximum likelihood, the predicted MTTF at T_j = 125 °C is 7.6 × 10⁹ h with 95% CBs of [6.4 × 10⁸, 8.9 × 10¹⁰]. Given the typical industry standard of 1 × 10⁶ h, the reliability requirements are easily met.It is suggested that the standard of 1 × 10⁶ h does not adequately capture failure time variation and that a better specification is in terms of fails in time (FITs). The 10 year average FIT rate at 125 °C is found to be negligible. Assuming a much higher junction temperature of 210 °C, the average failure rate climbs to 5 FITs with an upper 95% confidence bound of 40 FITs.     

High-quality NiGe/Ge diodes for Schottky barrier MOSFETs

Schottky barrier (SB) Ge channel MOSFETs suffer from high drain-body leakage at the required elevated substrate doping concentrations to suppress source–drain leakage. Here, we show that electrodeposited Ni–Ge and NiGe/Ge Schottky diodes on highly doped Ge show low off current, which might make them suitable for SB-MOSFETs. The Schottky diodes showed rectification of up to five orders in magnitude. At low forward biases, the overlap of the forward current density curves for the as-deposited Ni/n-Ge and NiGe/n-Ge Schottky diodes indicates Fermi-level pinning in the Ge bandgap. The SB height for electrons remains virtually constant at 0.52 eV (indicating a hole barrier height of 0.14 eV) under various annealing temperatures. The series resistance decreases with increasing annealing temperature in agreement with four-point probe measurements indicating the lower specific resistance of NiGe as compared with Ni, which is crucial for high drive current in SB-MOSFETs. We show by numerical simulation that by incorporating such high-quality Schottky diodes in the source/drain of a Ge channel PMOS, highly doped substrate could be used to minimize the subthreshold source to drain leakage current.     

Wideband patch antennas for mobile communications

This paper describes a new technique for bandwidth enhancement of microstrip patch antennas. An electromagnetically coupled (EMC) feeding structure was employed to increase the bandwidth. L-strip feeding rectangular and triangular patches were simulated and tested. The obtained bandwidth (SWR2) is about 1200 MHz (52%) for the rectangular patch, while that of the triangular one is around 1300 MHz (56%). These results provide evidence that the proposed designs can be used in the DCS, PCS, UMTS, WLAN and IMT-2000 service frequency bands.     

A numerical Schrödinger–Poisson solver for radially symmetric nanowire core–shell structures

We present here a general purpose numerical Schrödinger–Poisson solver for radially symmetric nanowire core–shell structures for electronic and optoelectronic applications. The solver provides self-consistent solutions of the Schrödinger equation and the Poisson equation in cylindrical coordinates, for nanowire core–shell structures with radial compositional variation. Quantized energy levels as well as their associated electron wavefunctions and populations can be obtained from the solutions. Individual equation solvers were verified by comparison with scenarios where analytical results exist; verification of the self-consistent solution process was done by comparing results in the large radius limit with numerical solutions for a rectangular slab structure. We apply this solver to compute the charge/capacitance–voltage characteristics for a nanowire field effect device with wrap-around gate. It is shown that quantum confinement and the low dimensionality can give rise to, for representative nanowire FETs considered, 30% reduction in gate capacitance compared to the classically predicted value, and is 1/3 of the geometrical barrier limited capacitance.     

Metallization of microvias by sputter-deposition

In high-density interconnection technologies the size of via holes significantly effects the space available for component assembly. Commonly used CO₂ lasers do not produce microvias small enough for future demands. In this paper we investigate metallization of UV-laser drilled microvias by magnetron sputtering.The core material of the test boards was a copper-clad FR-4 laminate. The boards were coated with two types of nonphotoimageable liquid dielectrics. A thin chrome layer (0.1 μm) with a subsequent copper layer (3 μm) or copper layer without any intermediate chrome layer was sputtered onto the surfaces and within the microvias. Copper was electrolytically grown onto the sputtered metal layers. In fine lines the adhesion of the metallic layer to the core material is essential. Our earlier studies have shown that chrome has good adhesion to epoxy and it is used as a seeding layer between epoxy and sputtered copper.The purpose of our research is to assess the usefulness of sputtering techniques for metallizing small vias and to find a combination of dielectric material, technologies for microvia formation and plating for achieving reliable microvia connections. Microvias were analyzed after every process stage by means of a microscope and a scanning electronic microscope.