A 5-GHz CMOS Type-II PLL With Low $K_{rm VCO}$ and Extended Fine-Tuning Range

A 5-GHz dual-path integer-$N$ Type-II phase-locked loop (PLL) uses an LC voltage-controlled oscillator and softly switched varactors in an overlapped digitally controlled integral path to allow a large fine-tuning range of approximately 160 MHz while realizing a low susceptibility to noise and spurs by using a low $K_{rm VCO}$ of 3.2 MHz/V. The reference spur level is less than $-$70 dBc with a 1-MHz reference frequency and a total loop-filter capacitance of 26 pF. The measured phase noise is $-$75 and $-$115 dBc/Hz at 10-kHz and 1-MHz offsets, respectively, using a loop bandwidth of approximately 30 kHz. This 0.25-${hbox{mm}}^{2}$ PLL is fabricated in a 90-nm digital CMOS process and consumes 11 mW from a 1.2-V supply.      

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops

A finite-modulo fractional-$N$ PLL utilizing a low-bit high-order $DeltaSigma$ modulator is presented. A 4-bit fourth-order $DeltaSigma$ modulator not only performs non-dithered 16-modulo fractional-$N$ operation but also offers less spur generation with negligible quantization noise. Further spur reduction is achieved by charge compensation in the voltage domain and phase interpolation in the time domain, which significantly relaxes the dynamic range requirement of the charge pump compensation current. A 1.8–2.6 GHz fractional-$N$ PLL is implemented in 0.18 $mu{hbox {m}}$ CMOS. By employing high-order deterministic $DeltaSigma$ modulation and hybrid spur compensation, the spur level of less than $-$55 dBc is achieved when the ratio of the bandwidth to minimum frequency resolution is set to 1/4. The prototype PLL consumes 35.3 mW in which only 2.7 mW is consumed by the digital modulator and compensation circuits.      

A Digital Intensive Fractional-N PLL and All-Digital Self-Calibration Schemes

A digital intensive PLL featuring a digital filter in parallel with an analog feed-forward path and a digital controlled oscillator (DCO) is presented. Digital loop filter replaces analog passive filter to reduce chip area and associated gate-leakage in advanced process. It also allows the PLL loop gain and DCO gain to be digitally calibrated to within 100 ppm within 50 $mu{hbox{s}}$. Such fine frequency resolution enables the PLL to accurately compensate for the loop parameter variation due to process, voltage and temperature (PVT). The analog feed-forward path is insensitive to quantization error of fractional-N divider and DCO nonlinearity. Direct modulating the DCO frequency and phase through the analog feed-forward path, and compensating the modulating signal digitally for the DCO gain variation are demonstrated. At 3.6 GHz all fractional spurs are under $-$ 75 dBc. The phase noise at 400 kHz and 3 MHz are $-$115.6 dBc/Hz and $-$134.9 dBc/Hz, respectively. The chip is fabricated in a 0.13 $mu$ m CMOS process, and occupies an active area of 0.85 ${hbox{mm}}^{2}$ and draws 40 mA from a 1.5 V supply including all auxiliary circuitry.      

A Phase-Locked Loop With Injection-Locked Frequency Multiplier in 0.18-$mu{hbox{m}}$ CMOS for $V$ -Band Applications

In this paper, a novel CMOS phase-locked loop (PLL) integrated with an injection-locked frequency multiplier (ILFM) that generates the $V$-band output signal is proposed. Since the proposed ILFM can generate the fifth-order harmonic frequency of the voltage-controlled oscillator (VCO) output, the operational frequency of the VCO can be reduced to only one-fifth of the desired frequency. With the loop gain smaller than unity in the ILFM, the output frequency range of the proposed PLL is from 53.04 to 58.0 GHz. The PLL is designed and fabricated in 0.18-$mu{hbox{m}}$ CMOS technology. The measured phase noises at 1- and 10-MHz offset from the carrier are $-$ 85.2 and $-{hbox{90.9 dBc}}/{hbox{Hz}}$, respectively. The reference spur level of $-{hbox{40.16 dBc}}$ is measured. The dc power dissipation of the fabricated PLL is 35.7 mW under a 1.8-V supply. It can be seen that the advantages of lower power dissipation and similar phase noise can be achieved in the proposed PLL structure. It is suitable for low-power and high-performance $V$-band applications.      

A 47 GHz Cross-Coupled VCO Employing High- Island-Gate Varactor for Phase Noise Reduction

A 47 GHz $LC$ cross-coupled voltage controlled oscillator (VCO) employing the high-$Q$ island-gate varactor (IGV) based on a 0.13 $mu{rm m}$ RFCMOS technology is reported in this work. To verify the improvement in the phase noise, two otherwise identical VCOs, each with an IGV and a conventional multi-finger varactor, were fabricated and the phase noise performance was compared. With $V_{DD}$ of 1.2 V and core power consumption of 3.86 mW, the VCOs with the IGV and the multi-finger varactor have a phase noise of $-$95.4 dBc/Hz and $-$91.4 dBc/Hz respectively, at 1 MHz offset, verifying the phase noise reduction with the introduction of the high-$Q$ IGV. The VCO with IGV exhibited an output power of around $-$15 dBm, leading to a FoM of $-$182.9 dBc/Hz and a tuning range of 3.35% (45.69 to 47.22 GHz).      

A Phase-Locked Loop With Self-Calibrated Charge Pumps in 3- $muhbox{m}$ LTPS-TFT Technology

A phase-locked loop (PLL) with self-calibrated charge pumps (CPs) has been fabricated in a 3- $muhbox{m}$ low-temperature polysilicon thin-film transistor (LTPS-TFT) technology. A voltage scaler and self-calibrated CPs are used to reduce the static phase error, reference spur, and jitter of an LTPS-TFT PLL. This PLL operates from 5.6 to 10.5 MHz at a supply of 8.4 V. Its area is 18.9 $hbox{mm}^{2}$, and it consumes 7.81 mW at 10.5 MHz. The measured static phase error without and with calibration is 80 and 6.56 ns, respectively, at 10.5 MHz. The measured peak-to-peak jitter without and with calibration is 3.573 and 2.834 ns, respectively. The measured reference spur is $-$26.04 and $-$ 30.2 dBc without and with calibration, respectively. The measured maximal locked time is 1.75 ms.      

A Sub-100 $mu{rm W}$ Ku-Band RTD VCO for Extremely Low Power Applications

This letter presents the microwave performance of a sub-100 $mu{rm W}$ Ku-band differential-mode resonant tunneling diode (RTD)-based voltage controlled oscillator (VCO) with an extremely low power consumption of 87 $mu{rm W}$ using an InP-based RTD/HBT MMIC technology. In order to achieve the extremely low-power Ku-band RTD VCO, the device size of RTD is scaled down to $0.6times 0.6 mu{rm m}^{2}$. The obtained dc power consumption of 87 $mu{rm W}$ is found to be only 1/18 of the conventional-type MMIC VCOs reported in the Ku-band. The fabricated RTD VCO has a phase noise of $-$100.3 dBc/Hz at 1 MHz offset frequency and a tuning range of 140 MHz with the figure-of-merit (FOM) of $-$194.3 dBc/Hz.      

A 5-GHz CMOS Frequency Synthesizer With an Injection-Locked Frequency Divider and Differential Switched Capacitors

A phase-locked loop (PLL)-based frequency synthesizer at 5 GHz is designed and fabricated in 0.18-${rm mu}hbox{m}$ CMOS technology. The power consumption of the synthesizer is significantly reduced by using an injection-locked frequency divider (ILFD) as the first frequency divider in the PLL feedback loop. The synthesizer chip consumes 18 mW of power, of which only 3.93 mW is consumed by the voltage-controlled oscillator (VCO) and the ILFD at 1.8-V supply voltage. The VCO has the phase noise of $-$ 104 dBc/Hz at 1-MHz offset and an output tuning range of 740 MHz. The chip size is 1.1 mm $times$ 0.95 mm.      

A Novel Multiloop Optoelectronic Oscillator

We present a novel realization of a multiloop optoelectronic oscillator based on a wavelength multiplexed optical source and fiber Bragg grating reflectors. The oscillator exhibits a phase noise of $-$108 dBc/Hz at 10-kHz offset from the 10.2-GHz carrier while suppressing parasitic modes to below $-$80 dBc.      

A Single-PLL UWB Frequency Synthesizer Using Multiphase Coupled Ring Oscillator and Current-Reused Multiplier

A single phase-locked loop (PLL) frequency synthesizer for a Mode-1 multiband orthogonal frequency-division multiplexing (MB-OFDM) ultrawideband (UWB) system is realized in 0.13-$mu hbox{m}$ CMOS. A current-reused multiply-by-1.5 circuit and a multiphase coupled ring oscillator are adopted to reduce the power consumption. For a 4.488-GHz signal, the measured image sideband is $-$40 dBc. The measured switching time from 3.342 to 4.488 GHz is 1.5 ns. The area is $0.85 times 0.9 hbox{mm}^{2}$ and the power is 31.2 mW for a 1.2-V supply voltage.      

An FIR-Embedded Noise Filtering Method for $Delta Sigma$ Fractional-N PLL Clock Generators

This paper describes a noise filtering method for $Delta Sigma$ fractional- $N$ PLL clock generators to reduce out-of-band phase noise and improve short-term jitter performance. Use of a low-cost ring VCO mandates a wideband PLL design and complicates filtering out high-frequency quantization noise from the $Delta Sigma$ modulator. A hybrid finite impulse response (FIR) filtering technique based on a semidigital approach enables low-OSR $Delta Sigma$ modulation with robust quantization noise reduction despite circuit mismatch and nonlinearity. A prototype 1-GHz $Delta Sigma$ fractional-$N$ PLL is implemented in 0.18 $muhbox{m}$ CMOS. Experimental results show that the proposed semidigital method effectively suppresses the out-of-band quantization noise, resulting in nearly 30% reduction in short-term jitter.      

A 0.65-V 2.5-GHz Fractional-N Synthesizer With Two-Point 2-Mb/s GFSK Data Modulation

We present ultra-low-voltage circuit design techniques for a fractional-N RF synthesizer with two-point modulation which was realized in 90-nm CMOS using only regular ${rm V}_{rm T}$ devices.; the voltage controlled oscillator, phase-frequency detector and charge pump operate from a 0.5 $~$V supply while the divider uses a 0.65$~$V supply. The frequency synthesizer achieves a phase noise better than $-$120 dBc/Hz at 3 MHz, while consuming 6 mW. A calibration technique to equalize the gain between the two modulation ports is introduced and enables phase/frequency modulation beyond the loop bandwidth of the phase-locked loop. Measurement results for 2-Mb/s GFSK modulation are presented.      

A Low Voltage and Low Power Bottom-Series Coupled Quadrature VCO

This letter presents a new low power quadrature voltage-controlled oscillator (QVCO), which consists of two complementary cross-coupled voltage-controlled oscillators (VCOs) with split-source tail inductors. The bottom-series coupling transistors are in parallel with the tail inductors and require no dc voltage headroom. The proposed CMOS QVCO has been implemented with the TSMC 0.18 $mu{rm m}$ CMOS technology and the die area is $0.512times 1.065 {rm mm}^{2}$. At the supply voltage of 1.1 V, the total power consumption is 2.545 mW. The free-running frequency of the QVCO is tunable from 4.38 to 4.71 GHz as the tuning voltage is varied from 0.0 V to 0.6 V. The measured phase noise at 1 MHz frequency offset is $-$120.8 dBc/Hz at the oscillation frequency of 4.4 GHz and the figure of merit (FOM) of the proposed QVCO is $-$ 189.61 dBc/Hz.      

17 GHz RF Front-Ends for Low-Power Wireless Sensor Networks

A 17 GHz low-power radio transceiver front-end implemented in a 0.25 $mu{hbox {m}}$ SiGe:C BiCMOS technology is described. Operating at data rates up to 10 Mbit/s with a reduced transceiver turn-on time of 2 $mu{hbox {s}}$, gives an overall energy consumption of 1.75 nJ/bit for the receiver and 1.6 nJ/bit for the transmitter. The measured conversion gain of the receiver chain is 25–30 dB into a 50 $Omega$ load at 10 MHz IF, and noise figure is 12 $pm$0.5 dB across the band from 10 to 200 MHz. The 1-dB compression point at the receiver input is $-$37 dBm and ${hbox{IIP}}_{3}$ is $-$25 dBm. The maximum saturated output power from the on-chip transmit amplifier is $-$1.4 dBm. Power consumption is 17.5 mW in receiver mode, and 16 mW in transmit mode, both operating from a 2.5 V supply. In standby, the transceiver supply current is less than 1 $mu{hbox {A}}$.      

Integrated Quadrature Couplers and Their Application in Image-Reject Receivers

Several fully-integrated multi-stage lumped-element quadrature hybrids that enhance bandwidth, amplitude and phase accuracies, and robustness are presented, and a fully-integrated double-quadrature heterodyne receiver front-end that uses two-stage Lange/Lange couplers is described. The Lange/Lange cascade exploits the inherent wide bandwidth characteristic of the Lange hybrid and enables a robust design using a relatively low transformer coupling coefficient. The measured image-rejection ratio is $>$ 55 dB over a 200 MHz bandwidth centered around 5.25 $~$GHz without any tuning, trimming, or calibration; the front-end features 23.5 dB gain, $-$79 dBm sensitivity, 5.6 dB SSB NF, $-$7$~$ dBm IIP3, $-$18 dB $S_{11}$ and a 1 mm $times$ 2 mm die area in 0.18$ mu{hbox {m}}$ CMOS.      

A Differential Clapp-VCO in 0.13 $mu{rm m}$ CMOS Technology

A new differential voltage-controlled oscillator (VCO) is designed and implemented in a 0.13 $mu{rm m}$ CMOS 1P8M process. The designed circuit topology is an all nMOS LC-tank Clapp-VCO using a series-tuned resonator. At the supply voltage of 0.9 V, the output phase noise of the VCO is $-$110.5 dBc/Hz at 1 MHz offset frequency from the carrier frequency of 18.78 GHz, and the figure of merit is $-$188.67 dBc/Hz. The core power consumption is 5.4 mW. Tuning range is about 3.43 GHz, from 18.79 to 22.22 GHz, while the control voltage was tuned from 0 to 1.3 V.      

Q-Band pHEMT and mHEMT Subharmonic Gilbert Upconversion Mixers

This letter makes a comparison between Q-band 0.15 $mu{rm m}$ pseudomorphic high electron mobility transistor (pHEMT) and metamorphic high electron mobility transistor (mHEMT) stacked-LO subharmonic upconversion mixers in terms of gain, isolation and linearity. In general, a 0.15 $mu{rm m}$ mHEMT device has a higher transconductance and cutoff frequency than a 0.15 $mu{rm m}$ pHEMT does. Thus, the conversion gain of the mHEMT is higher than that of the pHEMT in the active Gilbert mixer design. The Q-band stacked-LO subharmonic upconversion mixers using the pHEMT and mHEMT technologies have conversion gain of $-$7.1 dB and $-$0.2 dB, respectively. The pHEMT upconversion mixer has an ${rm OIP}_{3}$ of $-$12 dBm and an ${rm OP}_{1 {rm dB}}$ of $-$24 dBm, while the mHEMT one shows a 4 dB improvement on linearity for the difference between the ${rm OIP}_{3}$ and ${rm OP}_{1 {rm dB}}$. Both the chip sizes are the same at 1.3 mm $times$ 0.9 mm.      

An Edge Missing Compensator for Fast Settling Wide Locking Range Phase-Locked Loops

An edge missing compensator (EMC) is proposed to approach the function of an ideal PD with $pm 2 ^{N-1} times 2pi $ linear range with $N$-bit EMC. A PLL implemented with a 9-bit EMC achieves 320 MHz frequency hopping within 10 $~mu{hbox {s}}$ logarithmically which is about 2.4 times faster than the conventional design. The reference spur of the PLL is ${-}{hbox {48.7~dBc}}$ and the phase noise is ${-}hbox{88.31~dBc/Hz}$ at 10 kHz offset with $K_{rm VCO}= -$ 2 GHz/V.      

CMOS Avalanche Photodiode Embedded in a Phase-Shift Laser Rangefinder

This paper presents the design and the characterization of a CMOS avalanche photodiode (APD) working as an optoelectronic mixer. The $hbox{P}^{+}hbox{N}$ photodiode has been implemented in a commercial 0.35-$muhbox{m}$ CMOS technology after optimization with SILVACO. The surface of the active region is $ hbox{3.78} cdot hbox{10}^{-3} hbox{cm}^{2}$. An efficient guard-ring structure has been created using the lateral diffusion of two n-well regions separated by a gap of 1.2 $mu hbox{m}$. When biased at $-$2 V, the best responsitivity $S_{lambda ,{rm APD}} = hbox{0.11} hbox{A/W}$ is obtained at $lambda = hbox{500} hbox{nm}$. This value can easily be improved by using an antireflection coating. At $lambda = hbox{472} hbox{nm}$, the internal gain is about 75 at $-$6 V and 157 at $-$7 V. When biased at $-$6 V, the APD achieves a dark current of 128 $muhbox{A} cdot hbox{mm}^{-2}$ and an excess noise factor $F = hbox{20}$ . Then, the APD is successfully used as an optoelectronic mixer to improve the signal-to-noise ratio of a low-voltage embedded phase-shift laser rangefinder.      

A Wideband PLL-Based G/FSK Transmitter in 0.18 $mu$m CMOS

A wideband phase-locked loop (PLL)-based G/FSK transmitter (TX) architecture is presented in this paper. In the proposed TX, the G/FSK data is applied outside the loop; hence, the data rate is not constrained by the PLL bandwidth. In addition, the PLL remains locked all the time, preventing the carrier frequency from drifting. In this architecture, the G/FSK modulation signal is generated from a proposed Sigma-Delta modulated Phase Rotator $(SigmaDelta{hbox{-PR}})$. By properly combining the multi-phase signals from the PLL output, the $SigmaDelta{hbox{-PR}}$ effectively operates as a fractional frequency divider, which can synthesize modulation signals with fine-resolution frequencies. The proposed $SigmaDelta{hbox{-PR}}$ adopts the input signal as the phase transition trigger, facilitating a glitch-free operation. The impact of the $SigmaDelta{hbox{-PR}}$ on the TX output noise is also analyzed in this paper. The proposed TX with the $SigmaDelta{hbox{-PR}}$ is digitally programmable and can generate various G/FSK signals for different applications. Fabricated in a 0.18 $muhbox{m}$ CMOS technology, the proposed TX draws 6.3 mA from a 1.4 V supply, and delivers an output power of $-$11 dBm. With a maximum data rate of 6 Mb/s, the TX achieves an energy efficiency of 1.5 nJ/bit.