基于ST L6562的120W PFC线路设计与实现

为了使AC/DC电源在满足IEC61000-3-2谐波标准的同时能够实现低成本、高性能,对单级功率因数校正技术(PFC)的需求越来越紧迫,特别是小功率场合。本文按照不同划分原则对PFC技术分类讨论,指出单级PFC技术适用于小功率场合,是PFC技术在小功率应用中发展的必然趋势,同时也是目前PFC技术研究热点。选择临界导电模式(CRM),利用意法半导体(SGS-THOMSON)公司推出的功率因数控制芯片L6562设计一款性价比高的PFC线路,结果表明该电源系统的功率因数提高到0.98以上,总谐波含量低于2.5%,符合IEC61000-3-2谐波电流限制标准.     

Rethinking deep-submicron circuit design

Interconnect delay need not increase as CMOS process geometries shrink, and current IC design methods should suffice for modules of up to 50,000 gates. Beyond that, designers must focus on a new concept - global interconnect design. We consider the effects of both devices and interconnect, and our analysis shows that interconnect delay actually decreases for deep-submicron (DSM) processes in a modular design approach. The physical explanations of these DSM effects shed insight into this and other potential impacts on future high-performance ASIC designs     

A circuit representation technique for automated circuit design

We present a method of automatically generating circuit designs using evolutionary search and a set of circuit constructing primitives arranged in a linear sequence. This representation has the desirable property that virtually all sets of circuit-constructing primitives result in valid circuit graphs. While this representation excludes certain circuit topologies, it is capable of generating a rich set of them including many of the useful topologies seen in hand-designed circuits. Our system allows circuit size (number of devices), circuit topology, and device values to he evolved. Using a parallel genetic algorithm and circuit simulation software, we present experimental results as applied to three analog filter and two amplifier design tasks. In all tasks, our system is able to generate circuits that achieve the target specifications. Although the evolved circuits exist as software models, detailed examinations of each suggest that they are electrically well behaved and thus suitable for physical implementation. The modest computational requirements suggest that the ability to evolve complex analog circuit representations in software is becoming more approachable on a single engineering workstation     

Applied optimization and circuit design

A qualitative review of applied optimization forms is given, illustrated by reference to the linear circuit design problem. When used to solve very difficult problems, optimization theory becomes extremely vague with many conflicting objectives. These opposing standpoints are discussed and an approach is described which attempts to handle the complications. Working online, many of these nebulous aspects can be considered at run-time. To illustrate this approach a lumped-element simulation of a coaxial cable over a frequency band of $\text{1}\text{2}$ MHz-1 GHz is described.     

PPL integrated circuit design methodology

Path programmable logic (PPL) is an integrated circuit design methodology offering small layout areas, greatly reduced design time, and a high degree of technology independence. In this paper, the structure of PPL is presented, and the details of one implementation, static CMOS PPL, are shown. A conceptual model of PPL design using truth and state tables is given. A database format is presented, and the design system using this database is described. Benchmarks comparing PPL to other design methodologies show PPL compares favourably with custom design in terms of layout area while providing significant savings in design time.     

高速ADC电路设计分析

本文主要是从实际应用的角度分析高速ADC电路的设计方法。以一款非常经典的ADC电路设计入手展开分析,从分模拟输入,时钟和供电三部分的设计分别加以分析。通过对高速ADC电路设计的分析使其在能够更好的应用于电路设计中。     

基于FPGA的图像处理电路的设计与实现

以FPGA为平台,设计了灰阶变化、图像压缩、边缘检测等图像处理电路。与传统的设计方法相比较,本设计不仅具有FPGA电路特有的开发周期短、设计效率高、扩展性和升级性良好、设计灵活等特点,而且由于系统采用硬件电路实现,因此在图像处理的速度上具有明显的优势。     

An integrated circuit layout design system

An integrated circuit layout design system is presented. The system is effectively combined with a combinatorial optimization technique and man/machine interaction. This optimization technique allows wiring and placement of components to be determined simultaneously. By means of a c.r.t. display, the layout design of an integrated circuit chip is finally improved.