VMOS—A new MOS integrated circuit technology

A new V-groove MOS integrated circuit technology (VMOS) is described. It makes use of preferential etching of silicon to define the channels of the MOS transistors. The fabrication involves either a three or four mask process and is capable of producing either silicon gate or standard metal gate transistors. The technology results in very short channel length devices using non-critical alignment tolerances. Despite the short channel length, the VMOS transistor exhibits lower output conductance and higher breakdown voltage than a standard MOS transistor.A first order theory is presented for the VMOS transistor along with measurements made on test devices of various channel lengths. Some integrated circuit applications of the technology are also presented, including an R-S fiip-flop and a 27-stage bucket brigade shift register. The advantages of the VMOS technology in such applications are discussed.     

Low-Voltage MOS Translinear Analog Signal Processing

Different design procedures to operate MOS translinear loops at low supply voltage are presented. They utilize innovative biasing strategies based on flipped voltage followers and floating batteries. An alternate topology based on coupled negative feedback loops is also introduced. Simulation and measurement results for various test chip prototypes validate the proposed techniques and allow comparison among them.     

A new buried-oxide isolation for high-speed high-density MOS integrated circuits

The BO-MOS has an extensive oxide-isolated structure which isolates not only the sidewall but also the bottom of the source and drain diffusions, similar to SOS-MOS, and yet it retains high carrier mobility and low-leakage junction properties. A 1024-bit static NMOS RAM is successfully fabricated using photomasks of a redesigned high-density bulk NMOS RAM (Fujitsu MBM8115). The ring oscillator circuit fabricated using existing SOS-CMOS photomasks shows an equivalent speed-power performance to the original SOS device. The fabrication sequence for the BO-MOS requires the same number of photomasks as for the conventional MOS devices.     

MOS integrated piezoresistive microsensors

A comparative performance analysis is reported that addresses different circuit configurations of MOS integrated piezoresistive microsensor. It is proposed that circuit configurations be evaluated in terms of two sensitivities to process-induced spread in circuit parameters as well as in terms of piezoresistive sensitivity. The sensitivities are calculated subject to circuit-parameter correlation.Translated from Mikroelektronika, Vol. 34, No. 1, 2005, pp. 65–71.Original Russian Text Copyright © 2005 by Dragunov.     

MOS VLSI reliability and yield trends

The yield and reliability capability of an MOS technology are shown to be the product of at least six different technological trends; namely those towards: 1) more complex device structures, 2) scaled down feature sizes, 3) increased wafer sizes, 4) factory automation, 5) increased die size and package lead counts, and 6) increasingly sophisticated computer-aided design tools. The capabilities of a specific technology are a function of the equipment and processes by which it is manufactured and these are often the rate-limiting factors for evolution to the next generation of technology. However, because of the impact of scaling trends on MOS IC failure mechanisms, reliability concerns are starting to dominate the rate of technology change. This is evidenced, even at the present, by the fact that technology decisions must be made by trading off one reliability failure mechanism against another. For example, the high storage charge density needed to provide strong signals for alpha-particle-induced soft error immunity, produces high electric fields and oxide breakdown problems in thin-oxide MOS storage capacitors. Failure distribution for both failure mechanisms are shown to be exponentially dependent (in an inverse manner) on the scale factor for oxide thickness. Hot-electron degradation is also exponentially dependent on the scale factor for channel length. Metal and contact electromigration lifetimes can be reduced by the seventh and nineth powers of scale factor, respectively. The implications are that the dominant reliability mechanisms may change in the future, and that wearout will start to impinge on reliability life.     

Comparing MOS and bipolar integrated circuits

In terms of speed and speed/power performance, bipolar integrated circuits are superior to metal-oxide-semiconductor integrated circuits. This superiority is based on the high transconductance inherent in bipolar transistors and is technology-independent. For the MOS case, transconductance is highly technology-dependent, and hence the performance difference will probably diminish in the future. Comparisons of the two technologies in their mid-1966 forms are made; the bipolar performance advantage in most cases is between 10 and 100. MOS integrated circuits have an area-per-function advantage ratio of about 5 for equivalent-function circuits, but a ratio of between 5 and 10 when circuits exploiting the unique MOS properties are considered. In addition, MOS processing is simpler than bipolar processing by approximately 40 percent.     

Analog integrated filter compilation

A review of the progress in automated design of analog integrated filters is presented. Such tools are ahead of other analog circuit automation in terms of the acceptance by designers and practical applicability. A survey of the present-day commercial and academic systems is made and the range of facilities available is compared. The problems faced in the design of this type of software are typical of the problems of analog design systems in general; lack of openness for introduction of new design knowledge, difficulties of dealing simultaneously with expert and novice users, poor integration in design environments, and user-interface problems. The structure of a typical system is studied and the computer methods used within are discussed with regard to such issues as speed, flexibility, and ease-of-use. Some future directions for analog filter compilers are proposed.     

基于MOS管的新型转换开关在集成电路测试中的应用

为了克服继电器在集成电路测试板上触点烧蚀故障率较高,断开时易产生电磁干扰和开关时间过长等缺点,提出了一种基于MOS管的新型转换开关电路,能更加有效地测试芯片,显著降低芯片的成本。本文详细讨论了集成电路测试的要素和基本原则,继电器在测试板上的应用及其局限性,基于MOS管的新型转换开关电路的特点及控制原理。仿真结果表明,该电路在10v电源电压下开关的转换速度为70μs,工作频率可达100kHz以上,灵敏度高,适用于集成电路测试。     

模电教学中BJT与MOS的近似性分析

BJT 与MOS器件及电路是模电重要内容;教学中二者的电路模型与分析方法不一致,学生困惑于两套不同的器件及电路知识。本文在遵循器件及电路工作原理的基础上,首次将二者在小信号模型、电路参数、I-V方程、特性曲线、工作区间、指标计算上进行完整的近似性分析及一致性推导;在二者电路计算中,用三种单管单级放大器实例,阐述近似分析方法的便利性。本文是模电教学的有力补充。     

Performance of integrated dynamic MOS amplifiers

The letter presents measured data of two different types of dynamic amplifier which have been integrated in a standard CMOS metal gate technology. For a supply voltage of ±5 V, gains of 70 dB were obtained with a power dissipation of 58 ?W and 500 ?W at clock frequencies of 10 kHz and 100 kHz, respectively. The dynamic range exceeds 100 dB.     

Protective device for MOS integrated circuits

Two protective devices for MOS integrated circuits have been extensively tested and proved feasible. They also perform more reliably than conventional Zener diodes. One of them has been used in the fabrication of a dual 25-bit MOS and MNOS integrated shift register and performed reliably.     

Calculator-aided design of MOS integrated circuits

A set of programs has been developed for the characterization of the d.c. and transient behavior of MOS integrated circuits. The d.c. analysis program calculates and plots the voltage transfer and power dissipation characteristic of a MOS inverter approached from a new point of view. The algorithm enables the characterization of basic MOS IC cells on desktop calculators. The program for the transient characterization calculates and plots the output waveform of three simple MOS cells most often occurring in MOS IC's.The MOS transistor is simulated in terms of a four-terminal large signal model described by device processing parameters. Complex MOS IC's can be also characterized by appropriate combining of these programs.     

Technology and performance of integrated complementary MOS circuits

The desirable characteristics of complementary MOS circuits are low standby power consumption, high speed, and high noise immunity. These require close control and matching of n- and p-channel transistor characteristics. Acceptable limits for mismatch between devices were derived based on circuit considerations and were related to process variables. Predicted performances were achieved using test circuits; feasibility of the technology has been shown. The reliability of fabricated test structures was evaluated.     

An integrated thermo-capacitive type MOS flow sensor

A prototype of a new thermo-capacitive integrated flow sensor consisting of a floating-gate MOS transistor has been developed. Tantalum pentoxide is the dielectric material between the top (control) gate and the floating-gate. The temperature dependence of the dielectric constant is about 375 ppm/°C. The process flow is compatible with standard MOS process and augmented to include a capacitor module and bulk micromachining. The output voltage change at the flow velocity of 20 m/s is about 26 mV at 57 mW of heater power. The sensitivity in the 0-4 m/s flow velocity region is 4.25 mV(m/s)^-1     

Shielded silicon gate complementary MOS integrated circuit

An electrostatic shield for complementary MOS integrated circuits was developed to minimize the adverse effects of stray electric fields created by the potentials in the metal interconnections. The process is compatible with silicon gate technology. n-doped polycrystalline silicon was used for all the gates and the shield. The effectiveness of the shield was demonstrated by constructing a special field plate over certain transistors. The threshold voltages obtained on a oriented silicon substrate ranged from 1.5 to 3 V for either channel. Integrated inverters performed satisfactorily from 3 to 15 V, limited at the low end by the threshold voltages and at the high end by the drain breakdown voltage of the n-channel transistors. The stability of the new structure with an n-doped silicon gate as measured by the shift inC-Vcurve under 200°C ± 20 V temperature-bias conditions was better than conventional aluminum gate or p-doped silicon gate devices, presumably due to the doping of gate oxide with phosphorous. The advantages of the new structure are: avoidance of field inversion, elimination of guard rings, and thinner and more stable oxides.