NMOS Compatible Work Function of TaN Metal Gate With Erbium-Oxide-Doped Hafnium Oxide Gate Dielectric

This letter demonstrates reduction in effective work function of tantalum-nitride (TaN) metal gate with erbium-oxide-doped hafnium oxide. We report that TaN effective metal-gate work function can be tuned from Si midgap to the conduction band to meet the work-function requirement of NMOSFETs by incorporating ErO in HfO₂ with an equivalent oxide thickness as low as 1.15 nm. Several other lanthanide-oxide doped hafnium oxides show similar characteristics.     

基于二维电势分布的一种新型复合多晶硅栅LDMOS阈值电压模型

本文提出了一种新型的复合多晶硅栅LDMOS结构.该结构引入栅工程的概念,将LDMOST的栅分为n型多晶硅栅和p型多晶硅栅两部分,从而提高器件电流驱动能力,抑制SCEs(short channel effects )和DIBL(drain-induced barrier lowering).通过求解二维泊松方程建立了复合多晶硅栅LDMOST的二维阈值电压解析模型.模型考虑了LDMOS沟道杂质浓度分布和复合栅功函数差的共同影响,具有较高的精度.与MEDICI数值模拟结果比较后,模型得以验证.     

应用于存储卡中的新型EEPROM单元结构

通常的ＥＥＰＲＯＭ单元在应用于实际的存储卡时，因为进位而导致逻辑操作复杂，文中阐述了这种复杂性以及产生这种复杂性的原因，提出了一种新型的ＥＥＰＲＯＭ单元结构，并详细分析了这种结构对逻辑操作的改善，通过该结构与常规ＥＥＰＲＯＭ单元的应用加以比较，进一步说明了其优点。     

Novel Twin Poly-Si Thin-Film Transistors EEPROM With Trigate Nanowire Structure

This letter demonstrates a novel twin poly-Si thinfilm transistor (TFT) electrical erasable PROM (EEPROM) that utilizes trigate nanowires (NWs). The NW TFT EEPROM has superior gate control because its trigate structure provides a higher memory window and program/erase (P/E) efficiency over those of a single-channel one. For endurance and retention, the memory window can be maintained at 1.5 V after $hbox{10}^{3}$ P/E cycles and 25% charge loss for ten years of NW twin poly-Si EEPROM. This investigation explores its feasibility in future active matrix liquid crystal display system-on-panel and 3-D stacked Flash memory applications.      

异质栅非对称Halo SOI MOSFET

为了抑制异质栅SOI MOSFET的漏致势垒降低效应，在沟道源端一侧引入了高掺杂Halo结构．通过求解二维电势Poisson方程，为新结构器件建立了全耗尽条件下表面势和阈值电压解析模型，并对其性能改进情况进行了研究．结果表明，新结构器件比传统的异质栅SOI MOSFETs能更有效地抑制漏致势垒降低效应，并进一步提高载流子输运效率．新结构器件的漏致势垒降低效应随着Halo区掺杂浓度的增加而减弱，但随Halo区长度非单调变化．解析模型与数值模拟软件MEDICI所得结果高度吻合．     

A Novel Low-Temperature Polysilicon Thin-Film Transistors With a Self-Aligned Gate and Raised Source/Drain Formed by the Damascene Process

In this letter, a novel structure of the polycrystalline silicon thin-film transistors (TFTs) with a self-aligned gate and raised source/drain (RSD) formed by the damascene process has been developed and investigated. Comparing with the conventional coplanar TFT, the proposed RSD TFT has a remarkable lower off-state current (177 to 6.29 nA), and the on/off current ratio is only slightly decreased from 1.71 times 10⁷ to 1.39 times 10⁷. Only four photomasking steps are required. This novel structure is an excellent candidate for further high-performance large-area device applications.     

Carbon-Doped Polysilicon Floating Gate for Improved Data Retention and P/E Window of Flash Memory

We propose a novel approach to engineering floating gates (FGs) of Flash memory cells, namely, carbon incorporation into polysilicon FGs. This technique demonstrated an improvement in retention and a larger program/erase $V_{t}$ window, particularly for smaller capacitance coupling ratio cells, which is important for future scaled Flash memory cells.      

NMOS Compatible Work Function of TaN Metal Gate With Gadolinium Oxide Buffer Layer on Hf-Based Dielectrics

Reduction in effective work function (EWF) of midgap-tantalum nitride (TaN) metal gate with gadolinium-oxide buffer layer on Hafnium-based high-$kappa$gate stack has been demonstrated. EWF of 4.2 eV is achieved for TaN with a bilayer arrangement of$hboxGd_2 O_3/hboxHfSiO_x$dielectric. By using Gd–Si cosputtered layer on$hboxHfO_2$, a reduction in EWF to nMOS compatible value of 4.05 eV is obtained. Electrical and material characterization indicate that the conversion of gadolinium to gadolinium oxide and presence of silicon in the high-$kappa$layer are responsible for the EWF shift. nMOSFETs with improved output current, transconductance, and channel electron mobility highlight the approach of using gadolinium in the gate stack.     

HfLaON n-MOSFETs Using a Low Work Function HfSix Gate

At a 1.2-nm equivalent oxide thickness, HfSi_x/Hf_0.7La_0.3ON n-MOSFETs showed an effective work function of 4.33 eV, a low threshold voltage of 0.18 V, and a peak electron mobility of 215 cm²/(Vldrs). These self-aligned and gate-first HfSi_x/Hf_0.7La_0.3ON n-MOSFETs were processed using standard ion implantation and 1000-degC rapid thermal annealing, making them fully compatible with current very large scale integration fabrication lines.     

A Novel Four-Mask-Step Low-Temperature Polysilicon Thin-Film Transistor With Self-Aligned Raised Source/Drain (SARSD)

In this letter, a novel structure of polycrystalline-silicon thin-film transistors (TFTs) with self-aligned raised source/drain (SARSD) and a thin channel has been developed and investigated. In the proposed structure, a thick SD and a thin active region could be achieved with only four mask steps, which are less than that in conventional raised SD TFTs. The proposed SARSD TFT has a higher on-state current and a lower off-state leakage current. Moreover, the on/off current ratio of the proposed SARSD TFT is also higher than that of a conventional coplanar TFT     

Widely Tunable Work Function TaN/Ru Stacking Layer on HfLaO Gate Dielectric

For the first time, we demonstrate experimentally that using HfLaO high-kappa gate dielectric and vertical stacks of TaN/Ru metal layers, dual metal gates with continuously tunable work function over a very wide range from 3.9 to 5.2 eV, can be achieved after 1000 degC annealing required by a conventional CMOS source/drain activation process. The wide tunability of work function for this bilayer metal structure is attributed to metal interdiffusion during annealing and the release of Fermi level pinning between metal gates (Ru and TaN) and HfLaO. Moreover, this change is thermally stable and unaffected by a subsequent high temperature process.     

异质栅单Halo沟道SOI中隐埋层对器件特性的影响

研究异质栅单Halo沟道SOI MOS器件的隐埋层中二维效应对器件特性,如电势分布、阈值电压等的影响,仿真结果表明,隐埋层中的二维效应会引起更明显的SCE及DIBL效应.在考虑隐埋层二维效应的基础上,提出了一个新的二维阈值电压模型,能较好地吻合二维器件数值模拟软件Medici的仿真结果.     

A Novel Single-Cavity Dual Mode Substrate Integrated Waveguide Filter With Non-Resonating Node

A single-cavity novel dual mode substrate integrated waveguide (SIW) filter with non-resonating node (NRN) is presented. The NRN is implemented by etching a coplanar waveguide on the top metal layer of SIW cavity. Under such circumstances, the filter occupies similar area in comparison with conventional two-pole SIW counterparts, but exhibits better frequency selectivity. The measured S-parameters of the realized filter agree well with the simulated ones, with its good performance predicted.      

Compact Dual Band Bandpass Filter Using Novel E-Type Resonators With Controllable Bandwidths

A compact microstrip dual band bandpass filter (BPF) using novel E-type resonators is presented in this letter. The E-type resonator is a short-circuited stub loaded hairpin resonator, two passband frequencies of which can be regulated by adjusting the characteristic impedance and electrical length of the hairpin and the stub. By combining pseudo-interdigital coupling structure, the coupling coefficients of two bands can be adjusted to a desired value in a relatively wide range. In addition, hook feed line is introduced to obtain desired external coupling degrees for two bands. Thus, controllable fractional bandwidths (FBWs) can be achieved. Two two-order 2.45/5.25 GHz dual band BPFs with 3 dB FBW 7%/7% and 5%/5%, respectively, are designed. The measured result agrees well with the simulation.      

Proposal of Single Metal/Dual High-$k$ Devices for Aggressively Scaled CMISFETs With Precise Gate Profile Control

We have proposed a single metal/dual high-$k$ gate stack for aggressively scaled complementary metal–insulator–semiconductor field-effect transistors (MISFETs). The threshold voltage is controlled by the dual high-$k$ dielectrics, such as MgO- and $hbox{Al}_{2}hbox{O}_{3}$ -containing HfSiON for n- and p-type MISFETs, respectively. The gate profile is precisely controlled by taking advantage of a common gate electrode, which will suppress the variation in device performance. Based on this device concept, we have actually fabricated W/TiN/HfMgSiON n-type MISFETs and W/TiN/HfAlSiO p-type MISFETs and have successfully demonstrated a low threshold voltage operation for both of n- and p-type MISFETs.      

Effective Work Function Engineering of TaxCy Metal Gate on Hf-Based Dielectrics

This letter reports the engineering of effective work function (EWF) for tantalum carbide (TaC) metal gate on high-k gate dielectrics. The dependence of EWF on Si concentration in HfSiO as well as nitridation techniques is revealed. The EWF was extracted by both terraced oxide and terraced high-k techniques with the bulk and interface charges taken into account. The incorporation of Si in Hf-based dielectrics results in an increase of EWF, while the presence of N tends to decrease the EWF. Plasma nitridation is found to be more effective in lowering the EWF than a thermal nitridation. The phenomena can be explained by the modification of TaC/high-k interface dipole moment, which arises from the electronegativity difference for various interface bonds. Based on the above findings, we proposed a novel approach to reduce the EWF of TaC on HfSiON by using a thin HfO₂ cap layer after optimizing the nitridation. The MOSFET results show that this technique is able to achieve a lower V_t without degrading the device performance     

一种带有自适应纠错功能的通信射频模块控制电路

通信基带模块需要以很高的速率对通信射频模块进行控制,现行技术依靠前向纠错码(FEC)或自动重传请求算法(ARQ)等特定纠错算法进行数据校验,前者算法比较复杂并需要较多的硬件资源和带宽,后者将因为双向数据传输和等待在通信通路中造成较大时延.本文提出了一种带有自适应纠错功能的通信射频模块控制电路,对信号跳变错误和有效信号跳变可以做出有效区分并加以处理,以较少的硬件消耗实现了对射频模块的有效控制.     

The Effect of Oxygen on the Work Function of Tungsten Gate Electrodes in MOS Devices

The effect of oxygen on the work function of tungsten electrodes has been studied. As expected, it was found that the presence of the metastable A15 $(beta)$ phase is correlated with oxygen concentration. Tungsten films with minimal oxygen content contain only the stable bcc $(alpha)$ phase. However, after a forming gas anneal was performed on MOS capacitors made from these films, it was found that the $beta$ phase converts completely to a strained $alpha$ phase. Despite this uniform transformation, it was found that the work function of the tungsten gate electrodes varies from 4.54–4.91 eV, depending on the partial pressure of oxygen that the tungsten films were grown in. This is a novel work function tuning technique, and it is hypothesized that the observed variation is due solely to the incorporation of oxygen from the growth environment into the W layer at the $ hbox{SiO}_{2}/hbox{W}$ interface.      

锗预非晶化注入对镍硅(NiSi)金属栅功函数的影响研究

随着超大规模集成电路技术的发展,CMOS器件的制备过程需要同时引入金属栅和超浅结等新的先进工艺技术,因此各种新工艺的兼容性研究具有重要意义.本文研究了超浅结工艺中使用的锗预非晶化对镍硅(NiSi)金属栅功函数的影响.对具有不同剂量Ge注入的NiSi金属栅MOS电容样品的研究表明,锗预非晶化采用的Ge注入对NiSi金属栅的功函数影响很小(小于0.03eV),而且Ge注入也不会导致氧化层中固定电荷以及氧化层和硅衬底之间界面态的增加.这些结果表明,在自对准的先进CMOS工艺中,NiSi金属栅工艺和锗预非晶化超浅结工艺可以互相兼容.