Investigation of temperature-dependent characteristics of ann+-InGaAs/n-GaAs composite doped channel HFET

The temperature-dependent characteristics of an n⁺-InGaAs/n-GaAs composite doped channel (CDC) heterostructure field-effect transistor (HFET) have been studied. Due to the reduction of leakage current and good carrier confinement in the n ⁺-InGaAs/n-GaAs CDC structure, the degradation of device performances with increasing the temperature is insignificant. Experimentally, for a 1×100 μm² device, the gate-drain breakdown voltage of 24.5 (22.0) V, turn-on voltage of 2.05 (1.70) V, off-state drain-source breakdown voltage of 24.4 (18.7) V, transconductance of 161 (138) mS/mm, output conductance of 0.60 (0.60) mS/mm, and voltage gain of 268 (230) are obtained at 300 (450) K, respectively. The shift of V_th from 300 to 450 K is only 13 mV. In addition, the studied device also shows good microwave performances with flat and. wide operation regime     

An all implanted self-aligned enhancement mode n-JFET with Zn gatesfor GaAs digital applications

An all implanted self-aligned n-channel JFET fabrication process is described where Zn implantation is used to form the p⁺ gate region. A refractory metal (W) gate contact is used to allow subsequent high temperature activation of the self-aligned Si source and drain implant. 0.7 μm JFET's have a maximum transconductance of 170 mS/mm with a saturation current of 100 mA/mm at a gate bias of 0.9 V. The p⁺/n homojunction gate has a turn on voltage of 0.95 V at a current of 1 mA/mm. The drain-source breakdown voltage is 6.5 V. Microwave measurements made at a gate bias of 1 V show an f_t of 19 GHz with an f_max of 36 GHz. These devices show promise for incorporation in both DCFL and complementary logic circuits     

High-linearity high-current-drivabilityGa0.51In0.49P/GaAs MISFET usingGa0.51In0.49P airbridge gate structure grown byGSMBE

A novel structure Ga_0.51In_0.49P/GaAs MISFET with an undoped Ga_0.51In_0.49P layer serving as the airbridge between active region and gate pad was first designed and fabricated. Wide and flat characteristics of g_m and f_max versus drain current or gate voltage were achieved. The device also showed a very high maximum current density (610 mA/mm) and a very high gate-to-drain breakdown voltage (25 V). Parasitic capacitances and leakage currents were minimized by the airbridge gate structure and thus high f_T of 22 GHz and high f_max of 40 GHz for 1 μm gate length devices were attained. To our knowledge, both were the best reported values for 1 μm gate GaAs channel FET's     

Analytical models for n+-p+ double-gate SOIMOSFET's

Previously, we proposed n⁺-p⁺ double-gate SOI MOSFET's, which have n⁺ polysilicon for the back gate and p⁺ polysilicon for the front gate to enable adjustment of the threshold voltage, and demonstrated high speed operation. In this paper, we establish analytical models for this device, This transistor has two threshold voltages related to n⁺ and p⁺ polysilicon gates: V_th1 and V_th2, respectively. V _th1 is a function of the gate oxide thickness t_Ox and SOI thickness t_Si and is about 0.25 V when t_Ox/t_Si=5, while V_th2 is insensitive to t_Ox and t_Si and is about 1 V. We also derive models for conduction charge and drain current and verified their validity by numerical analysis. Furthermore, we establish a scaling theory unique to the device, and show how to design the device parameters with decreasing gate length. We show numerically that we can design sub 0.1 μm gate length devices with an an appropriate threshold voltage and an ideal subthreshold swing     

A novel GaAs FET with double camel-like gate structure

Extremely high potential barrier height and gate turn-on voltage of a novel GaAs field-effect transistor with n/sup +//p/sup +//n/sup +//p/sup +//n double camel-like gate structure are demonstrated. The maximum electric field and potential barrier height of the double camel-like gate are substantially enhanced by the addition of another n/sup +//p/sup +/ layers in gate region, as compared with the conventional n/sup +//p/sup +//n single camel-like gate. For a 1/spl times/100 /spl mu/m/sup 2/ device, a potential barrier height up to 2.741 V is obtained. Experimentally, a high gate turn-on voltage up to +4.9 V is achieved because two reverse-biased junctions of the double camel-like gate absorb part of positive gate voltage. In addition, the transistor action shows a maximum saturation current of 730 mA/mm and an extrinsic transconductance of 166 mS/mm.     

High-breakdown characteristics of the InP-based heterostructurefield-effect transistor withIn0.34Al0.66As0.85Sb0.15Schottky layer

We report improved breakdown characteristics of InP-based heterostructure field-effect transistors (HFET's) utilizing In_0.34 Al_0.66As_0.85Sb_0.15 Schottky layer grown by low-pressure metalorganic chemical vapor deposition. Due to high energy bandgap and high Schottky barrier height (>0.73 eV) of the In_0.34Al_0.66As_0.85Sb_0.15 Schottky layer, high two-terminal gate-to-drain breakdown voltage of 40 V, three-terminal off-state breakdown voltage of 40 V three-terminal threshold-state breakdown voltage of 31 V, and three-terminal on-state breakdown voltage of 18 V at 300 K for In_0.75Ga_0.25As channel, are achieved. Moreover, the temperature dependence of two-terminal reverse leakage current is also investigated. The two-terminal gate-to-drain breakdown voltage is up to 36 V at 420 K. A maximum extrinsic transconductance of 216 mS/mm is obtained with a gate length of 1.5 μm     

Impact ionization and transport in the InAlAs/n+-InPHFET

We have carried out an experimental study exploring both impact ionization and electron transport in InAlAs/n⁺-InP HFET's. Our devices show no signature of impact ionization in the gate current, which remains below 17 μA/mm under typical bias conditions for L_g=0.8 μm devices (60 times lower than for InAlAs/InGaAs HEMT's). The lack of impact ionization results in a drain-source breakdown voltage (BV_DS) that increases as the device is turned on, displaying an off-state value of 10 V. Additionally, we find that the channel electron velocity approaches the InP saturation velocity of about 10⁷ cm/s (in devices with L_g<1.6 μm) rather than reaching the material's peak velocity. We attribute this to the impact of channel doping both on the steady-state peak velocity and on the conditions necessary for velocity overshoot to take place. Our findings suggest that the InP-channel HFET benefits from channel electrons which remain cold even at large V_GS and V_DS making the device well-suited to power applications demanding small I_G, low g_d, and high BV_DS     

A CMOS compatible lateral emitter switched thyristor with enhancedturn-on capability

A new Lateral Emitter Switched Thyristor structure (LEST) is proposed and experimentally verified. The structure differs from the conventional LEST in that it embeds a floating ohmic contact between the n^- drift region and the n⁺ floating emitter. Both simulation and experimental results show that the device has an enhanced turn-on capability compared with the conventional LEST without deteriorating its other characteristics. The device is fabricated using a 3 μm CMOS process to have a 320 V breakdown voltage and a 0.7 V threshold voltage. Thyristor turn-on is observed at an anode voltage below 2 V. The maximum MOS controllable current density is in excess of 200 A/cm² with 5 V gate voltage     

4-GHz 15-W power GaAs MESFET

High-field behavior of GaAs MESFET's such as drain-source breakdown characteristics and visible light emission and a model explaining these phenomena are described. An FET structure with a high drain-source breakdown voltage in excess of 26 V has been developed following an analysis of the high-field behavior of the device. Typical characteristics of the fabricated devices at 4 GHz are as follows: Pout= 9.6 W Ga= 5 dB ηadd= 33.6 percent at 18 V from single chip (WG= 13 mm) Pout= 15 W Ga= 5 dB ηadd= 28.3 percent at 22 V from two chip (WG= 26 mm) where Pout, Ga, ηadd, and WGindicate the output power, associated power gain, power added efficiency, and total gate width of the FET's, respectively.     

DC characteristics of high-breakdown-voltage p-i-n diodes made by20-MeV Si implantation in InP:Fe

A vertical p-i-n diode is made for the first time in InP:Fe using megaelectronvolt energy ion implantation, A 20-MeV Si implantation and kiloelectronvolt energy Be/P coimplantation are used to obtain a buried n⁺ layer and a shallow p⁺ layer, respectively. The junction area of the device is 2.3×10^-5 cm² and the intrinsic region thickness is ≈3 μm. The device has a high breakdown voltage of 110 V, reverse leakage current of 0.1 mA/cm² at -80 V, off-state capacitance of 2.2 nF/cm² at -20 V, and a DC incremental forward resistance of 4 Ω at 40 mA     

Anisotype-gate self-aligned p-channel heterostructure field-effecttransistors

A new self-aligned p-channel HFET structure was evaluated for application to complementary HFET circuits. The AlGaAs/InGaAs HFET structure uses an anisotype graded n⁺ InGaAs/GaAs semiconductor gate to enhance the barrier height of the FET, resulting in a significant reduction in gate leakage current at low voltages. With AlGaAs composition of x=0.3, and a thin AlAs spacer of 60 Å, leakage current was reduced by a factor of about 1000 at gate voltage of 1 V, when compared to AlGaAs/InGaAs HIGFET of aluminum content x=0.75. The anisotype PFET maintains high device transconductance, typically 50 mS/mm for 1.3×10 μm PFETs, high reverse breakdown voltages 9-10 V, and low capacitance. Microwave S -parameter characterization resulted in F_t of 5 GHz for a 1×50 μm PFET     

DC and RF characteristics of E-mode Ga/sub 0.51/In/sub 0.49/P-In/sub 0.15/Ga/sub 0.85/As pseudomorphic HEMTs

The DC and RF characteristics of Ga/sub 0.49/In/sub 0.51/P-In/sub 0.15/Ga/sub 0.85/As enhancement- mode pseudomorphic HEMTs (pHEMTs) are reported for the first time. The transistor has a gate length of 0.8 /spl mu/m and a gate width of 200 /spl mu/m. It is found that the device can be operated with gate voltage up to 1.6 V, which corresponds to a high drain-source current (I/sub DS/) of 340 mA/mm when the drain-source voltage (V/sub DS/) is 4.0 V. The measured maximum transconductance, current gain cut-off frequency, and maximum oscillation frequency are 255.2 mS/mm, 20.6 GHz, and 40 GHz, respectively. When this device is operated at 1.9 GHz under class-AB bias condition, a 14.7-dBm (148.6 mW/mm) saturated power with a power-added efficiency of 50% is achieved when the drain voltage is 3.5 V. The measured F/sub min/ is 0.74 dB under I/sub DS/=15 mA and V/sub DS/=2 V.     

p-Channel MOSFET's in LPCVD PolySilicon

p-channel MOSFET's have been fabricated in LPCVD polysilicon. A 5000-Å n⁺poly acts as the gate electrode on which a 500-Å thermal oxide is grown to act as the gate insulator. Then a 1500-Å LPCVD polysilicon layer is deposited at 620°C and is subsequently boron doped to form the conductive channel. Devices with channel length as small as 2 µm show well-behaved transistor characteristics. The drive current and leakage current are as suitable for usage as load element in memory applications. At large gate voltages the accumulation hole mobility is 9 cm²/V.s. The drain-to-source breakdown voltage exceeds -20 V.     

Microwave Performance of Double δ-Doped High Electron Mobility Transistor With Various Lower/Upper Planar-Doped Ratio Designs

The microwave noise, power, and linearity characteristics of pseudomorphic high electron mobility transistors (pHEMTs) with various lower/upper planar delta-doped ratios were systematically evaluated and studied. By varying the lower/upper delta-doped ratio from 1:1 to 1:4, both Schottky gate turn-on voltage V_ON and breakdown voltage V_BR were reduced. In addition, higher upper delta-doped design is effective in improving the device current density, transconductance, output power, and power-added efficiency; however, this design also scarified the flatness of transconductance distribution and Schottky performance, resulting in a degradation of device linearity. As to the noise performance, after increasing the upper delta-doped concentration by more than 2 times 10¹² cm^-2, the minimum noise figure NF_min can be reduced to a stable range, and higher current density cannot efficiently improve the noise performance. Although the 1:4 design provided the largest power density of pHEMT, its high gate leakage current at high input power swing limited its linearity, and 1:3 design achieved the best linearity performance.     

Temperature-dependence investigation of a high-performance inverteddelta-doped V-shaped GaInP/InxGa1-xAs/GaAspseudomorphic high electron mobility transistor

A newly designed inverted delta-doped V-shaped GaInP/In_xGa_1-xAs/GaAs pseudomorphic high electron mobility transistor (PHEMT) has been successfully fabricated and studied. For a 1×100 μm² device, a high gate-to-drain breakdown voltage over 30 V at 300 K is found. In addition, a maximum transconductance of 201 mS/mm with a broad operation regime for 3 V of gate bias (565 mA/mm of drain current density), a very high output drain saturation current density of 826 mA/mm, and a high DC gain ratio of 575 are obtained. Furthermore, good temperature-dependent performances at the operating temperature ranging from 300 to 450 K are found. The unity current gain cutoff frequency f_T and maximum oscillation frequency f_max up to 16 and 34 GHz are obtained, respectively. Meanwhile, the studied device shows the significantly wide and flat gate bias operation regime (3 V) for microwave performances     

A novel simplified process for fabricating a very high densityp-channel trench gate power MOSFET

A novel simplified fabrication method of a very high density p-channel trench gate power MOSFET using four mask layers and nitride/TEOS sidewall spacers is realized. The proposed process showed improved on-resistance characteristics of the device with increasing cell density and the cost-effective production capability due to the lesser number of processing steps. By using this process technique, a remarkably increased high density (100 Mcell/inch²) trench gate power MOSFET with a cell pitch of 2.5 μm could be effectively realized. The fabricated device had a low specific on-resistance of 1.1 mΩ-cm² with a breakdown voltage of -36 V     

The impact of oxidation of channel polysilicon on the trap-densityof submicron bottom-gate TFT's

Oxidation of channel polysilicon improves characteristics of narrow channel TFT's, especially in leakage current. Small leakage current of less than -20 fA/μm and high on/off ratio of about 7 orders of magnitude at a drain voltage of -3.3 V have been achieved by this method. By the analysis of trap densities, leakage current reduction in the oxidized TFT is attributed to the oxidation encroachment under the channel polysilicon which results in a decrease of interface-state density from 5×10¹¹/cm² to about 10¹⁰/cm² at both gate side and back side of the channel polysilicon. It is pointed out that interface state is in some cases more responsible for device degradation than bulk traps and that the reduction of interface states is indispensable to improving device characteristics. This method is directly applicable to TFT load SRAM's in which TFT width is less than 0.5 μm     

一种低功耗4H-SiC IGBT的仿真研究

针对传统沟槽栅4H-SiC IGBT关断时间长且关断能量损耗高的问题,文中利用Silvaco TCAD设计并仿真了一种新型沟槽栅4H-SiC IGBT结构。通过在传统沟槽栅4H-SiC IGBT结构基础上进行改进,在N ⁺缓冲层中引入两组高掺杂浓度P区和N区,提高了N ⁺缓冲层施主浓度,折中了器件正向压降与关断能量损耗。在器件关断过程中,N ⁺缓冲层中处于反向偏置状态的PN结对N ^-漂移区中电场分布起到优化作用,加速了N ^-漂移区中电子抽取,在缩短器件关断时间和降低关断能量损耗的同时提升了击穿电压。Silvaco TCAD仿真结果显示,新型沟槽栅4H-SiC IGBT击穿电压为16 kV,在15 kV的耐压设计指标下,关断能量损耗低至4.63 mJ,相比传统结构降低了40.41%。     

High-Temperature Operation of AlGaN/GaN HFET With a Low on-State Resistance, High Breakdown Voltage, and Fast Switching

Improved characteristics of an AlGaN/GaN HFET are reported. In this paper, the authors introduce a new ohmic electrode of Ti/AlSi/Mo and a low refractive index SiN_x to decrease the contact resistance and gate leakage current. The AlGaN/GaN HFET showed a low specific resistance of 6.3 mOmega middot cm² and a high breakdown voltage of 750 V. The switching characteristics of an AlGaN/GaN HFET are investigated. The small turn-on delay of 7.2 ns, which was one-tenth of Si MOSFETs, was measured. The switching operation of the HFET showed no significant degradation up to 225 degC     

Metamorphic In0.4Al0.6As/In0.4Ga0.6As HEMTs on GaAs substrate

New In_0.4Al_0.6As/In_0.4Ga_0.6 As metamorphic (MM) high electron mobility transistors (HEMTs) have been successfully fabricated on GaAs substrate with T-shaped gate lengths varying from 0.1 to 0.25 μm. The Schottky characteristics are a forward turn-on voltage of 0.7 V and a gate breakdown voltage of -10.5 V. These new MM-HEMTs exhibit typical drain currents of 600 mA/mm and extrinsic transconductance superior to 720 mS/mm. An extrinsic current cutoff frequency f_T of 195 GHz is achieved with the 0.1-μm gate length device. These results are the first reported for In_0.4 Al_0.6As/In_0.4Ga_0.6As MM-HEMTs on GaAs substrate