基于故障物理的电子产品可靠性仿真分析方法

基于故障物理的电子产品可靠性仿真分析方法首先对产品进行故障模式、机理与影响分析（FMMEA）,得到所有潜在故障点的故障模式、机理与对应的物理模型.利用产品材料、结构、工艺、应力等参数建立产品的仿真数字模型,并进行应力分析,利用概率故障物理（PPoF）模型进行损伤分析,得到各潜在故障的寿命分布.最后利用时间竞争的原理对其进行数据融合,得到产品故障率、平均故障间隔时间（MTBF）等可靠性指标.通过某型单板计算机的可靠性仿真过程说明了该方法的实施流程.这种基于故障物理的可靠性仿真的方法从微观角度将可靠性与产品的结构、材料及所承受的应力联系在一起,有助于发现产品的薄弱环节并采取切实有效的措施,是目前基于手册数据的可靠性预计方法的有益补充.     

An improved reliability model for Si and GaN power FET

The existing standard reliability models for power devices are not satisfactory and they fall short of predicting failure rates or wear-out lifetime of semiconductor products. This is mainly attributed to two reasons; the lack of a unified approach for predicting device failure rates and the fact that all commercial reliability evaluation methods relay on the acceleration of one dominant failure mechanism. Recently, device reliability research programs are aimed to develop new theoretical models and experimental methods that would result a better assessment of the device lifetime as well as point out on the dominating failure mechanism for particular operating conditions. A new model, named Multi failure mechanism, Overstress Life test (MOL) has been introduced and posed a better understanding of the dominating failure mechanisms under various stressed conditions in advanced FPGA devices (for 45 and 28 nm technologies). In this work we present, for the first time, the implementation of the MOL model to investigate the reliability of silicon power MOSFET and GaN power FET devices. Both, LTSpice simulation and experimental data are presented for a test circuit of a ring oscillator, based on CMOS-FET, NMOS-FET, PMOS-FET and N-channel e-GaN FET. The monitored data was acquired in-situ in form of the ring frequency or Vds values that enabled to assess the lifetime and determine the dominating mechanism during accelerated wearout by temperature, applied bias voltage, thermal cycling, gamma and electron irradiation. Moreover, in the case of GaN devices, RDS-On monitoring circuit has also been operated during thermal cycling of the tested component and the acceleration factor was derived for various operational parameters.     

Power cycling test and failure analysis of molded Intelligent Power IGBT Module under different temperature swing durations

Molded IGBT modules are widely used in low power motor drive applications due to their advantage like compactness, low cost, and high reliability. Thermo-mechanical stress is generally the main cause of degradation of IGBT modules and thus much research has been performed to investigate the effect of temperature stresses on IGBT modules such as temperature swing and steady-state temperature. The temperature swing duration is also an important factor from a real application point of view, but there is a still lack of quantitative study. In this paper, the impact of temperature swing duration on the lifetime of 600 V, 30 A, 3-phase molded Intelligent Power Modules (IPM) and their failure mechanisms are investigated. The study is based on the accelerated power cycling test results of 36 samples under 6 different conditions and tests are performed under realistic electrical conditions by an advanced power cycling test setup. The results show that the temperature swing duration has a significant effect on the lifetime of IGBT modules. Longer temperature swing duration leads to the smaller number of cycles to failure. Further, it also shows that the bond-wire crack is the main failure mechanism of the tested IGBT modules.     

Layout analysis as supporting tool for failure localization: Basic principles and case studies

To be able to localize a defect on results obtained by failure analysis tools like emission microscopy or OBIRCH analysis it is necessary to understand the effect of a certain defect on an integrated circuit, as only some defects can directly be pinpointed by these analysis methods. In the majority of cases, only second order effects are visible, e.g., a floating gate will cause a transistor to emit light. In that case, the failure site differs from the point of emission.While the physical principles of common defects are well understood one has also to consider the layout of an integrated circuit. By matching the failure analysis results obtained by emission microscopy or OBIRCH analysis to the layout and schematics of a failing device it is possible estimate the root cause of the failure. Thus, the failure site can be narrowed down, to be finally able to proceed with the physical analysis for root cause determination.This paper will give an overview of physical failures that can occur and their effects on emission and OBIRCH analysis. These failure modes will then be correlated to the layout of a device in order to be able to estimate the root cause of a failure based on analysis techniques like emission microscopy and OBIRCH analysis. Finally, we will present case studies of successful failure localization based on layout analysis.     

域间路由系统级联失效下的目标失效链路定位方法研究

协同跨平面会话中断攻击(CXPST)通过反复对多条目标关键链路实施低速率拒绝服务攻击(LDoS)造成域间路由系统的级联失效,从而导致互联网的崩溃。在攻击发生的初期,准确定位受攻击的关键链路并进行针对性防御可遏制级联失效的发生。现有定位方法研究主要基于单源假设,没有考虑多条目标链路同时失效对路径撤回的影响,定位准确度受限。针对上述问题,该文提出一种基于加权统计匹配得分的多失效链路定位方法(WSFS),以级联失效攻击目标链路选择策略作为推断基础,将撤销路径长度的倒数作为权重对评分进行加权。基于实际网络拓扑和有利点位置的级联失效攻击仿真实验结果表明,WSFS比目前最优方法平均准确率可提升5.45%。实验结果证明WSFS相比于其他定位方法更适合应对域间路由系统级联失效下的目标失效链路定位问题。     

Accelerated stress testing of a-Si:H pixel circuits for AMOLED displays

Electronics reliability testing is traditionally carried out by accelerating the failure mechanisms using high temperature and high stress, and then predicting the real-life performance with the Arrhenius model. Such methods have also been applied to organic light-emitting diode (OLED) testing to predict lifetimes of tens of thousands of hours. However, testing the active matrix OLED thin-film transistor (TFT) backplane is a unique and complex case where standard accelerated testing cannot be directly applied. This is because the failure mechanism of pixel circuits is governed by multiple material and device effects, which are compounded by the self-compensating nature of the circuits. In this paper, we define and characterize the factors affecting the primary failure mechanism and develop a general method for accelerated stress testing of TFT pixel circuits in a-Si AMOLED displays. The acceleration factors derived are based on high electrical and temperature stress, and can be used to significantly reduce the testing time required to guarantee a 30 000-h display backplane lifespan.     

A self-tuning DVS processor using delay-error detection and correction

In this paper, we present a dynamic voltage scaling (DVS) technique called Razor which incorporates an in situ error detection and correction mechanism to recover from timing errors. We also present the implementation details and silicon measurements results of a 64-bit processor fabricated in 0.18-/spl mu/m technology that uses Razor for supply voltage control. Traditional DVS techniques require significant voltage safety margins to guarantee computational correctness at the worst case combination of process, voltage and temperature conditions, leading to a loss in energy efficiency. In Razor-based DVS, however, the supply voltage is automatically reduced to the point of first failure using the error detection and correction mechanism, thereby eliminating safety margins while still ensuring correct operation. In addition, the supply voltage can be intentionally scaled below the point of first failure of the processor to achieve an optimal tradeoff between energy savings from further voltage reduction and energy overhead from increased error detection and correction activity. We tested and measured savings due to Razor DVS for 33 different dies and obtained an average energy savings of 50% over worst case operating conditions by scaling supply voltage to achieve a 0.1% targeted error rate, at a fixed frequency of 120 MHz.     

An Efficient Multi-Path Self-Organizing Strategy in Internet of Things

In order to improve the organizing performance and fault tolerance of the wireless network protocol GEAR based on the geographical location information in the Internet of things and achieve better energy distribution and conservation effects. This paper proposes a new multipath routing organizing protocol (SMG, Self-organized Multipath GEAR) based on the basic geographic routing protocol GEAR. By two-step organizing, communication empty nodes and communication hole can join the network respectively and energy spreading out and mechanism of dormancy of the multi-path are utilized to spread out and save energy. Meanwhile, this paper presents an approximate estimation algorithm to estimate the number of the nodes in the monitoring region with a certain size and regular shape. The critical path node goes to failure in different times while received packet rate is monitored using the experiment of NS2 simulation and actual hardware. The experiment results show that the improved protocol increases the fault tolerance of the network, reduces the paralysis rate of the network and achieves the effect of energy spreading out and saving, increases the lifetime of the network through a multi-path strategy.     

Probing negative bias temperature instability using a continuum numerical framework: Physics to real world operation

CMOS reliability is facing unprecedented challenges due to the continued scaling of device dimensions. To sustain the current scaling trends, it is imperative to understand the fundamental physics of failure mechanisms. Due to the inherent complexity of these mechanisms, some of the key failure mechanisms can be understood only by a numerical modeling approach. Most failure mechanisms have a characteristic time dependence to failure. Hence in this work, we use a numerical approach to investigate the time dependence of failure mechanism associated with interfacial kinetics at the Si/SiO₂ interface. Several models are critically examined to develop a reaction/diffusion based modeling framework for predicting interface state generation. Our modeling shows reactions at the Si/SiO₂ interface have a direct impact on the time dependence (or time slopes). These time kinetics predictions shed light on the underlying mechanisms behind an technologically important failure mechanism (negative bias temperature instability (NBTI)). In particular, the breaking of an interface SiH bond to release atomic H results in a time slope of 0.25, whereas the release of molecular H₂ results in a time slope of 0.165. Based on this model, we conclude NBTI degradation is dominated by diffusion of neutral molecular hydrogen defects. These models are extended to 2D simulations to study device layout effects. Our simulations suggest differences with device structure (Lgate, Width etc.) and agree with observed experimental results. The developed models are further applied to understand operation under dynamic and static stress.     

Assessing the Soft Error Rate of Digital Architectures Devoted to Operate in Radiation Environment: A Case Studied

The effects of transient bit flips on the operation of processor based architectures is investigated through fault injection experiments performed in the hardware itself by means of the interruption mechanism. Such an approach is based on the execution, as the consequence of an interruption signal assertion, of pieces of code called CEU (Code Emulating Upsets), asynchronously downloaded in a suitable memory area. This paper focuses in the methodology followed to set-up CEU injection experiments on a digital architecture, illustrating it main steps by means of a studied case: the 80C51 microcontroller. Results obtained from automated fault injection sessions performed using the capabilities of a devoted test system, will point out the capabilities and limitations of the studied approach.     

On the effects of temperature on the drop reliability of electronic component boards

The effects of package temperature on failure mechanisms and lifetimes under mechanical shock loading were studied with the help of five different types of high-density packages (a WL-CSP and four CSP-BGAs) assembled on both double-layer and multi-layer FR4 boards. The localized heating of the packages by means of integrated heating elements was utilized in order to produce similar hot spots to those occurring in products in service. The results showed that the temperature can have a significant effect on the lifetimes of component boards under mechanical shock loading but that the effect varied according to the structures of the component boards. The average number of drops to failure of the WL-CSP component boards increased significantly with an increase in the temperature of the package, while the average number of drops to failure of the CSP-BGA component boards generally decreased. On the other hand, the drop reliability of one out of four CSP-BGA component board types was insensitive to temperature.The failure modes and mechanisms were clarified with the help of physical failure analyses that revealed different failure modes in the component boards. Furthermore, depending on the component board type, the primary failure mode may change with temperature from that identified at room temperature. Particular attention was paid to the nucleation and propagation of cracks at different test temperatures. Computational case studies were designed in order to identify the significance of a change in temperature on three factors: (a) the stiffness of the PWB; (b) the strength and elastic modulus of the solder, and (c) the thermomechanical loads. The influences of each factor on the strains and stresses in the proximity of the solder interconnections were evaluated by means of the finite element method. The results of the statistical and physical failure analyses were rationalized with the help of the results from the finite element analyses. They showed that the effects of a change in temperature on the lifetimes of the component boards under mechanical shock loading can be explained by changes in the nucleation site and/or the propagation of cracks. The results presented in this paper point out that single-load reliability tests can form an incomplete understanding of the failure mechanisms in real service environments and modifications to the currently employed reliability test standards that are needed.     

Proxy‐based failure detection in multimedia streaming environments

This paper presents an effective failure‐detection mechanism called the ‘dynamic threshold,’ which has specifically developed for use with multimedia streaming applications. Compared to the conventional failure‐detection methods, which normally use a fixed threshold to detect a server failure, the proposed mechanism detects the failure in an effective and timely manner by using a dynamically adjusted timeout value upon which queries are sent to suspected streaming servers running in a dynamic network environment. The failover mechanism based on the dynamic threshold was implemented in a real streaming environment. The empirical results show that the dynamic threshold mechanism performs better than the conventional method in terms of timeliness, with comparable accuracy. Copyright © 2006 John Wiley & Sons, Ltd.     

Feasibility analysis of phonon lasers

We identify the main reason impeding coherent generation of phonons in solid state - the inherently high density of phonon states. Based on the results of our analysis we formulate a set of conditions that may make phonon lasing practical and point out the most promising mechanism of phonon lasing: LO/spl rarr/LA+TO in InP. We then develop a complete set of phonon laser equations and evaluate the threshold, output power and efficiency of phonon lasers based on InP MESFET. We show that one can obtain high-power 1.26-THz coherent phonon emission with pump power as small as a few milliwatts and up to 5% slope efficiency. Potential applications are also discussed.     

Early-life reliability prediction methodology for integrated circuits

A methodology for predicting early failures due to random process flaws in integrated circuits is proposed. Early failures are not intrinsic failures, and therefore the current practice of extrapolating intrinsic life-test distributions to estimate early-life reliability is incorrect and yields optimistic results. Early failure mechanisms are classified into three categories based on the physical understanding and statistical data available for the mechanism. Subpopulations with defect-related failure distributions are characterized by a knowledge of the effects of defects in category one and using past field return data in category two. The third category, associated with failures due to applied overstress or misuse, iis characterized by field return, technology and design data. Modeling early failures at the ‘micro’ level (subsystem level) is an improvement over the existing practice of characterizing infant mortality based on field returns at the ‘macro’ level (chip level). Using the proposed methodology, process and design improvements can be incorporated in the early failure predictions. Examples showing the application of this methodology are included.     

电子产品金属桥连接的可靠性研究

分析了3种金属桥材料在规定的环境条件下，所产生的热应变、热应力对可靠性的影响和金属桥失效的机理，并通过试验验证了金属桥连接的可靠性。     

6G oriented blockchain based Internet of things data sharing and storage mechanism

Considering the heterogeneity of various IoT system and the single point failure of centralized data-processing platform,a decentralized IoT data sharing and storage method based on blockchain technology was proposed.The block consensus and decentralized storage of shared data were realized through the PoS consensus mechanism.A block layered propagation mechanism between consensus node and verified node was proposed based on the Gossip protocol.The block propagation delay model and decentralization evaluation model of blockchain networks were derived.The trade-off between the block propagation delay and the decentralization degree of networks was analyzed.The simulation results demonstrate that the block propagation delay and degree of network decentralization decrease with the increase of minimal capabilities of consensus nodes.As an application example,in the trajectory data sharing scenario of confirmed patients,the data sharing smart contract is implemented and tested based on the Ethereum development platform.     

多模计数器静电放电损伤的失效分析

静电放电(ESD)损伤会降低半导体器件和集成电路的可靠性并导致其性能退化.针对一款国产2-32型多模计数器的失效现象,通过分析该计数器的电路结构,利用X射线成像、显微红外热成像、光束感生电阻变化以及钝化层、金属化层去除等技术对计数器进行了失效分析,将失效点准确定位至输出端口逻辑单元电路的2只晶体管上.分析结果表明,多模计数器的ESD损伤使输出端口驱动晶体管以及为负载晶体管提供栅偏置的前级电路晶体管同时受损,导致计数器端口高、低电平输出均失效而丧失计数功能.对相关的失效机理展开了讨论,同时提出了在电路研制和使用过程中的ESD防护措施.     

VDMOSFET HEF degradation modelling considering turn-around phenomenon

Gate oxide failure of power VDMOSFET has been researched for a long time. For BTI parameter degradation, some models are proposed. However, the degradation modelling of HEF still have challenges, one of which is the turn-around phenomenon. Due to the existence of the turn-around point, the threshold voltage degradation model under HEF cannot be described using classical models. Aiming at this problem, the experimental study and the argument are proposed in this paper. First, the theoretical model assumption is discussed based on the degradation mechanism. Second, the HEF stress experiments are carried out to acquire experimental data. Then the model fitting is processed. A three-phase model is proposed to describe threshold voltage degradation under HEF stress.     

局部阴影下光伏阵列最大功率点跟踪算法的研究

在局部阴影条件下,光伏阵列的功率-电压（P-V）特性曲线呈现多峰现象,传统的最大功率点跟踪方法容易受困于局部最大功率点,造成输出功率的损失。提出了基于布谷鸟搜索算法（cuckoo search,CS）的MPPT新方法,利用Lévy飞行搜索机制快速、有效的跳出局部最优的束缚,完成对全局最大功率点的跟踪。仿真和实验验证了该方法的可行性和有效性。     

Modeling early failure in integrated circuit interconnect

A model based on the random electron–atom scattering is developed to characterize the effects of defects and grain sizes on electromigration caused failure in confined sub-micron metal interconnect lines. Our study shows that lines at sub-micron widths with a more uniform microstructure exhibit a greater consistency in time to failure. Taking mean time to failure and dispersion in time to failure as criteria, the simulator predicts that grain sizes in the 0.03–0.05 μm range are optimal for 0.125 μm wide Al alloy lines. We also argue that the early failure mechanism associated with the missing metal defects is eliminated by using a homogeneous, fine-grained material. The uniformity of the structure results in a mono-modal failure distribution and contributes to increasing the built-in reliability of the interconnect lines.