SOI电路可靠性筛选技术及失效机理研究

可靠性筛选是提高电子产品良率的重要技术手段。针对绝缘体上硅（SOI）技术日益广泛的应用,通过大量实验研究了SOI电路的常用筛选试验,并对失效样品进行了相应的失效机理研究。首先讨论了SOI电路失效模式和筛选方法之间的关系;其次,针对三款SOI电路分别开展了老炼应力、高温贮存及恒定加速度试验来进行可靠性筛选;最后,利用光发射显微镜、扫描电子显微镜、聚焦离子束和激励源诱导故障测试等失效分析手段,对失效样品进行了失效模式及机理分析,揭示了失效根源,为改进工艺、提高SOI电路可靠性提供了依据。     

功率半导体IGBT失效分析与可靠性研究

高端变频空调在实际应用中出现大量外机不工作,经过大量失效主板分析确认是主动式PFC电路中IGBT击穿失效,本文结合大量失效品分析与电路设计分析,对IGBT失效原因及失效机理分析,分析结果表明:经过对IGBT失效分析及IGBT工作电路失效分析及整机相关波形检测、热设计分析、IGBT极限参数检测对比发现IGBT失效由多种原...     

一种硅微波功率三极管的失效分析

描述了硅微波功率三极管的失效模式,给出了器件输出功率与器件耗损功率的关系,得出了微波脉冲电流与有效值的关系,证明了器件在规定的参数范围内能可靠工作,推论了器件失效发生时的状态。指出器件的失效是热电正反馈熔融烧毁所致,是使用问题而不是器件的本质失效;其分析过程对其它器件的失效分析有指导作用。     

SOI专用集成电路的静态电流监测和失效分析

静态电流测试是一种高灵敏度、低成本的集成电路失效分析技术,在集成电路故障检测、可靠性测试及筛选中的应用日益普遍。针对某绝缘体上硅专用集成电路在老炼和热冲击实验后出现的静态电流测试失效现象,结合样品伏安特性、光发射显微镜和扫描电子显微镜等电学和物理失效分析手段,确定了栅氧化层中物理缺陷的存在、位置及类型;结合栅氧化层经时介质击穿原理分析,揭示了样品的主要失效机理,并分析了经时介质击穿失效的根源,为改进工艺、提高电路可靠性提供了依据。     

功率半导体IGBT热击穿失效的可靠性研究

针对变频空调使用缘栅双极型晶体管（IGBT）击穿短路故障进行分析,确认IGBT为过压损坏失效。,空调供电电源出现大的波动影响芯片供电电源质量,电压偏低导致IGBT开通异常,不能及时欠压保护,IGBT长时间处于工作在放大状态,IGBT开通损耗大热击穿失效。本文主要从电路设计,工作环境,模拟验证等方面分析研究,确认IGBT击穿短路失效原因,从设计电路与物料选型优化提升产品工作可靠性。     

集成电路分层的失效分析

在集成电路封装中,分层是一个很普遍的现象,同时又是导致集成电路失效的主要原因之一。所谓分层泛指集成电路封装中不同材料之间的界面分离,以及同种材料内部的空洞。针对不同的封装,总结了扫描声学显微镜及X-ray检测系统（包括2D、 3D）两种无损检测分层现象的方法。并在此基础上,结合失效分析案例,阐述了两种方法在失效分析过程中的应用,以及分层导致集成电路失效的机理。     

FIB与PEM联用在半导体器件失效分析中的应用

在半导体器件的失效分析中,缺陷定位是必不可少的重要环节.光发射显微镜(PEM)是IC失效定位中最有效的工具之一.PEM利用了IC器件缺陷在一定条件下的发光现象,迅速定位缺陷.而聚焦等离子束(FIB)的定点切割和沉积技术在亚微米级半导体工艺失效分析中扮演着越来越重要的作用.介绍了一种联合使用FIB和PEM进行亚微米级缺陷定位的新方法,使得一些单独使用PEM无法完成缺陷定位的案例得以成功解决.     

高密度陶瓷倒装焊封装可靠性试验开路后的失效定位

陶瓷材料具有优良的综合特性,被广泛应用于高可靠微电子封装.陶瓷倒装焊封装的特殊结构使得对其进行失效分析相较其他传统封装形式更为困难.针对一款在可靠性试验中发生开路的高密度陶瓷倒装焊封装器件,制定了一套从非破坏性到破坏性的试验方案对其进行分析.通过时域反射计(TDR)测试排除了基板内部失效的可能性,通过X射线(X-ray)检测、超声扫描显微镜(SAM)和光学显微分析初步断定失效位置,并最终通过扫描电子显微镜和X射线能谱仪实现了对该器件的准确的失效定位,确定失效位置为基板端镀Ni层.该失效分析方法对其他陶瓷倒装焊封装的失效检测及分析有一定的借鉴意义.     

基于TSV硅转接板封装结构的力学可靠性分析

TSV硅转接板是3D IC封装技术的一项重要应用,其力学可靠性是影响系统集成的关键问题。以某TSV硅转接板封装结构为对象,采用有限元方法开展了封装、服役过程中应力应变特性和热疲劳寿命研究,分析了基板材料对封装结构力学可靠性的影响,提出了基板材料优选思路。论文提出的分析方法可用作此类封装结构设计优化以及结构力学可靠性初步验证的手段,可以提高设计效率,缩短研制周期。     

BGA制作与组装工艺研究

本文重点介绍在LTCC基板和Al2O3陶瓷基板的底部制作BGA焊球端子的上艺，进而研究BGA器件的组装方法与检测要求。     

High-performance GaAs metal insulator semiconductor transistor

Proton bombardment techniques have been used to fabricate GaAs metal insulator semiconductor transistors (MIST's) with good thermal stability and radiation hardened performance. Highly stable insulator layers have been obtained using both single-species (H1+) and multiple-species (H1+, H2+, O+, and OH+) beams. The device processing is compatible with fabrication of GaAs FET devices in monolithic circuits.     

半导体薄膜晶体管的节能设计方法研究

以往提出的半导体薄膜晶体管的节能设计方法,受到半导体薄膜晶体管不易受控缺陷的影响,节能效果不佳,故提出一种性能更为优异的半导体薄膜晶体管的节能设计方法。概述了半导体薄膜晶体管中电源回路和驱动电路的节能设计原理,并给出终端设备架构设计方案。使用电源回路控制半导体薄膜晶体管供电频率,实现基本节能。利用驱动电路进一步调节电能损耗、管理电源回路的电流谐波,改善半导体薄膜晶体管的开关性能。并以构建模型的方式对电路噪音进行消除,优化储能水平。经实验验证可得,所提方法下的半导体薄膜晶体管拥有优良的开关性能和储能水平,并且节能效果较好。     

Optical semiconductor device reliability

Based on the degradation modes and mechanisms clarified in 1980s and 1990s, reliability of laser diodes and photodiodes is discussed for application to current optical fiber networks such as communication systems employing wavelength-division-multiplexing technique (WDM), high-frequency modulation technique, etc.     

In-situ transistor reliability measurements through nanoprobing

In this study we examine the feasibility of performing transistor reliability measurements with the Hyperion II nanoprobing system. Proof-of-concept bias temperature instability (BTI) measurements were run on a commercially available Intel 14 nm FinFET processor. BTI degradation was found to closely follow the expected power law over 10³ s stress in total at 2 V with characterization done <50 ms into recovery. Examination of 50 SRAM transistors with 30 s stress at 2 V yielded average I_ON reduction of 14.4% (σ = 6.6%) and 6.5% (σ = 2.5%) for pullups and pulldowns, respectively. The in-situ nature of the nanoprobing approach provides insight into transistor lifetime and performance as a function of layout as well as variations in aging between identically designed devices. This is a compelling reason to apply nanoprobing for a range of reliability measurements as a complement to the suite of established reliability testing techniques.     

The Feasibility of creating a high-speed semiconductor—semimetal—semiconductor transistor

The feasibility of creating a semiconductor-semimetal-semiconductor transistor with fast electron transit through its base is considered. Deceased.     

A three dimensional semiconductor device simulator for GaAs/AlGaAsheterojunction bipolar transistor analysis

A three-dimensional semiconductor device simulator was developed to study the steady-state characteristics of heterostructure compound semiconductor devices. The semiconductor partial differential equations-Poisson's equation and the two carrier transport equations-are solved using finite-difference discretization. The Gummel iteration method and indirect space matrix solution techniques are utilized for minimizing computation time and memory requirements. This simulator was applied to the analysis of heterojunction bipolar transistors. The effect of emitter grading on the current-voltage characteristic is demonstrated. A comparison between two- and three-dimensional simulations is also presented. The results show that three-dimensional analysis is indispensable, in particular for devices of small geometry     

New semiconductor active device: the conductivity-controlled transistor

A new semiconductor 3-terminal device has been realised in which a majority-carrier current, flowing in a N+-N-N+ structure, is controlled by a minority-carrier current supplied by a forward-biased P+-N junction. The properties of this device are presented and discussed in terms of a physical model.     

Modulating transistor: a new class of semiconductor device

A new negative resistance transistor n+-p-p?-p structure, consisting of four layers with three electrodes, is reported. The negative resistance effect is due to bulk conductivity modulation. Common emitter, common collector and common base characteristics are described.     

Historical review of compound semiconductor reliability

This discussion is meant to look back at reliability progress over the last thirty years and identify trends and shortcomings. The main body of published work came from the ROCS workshop. While the workshop addresses various specific issues individually, it is the accumulation of a variety of data, information, and experience which forms the basis of an assessment of reliability. In the end, reliability is simply an insightful perception of facts and statistics. After 20-years of workshop meetings and three decades of accumulation of compound semiconductor reliability information, it is time to review, compare, and discuss the progress and the future of reliability for compound semiconductors.